# Dutch (Netherlands) include common map 0x413 exclam 0x02 shift onesuperior 0x02 altgr quotebl 0x03 shift twosuperior 0x03 altgr numbersign 0x04 shift threesuperior 0x04 altgr dollar 0x05 shift onequarter 0x05 altgr percent 0x06 shift onehalf 0x06 altgr ampersand 0x07 shift threequarters 0x07 altgr underscore 0x08 shift sterling 0x08 altgr parenleft 0x09 shift braceleft 0x09 altgr parenright 0x0a shift braceright 0x0a altgr apostrophe 0x0b shift slash 0x0c question 0x0c shift backslash 0x0c altgr degree 0x0d dead_tilde 0x0d shift dead_cedilla 0x0d altgr EuroSign 0x12 altgr paragraph 0x13 altgr dead_diaeresis 0x1a dead_circumflex 0x1a shift asterisk 0x1b bar 0x1b shift ssharp 0x1f altgr plus 0x27 plusminus 0x27 shift dead_acute 0x28 dead_grave 0x28 shift at 0x29 section 0x29 shift notsign 0x29 altgr less 0x2b greater 0x2b shift guillemotleft 0x2c altgr guillemotright 0x2d altgr copyright 0x2e altgr mu 0x32 altgr comma 0x33 semicolon 0x33 shift period 0x34 colon 0x34 shift periodcentered 0x34 altgr hyphen 0x35 equal 0x35 shift bracketright 0x56 bracketleft 0x56 shift brokenbar 0x56 altgr > clone of https://github.com/YosysHQ/yosys
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module TopModule(
    input logic clk,
    input logic rst,
    output logic [21:0] outOther,
    input logic [1:0] sig,
    input logic flip,
    output logic [1:0] sig_out,
    MyInterface.submodule1 interfaceInstanceAtTop,
    output logic [15:0] passThrough);

  MyInterface #(.WIDTH(4)) MyInterfaceInstance();

  SubModule1 u_SubModule1 (
    .clk(clk),
    .rst(rst),
    .u_MyInterface(MyInterfaceInstance),
    .u_MyInterfaceFromTop(interfaceInstanceAtTop),
    .outOther(outOther),
    .sig (sig)
  );

  assign sig_out = MyInterfaceInstance.mysig_out;


  assign MyInterfaceInstance.setting = flip;

  assign passThrough = MyInterfaceInstance.passThrough;

endmodule

interface MyInterface #(
  parameter WIDTH = 3)(
  );

  logic setting;
  logic [WIDTH-1:0] other_setting;

  logic [1:0] mysig_out;

  logic [15:0] passThrough;

    modport submodule1 (
        input  setting,
        output other_setting,
        output mysig_out,
        output passThrough
    );

    modport submodule2 (
        input  setting,
        output other_setting,
        input  mysig_out,
        output passThrough
    );

endinterface


module SubModule1(
    input logic clk,
    input logic rst,
    MyInterface.submodule1 u_MyInterface,
    MyInterface.submodule1 u_MyInterfaceFromTop,
    input logic [1:0] sig,
    output logic [21:0] outOther

  );


  always_ff @(posedge clk or posedge rst)
    if(rst)
      u_MyInterface.mysig_out <= 0;
    else begin
      if(u_MyInterface.setting)
        u_MyInterface.mysig_out <= sig;
      else
        u_MyInterface.mysig_out <= ~sig;
    end

  MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();

  SubModule2 u_SubModule2 (
    .clk(clk),
    .rst(rst),
    .u_MyInterfaceFromTopDown(u_MyInterfaceFromTop),
    .u_MyInterfaceInSub2(u_MyInterface),
    .u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
  );

    assign outOther = MyInterfaceInstanceInSub.other_setting;

    assign MyInterfaceInstanceInSub.setting = 0;
    assign MyInterfaceInstanceInSub.mysig_out = sig;

endmodule

module SubModule2(

    input logic clk,
    input logic rst,
    MyInterface.submodule2 u_MyInterfaceInSub2,
    MyInterface.submodule1 u_MyInterfaceFromTopDown,
    MyInterface.submodule2 u_MyInterfaceInSub3

  );

  assign u_MyInterfaceFromTopDown.mysig_out = u_MyInterfaceFromTop.setting ? 10 :  20;

   always_comb begin
      if (u_MyInterfaceInSub3.mysig_out == 2'b00)
        u_MyInterfaceInSub3.other_setting[21:0] = 1000;
      else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
        u_MyInterfaceInSub3.other_setting[21:0] = 2000;
      else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
        u_MyInterfaceInSub3.other_setting[21:0] = 3000;
      else
        u_MyInterfaceInSub3.other_setting[21:0] = 4000;
   end

    assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
    assign u_MyInterfaceInSub2.passThrough[15:8] = 200;

endmodule