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module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z);
  assign x = -$signed({1'b0, a});
  assign y = $signed({1'b0, a}) + $signed({1'b0, b});
  assign z = x ^ y;
endmodule

module wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w);
  assign x = a - b, y = a * b, z = a >> b, w = a << b;
endmodule
#include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct ScatterPass : public Pass { ScatterPass() : Pass("scatter", "add additional intermediate nets") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" scatter [selection]\n"); log("\n"); log("This command adds additional intermediate nets on all cell ports. This is used\n"); log("for testing the correct use of the SigMap helper in passes. If you don't know\n"); log("what this means: don't worry -- you only need this pass when testing your own\n"); log("extensions to Yosys.\n"); log("\n"); log("Use the opt_clean command to get rid of the additional nets.\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { CellTypes ct(design); extra_args(args, 1, design); for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; for (auto &c : mod_it.second->cells_) for (auto &p : c.second->connections_) { RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size()); if (ct.cell_output(c.second->type, p.first)) { RTLIL::SigSig sigsig(p.second, wire); mod_it.second->connect(sigsig); } else { RTLIL::SigSig sigsig(wire, p.second); mod_it.second->connect(sigsig); } p.second = wire; } } } } ScatterPass; PRIVATE_NAMESPACE_END