1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
|
module TopModule(
input logic clk,
input logic rst,
input logic [1:0] sig,
output logic [1:0] sig_out);
MyInterface #(.WIDTH(4)) MyInterfaceInstance();
SubModule1 u_SubModule1 (
.clk(clk),
.rst(rst),
.u_MyInterface(MyInterfaceInstance),
.sig (sig)
);
assign sig_out = MyInterfaceInstance.mysig_out;
assign MyInterfaceInstance.setting = 1;
assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
endmodule
interface MyInterface #(
parameter WIDTH = 3)(
);
logic setting;
logic [WIDTH-1:0] other_setting;
logic [1:0] mysig_out;
endinterface
module SubModule1(
input logic clk,
input logic rst,
MyInterface u_MyInterface,
input logic [1:0] sig
);
always_ff @(posedge clk or posedge rst)
if(rst)
u_MyInterface.mysig_out <= 0;
else begin
if(u_MyInterface.setting)
u_MyInterface.mysig_out <= sig;
else
u_MyInterface.mysig_out <= ~sig;
end
MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
SubModule2 u_SubModule2 (
.clk(clk),
.rst(rst),
.u_MyInterfaceInSub2(u_MyInterface),
.sig (sig)
);
endmodule
module SubModule2(
input logic clk,
input logic rst,
MyInterface u_MyInterfaceInSub2,
input logic [1:0] sig
);
endmodule
|
