#!/bin/bash set -ex yosys -p ' read_verilog -formal demo.v prep -flatten -nordff -top demo write_smt2 -wires demo.smt2 flatten demo; delete -output memory_map; opt -full techmap; opt -fast abc -fast -g AND; opt_clean write_aiger -map demo.aim demo.aig ' super_prove demo.aig > demo.aiw yosys-smtbmc --dump-vcd demo.vcd --aig demo demo.smt2 //git.panaceas.org/iCE40/yosys' title='iCE40/yosys Git repository'/>

about summary refs log tree commit diff stats

path: root/tests/errors/syntax_err09.v

blob: 1e472eb94ae9d0283aecd18824b50d5e458ea338 (plain)

1
2
3

module a(input wire x = 1'b0);
endmodule