code_verilog_tutorial_multiply.v « asicworld « tests - iCE40/yosys - [no description]

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module muliply (a,product);
  	  	input [3:0] a;
  	  	output [4:0] product;
  	  	wire [4:0] product;
  	  	 
  	  	assign product  = a << 1;
  	  	 
endmodule

ss="n">build_ffi, compiler_type, extra_link_args with open(os.path.join( os.path.dirname(__file__), "hazmat_src/padding.h" )) as f: types = f.read() with open(os.path.join( os.path.dirname(__file__), "hazmat_src/padding.c" )) as f: functions = f.read() ffi = build_ffi( module_name="_padding", cdef_source=types, verify_source=functions, extra_link_args=extra_link_args(compiler_type()), )