tests/asicworld/code_verilog_tutorial_explicit.v


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generated by cgit v1.2.3 (git 2.25.1) at 2025-08-29 13:03:51 +0000
 

ass="p">, q_bar;
reg q;

assign q_bar = ~q;

always @ (posedge clk)
if (rst == 1'b1) begin
  q <= 0;
end else if (pre == 1'b1) begin
  q <= 1;
end else begin
  q <= d;
end

endmodule