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  | 
module dff ( input d, clk, output reg q );
	  always @( posedge clk )
        q <= d;
endmodule
module dffe( input d, clk, en, output reg q );
    initial begin
        q = 0;
    end
	  always @( posedge clk )
        if ( en )
              q <= d;
endmodule
 
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