tests/anlogic/shifter.v


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module top    (
out,
clk,
in
);
    output [7:0] out;
    input signed clk, in;
    reg signed [7:0] out = 0;

    always @(posedge clk)
	begin
		out    <= out >> 1;
		out[7] <= in;
	end

endmodule