library ieee; use ieee.std_logic_1164.all; entity bug2 is end; architecture this of bug2 is function f return integer is constant cc1: std_logic_vector := "1100"; constant cc2: std_logic_vector := cc1; variable r: std_logic_vector(3 downto 0); begin assert false report "case2-a: "&integer'image(cc1'length) severity note; assert false report "case2-b: "&integer'image(cc2'length) severity note;--This reports "0". Correct one would be "4"! return 0; end; constant c1: std_logic_vector := "1010"; constant c2: std_logic_vector := c1; signal i: integer; begin process begin assert false report "case1-a: "&integer'image(c1'length) severity note; assert false report "case1-b: "&integer'image(c2'length) severity note; i <= f; wait; end process; end; orm'>
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path: root/techlibs/xilinx/tests/test_dsp48_model.sh
blob: 9a73f9b0c3e3bf4a56530947fe5d21d63cf9142a (plain)
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#!/bin/bash
set -ex
if [ -z $ISE_DIR ]; then
	ISE_DIR=/opt/Xilinx/ISE/14.7
fi
sed 's/DSP48 /DSP48_UUT /; /DSP48_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48_model_uut.v
if [ ! -f "test_dsp48_model_ref.v" ]; then
	cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48.v test_dsp48_model_ref.v
fi
for tb in mult_allreg mult_noreg mult_inreg
do
	iverilog -s $tb -s glbl -o test_dsp48_model test_dsp48_model.v test_dsp48_model_uut.v test_dsp48_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v
	vvp -N ./test_dsp48_model
done