aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/intel_alm/common/misc_sim.v
blob: b1f970a21f9a95bfb4134ea45c90c26e9a875d68 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
module MISTRAL_IB((* iopad_external_pin *)  input PAD, output O);
	assign O = PAD;
endmodule

module MISTRAL_OB((* iopad_external_pin *)  output PAD, input I);
	assign PAD = I;
endmodule

module MISTRAL_IO((* iopad_external_pin *)  inout PAD, input I, input OE, output O);
	assign PAD = OE ? I : 1'bz;
	assign O = PAD;
endmodule

// Eventually, we should support clock enables and model them here too.
// For now, CLKENA is used as a basic entry point to global routing.
module MISTRAL_CLKBUF (
	input A,
	(* clkbuf_driver *) output Q
);
	assign Q = A;
endmodule
class="p">, input wire [DATA_WIDTH-1:0] data_in, input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // block_ram `default_nettype none module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) (input wire write_enable, clk, input wire [DATA_WIDTH-1:0] data_in, input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // distributed_ram `default_nettype none module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) (input wire write_enable, clk, input wire [DATA_WIDTH-1:0] data_in, input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; (* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // distributed_ram `default_nettype none module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) (input wire write_enable, clk, input wire [DATA_WIDTH-1:0] data_in, input wire [ADDRESS_WIDTH-1:0] address_in, output wire [DATA_WIDTH-1:0] data_out); localparam WORD = (DATA_WIDTH-1); localparam DEPTH = (2**ADDRESS_WIDTH-1); reg [WORD:0] data_out_r; (* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH]; always @(posedge clk) begin if (write_enable) memory[address_in] <= data_in; data_out_r <= memory[address_in]; end assign data_out = data_out_r; endmodule // distributed_ram