avr/qmk/ChibiOS - [no description]

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author	areviu <areviu.info@gmail.com>	2018-03-19 19:40:09 +0000
committer	areviu <areviu.info@gmail.com>	2018-03-19 19:40:09 +0000
commit	d82f92151f7d0fbc6b34aad78e0e02da0a619057 (patch)
tree	97211273ae990a3ab60852e023960039ae6ae109 /os/hal/src/hal_mac.c
parent	badec871127cc434bdb83a54c2a4d7dde26b073f (diff)
download	ChibiOS-d82f92151f7d0fbc6b34aad78e0e02da0a619057.tar.gz ChibiOS-d82f92151f7d0fbc6b34aad78e0e02da0a619057.tar.bz2 ChibiOS-d82f92151f7d0fbc6b34aad78e0e02da0a619057.zip

update hal crypto sha lld, added integration with wolfcrypt

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11824 110e8d01-0319-4d1e-a829-52ad28d1bb01

Diffstat (limited to 'os/hal/src/hal_mac.c')

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module LUT1(output F, input I0); parameter [1:0] INIT = 0; assign F = I0 ? INIT[1] : INIT[0]; endmodule module LUT2(output F, input I0, I1); parameter [3:0] INIT = 0; wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; assign F = I0 ? s1[1] : s1[0]; endmodule module LUT3(output F, input I0, I1, I2); parameter [7:0] INIT = 0; wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign F = I0 ? s1[1] : s1[0]; endmodule module LUT4(output F, input I0, I1, I2, I3); parameter [15:0] INIT = 0; wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign F = I0 ? s1[1] : s1[0]; endmodule module DFF (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; always @(posedge CLK) Q <= D; endmodule module DFFN (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; always @(negedge CLK) Q <= D; endmodule module DFFR (output reg Q, input D, CLK, RESET); parameter [0:0] INIT = 1'b0; initial Q = INIT; always @(posedge CLK) begin if (RESET) Q <= 1'b0; else Q <= D; end endmodule // DFFR (positive clock edge; synchronous reset) module VCC(output V); assign V = 1; endmodule module GND(output G); assign G = 0; endmodule module IBUF(output O, input I); assign O = I; endmodule module OBUF(output O, input I); assign O = I; endmodule module GSR (input GSRI); wire GSRO = GSRI; endmodule module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM); parameter [3:0] ALU_MODE = 0; // default 0 = ADD assign {COUT, SUM} = CIN + I1 + I0; endmodule // alu module RAM16S4 (DO, DI, AD, WRE, CLK); parameter WIDTH = 4; parameter INIT_0 = 16'h0000; parameter INIT_1 = 16'h0000; parameter INIT_2 = 16'h0000; parameter INIT_3 = 16'h0000; input [WIDTH-1:0] AD; input [WIDTH-1:0] DI; output [WIDTH-1:0] DO; input CLK; input WRE; reg [15:0] mem0, mem1, mem2, mem3; initial begin mem0 = INIT_0; mem1 = INIT_1; mem2 = INIT_2; mem3 = INIT_3; end assign DO[0] = mem0[AD]; assign DO[1] = mem1[AD]; assign DO[2] = mem2[AD]; assign DO[3] = mem3[AD]; always @(posedge CLK) begin if (WRE) begin mem0[AD] <= DI[0]; mem1[AD] <= DI[1]; mem2[AD] <= DI[2]; mem3[AD] <= DI[3]; end end endmodule // RAM16S4 (* blackbox *) module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB); //1'b0: Bypass mode; 1'b1 Pipeline mode parameter READ_MODE = 1'b0; parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32 parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32 parameter BLK_SEL = 3'b000; parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; input OCE; // clock enable of memory output register input RESETA, RESETB; // resets output registers, not memory contents input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled input [13:0] ADA, ADB; input [31:0] DI; input [2:0] BLKSEL; output [31:0] DO; endmodule


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