#ifndef __ARM_TYPES_H__ #define __ARM_TYPES_H__ #ifndef __ASSEMBLY__ #include typedef __signed__ char __s8; typedef unsigned char __u8; typedef __signed__ short __s16; typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; #if defined(__GNUC__) && !defined(__STRICT_ANSI__) typedef __signed__ long long __s64; typedef unsigned long long __u64; #endif typedef signed char s8; typedef unsigned char u8; typedef signed short s16; typedef unsigned short u16; typedef signed int s32; typedef unsigned int u32; typedef signed long long s64; typedef unsigned long long u64; typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" typedef unsigned long size_t; typedef char bool_t; #define test_and_set_bool(b) xchg(&(b), 1) #define test_and_clear_bool(b) xchg(&(b), 0) #endif /* __ASSEMBLY__ */ #define BITS_PER_LONG 32 #define BYTES_PER_LONG 4 #define LONG_BYTEORDER 2 #endif /* __ARM_TYPES_H__ */ /* * Local variables: * mode: C * c-set-style: "BSD" * c-basic-offset: 4 * indent-tabs-mode: nil * End: */ /form> clone of https://github.com/YosysHQ/yosys
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path: root/techlibs/ecp5/latches_map.v
blob: c28f88cf767b32807f3262c7c624dd3d08de10a1 (plain) 
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module \$_DLATCH_N_ (E, D, Q);
  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
  input E, D;
  output Q = !E ? D : Q;
endmodule

module \$_DLATCH_P_ (E, D, Q);
  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
  input E, D;
  output Q = E ? D : Q;
endmodule
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