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Name
Size
-rw-r--r--
.gitignore
71
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APPNOTE_010_Verilog_to_BLIF.tex
17076
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APPNOTE_011_Design_Investigation.tex
46124
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APPNOTE_011_Design_Investigation
1156
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APPNOTE_012_Verilog_to_BTOR.tex
12549
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CHAPTER_Appnotes.tex
1123
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CHAPTER_Approach.tex
6856
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CHAPTER_Auxlibs.tex
1319
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CHAPTER_Auxprogs.tex
817
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CHAPTER_Basics.tex
37565
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CHAPTER_CellLib.tex
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CHAPTER_Eval.tex
13087
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CHAPTER_Eval
281
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CHAPTER_Intro.tex
5054
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CHAPTER_Optimize.tex
13424
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CHAPTER_Overview.tex
26372
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CHAPTER_Prog.tex
1123
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CHAPTER_Prog
147
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CHAPTER_StateOfTheArt.tex
13769
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CHAPTER_StateOfTheArt
725
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CHAPTER_Techmap.tex
5225
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CHAPTER_Verilog.tex
36047
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PRESENTATION_ExAdv.tex
33858
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PRESENTATION_ExAdv
1399
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PRESENTATION_ExOth.tex
6925
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PRESENTATION_ExOth
309
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PRESENTATION_ExSyn.tex
18761
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PRESENTATION_ExSyn
1033
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PRESENTATION_Intro.tex
32616
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PRESENTATION_Intro
225
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PRESENTATION_Prog.tex
21331
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PRESENTATION_Prog
192
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appnotes.sh
478
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-rwxr-xr-x
clean.sh
140
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command-reference-manual.tex
148195
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literature.bib
6437
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manual.sh
818
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manual.tex
6828
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presentation.sh
808
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presentation.tex
4716
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-rw-r--r--
weblinks.bib
3670
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