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\begin{center}
\bf\Huge Yosys Manual
\bigskip
\large Clifford Wolf
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\chapter*{Abstract}
Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
with the help of HDL synthesis tools.
In special cases such as synthesis for coarse-grain cell libraries or when
testing new synthesis algorithms it might be necessary to write a custom HDL
synthesis tool or add new features to an existing one. It this cases the
availability of a Free and Open Source (FOSS) synthesis tool that can be used
as basis for custom tools would be helpful.
In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was
developped. This document covers the design and implementation of this tool.
At the moment the main focus of Yosys lies on the high-level aspects of
digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used
by Yosys to perform advanced gate-level optimizations.
An evaluation of Yosys based on real-world designs is included. It is shown
that Yosys can be used as-is to synthesize such designs. The results produced
by Yosys in this tests where successflly verified using formal verification
and are comparable in quality to the results produced by a commercial
synthesis tool.
\bigskip
This document was originally published as bachelor thesis at the Vienna
University of Technology \cite{BACC}.
\chapter*{Abbreviations}
\begin{tabular}{ll}
AIG & And-Inverter-Graph \\
ASIC & Application-Specific Integrated Circuit \\
AST & Abstract Syntax Tree \\
BDD & Binary Decicion Diagram \\
BLIF & Berkeley Logic Interchange Format \\
EDA & Electronic Design Automation \\
EDIF & Electronic Design Interchange Format \\
ER Diagram & Entity-Relationship Diagram \\
FOSS & Free and Open-Source Software \\
FPGA & Field-Programmable Gate Array \\
FSM & Finite-state machine \\
HDL & Hardware Description Language \\
LPM & Library of Parameterized Modules \\
RTLIL & RTL Intermediate Language \\
RTL & Register Transfer Level \\
SAT & Satisfiability Problem \\
% SSA & Static Single Assignment Form \\
VHDL & VHSIC Hardware Description Language \\
VHSIC & Very-High-Speed Integrated Circuit \\
YOSYS & Yosys Open SYnthesis Suite \\
\end{tabular}
\tableofcontents
\include{CHAPTER_Intro}
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\include{CHAPTER_Overview}
\include{CHAPTER_CellLib}
\include{CHAPTER_Prog}
\include{CHAPTER_Verilog}
\include{CHAPTER_Optimize}
\include{CHAPTER_Techmap}
\include{CHAPTER_Eval}
\appendix
\include{CHAPTER_Auxlibs}
\include{CHAPTER_Auxprogs}
\chapter{Command Reference Manual}
\label{commandref}
\input{command-reference-manual}
\include{CHAPTER_Appnotes}
\include{CHAPTER_StateOfTheArt}
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