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<a id='n359' href='#n359'>359</a>
<a id='n360' href='#n360'>360</a>
<a id='n361' href='#n361'>361</a>
<a id='n362' href='#n362'>362</a>
<a id='n363' href='#n363'>363</a>
<a id='n364' href='#n364'>364</a>
<a id='n365' href='#n365'>365</a>
<a id='n366' href='#n366'>366</a>
<a id='n367' href='#n367'>367</a>
<a id='n368' href='#n368'>368</a>
<a id='n369' href='#n369'>369</a>
<a id='n370' href='#n370'>370</a>
<a id='n371' href='#n371'>371</a>
<a id='n372' href='#n372'>372</a>
<a id='n373' href='#n373'>373</a>
<a id='n374' href='#n374'>374</a>
<a id='n375' href='#n375'>375</a>
<a id='n376' href='#n376'>376</a>
<a id='n377' href='#n377'>377</a>
<a id='n378' href='#n378'>378</a>
<a id='n379' href='#n379'>379</a>
<a id='n380' href='#n380'>380</a>
<a id='n381' href='#n381'>381</a>
<a id='n382' href='#n382'>382</a>
<a id='n383' href='#n383'>383</a>
<a id='n384' href='#n384'>384</a>
<a id='n385' href='#n385'>385</a>
<a id='n386' href='#n386'>386</a>
<a id='n387' href='#n387'>387</a>
<a id='n388' href='#n388'>388</a>
<a id='n389' href='#n389'>389</a>
<a id='n390' href='#n390'>390</a>
<a id='n391' href='#n391'>391</a>
<a id='n392' href='#n392'>392</a>
<a id='n393' href='#n393'>393</a>
<a id='n394' href='#n394'>394</a>
<a id='n395' href='#n395'>395</a>
<a id='n396' href='#n396'>396</a>
<a id='n397' href='#n397'>397</a>
<a id='n398' href='#n398'>398</a>
<a id='n399' href='#n399'>399</a>
<a id='n400' href='#n400'>400</a>
<a id='n401' href='#n401'>401</a>
<a id='n402' href='#n402'>402</a>
<a id='n403' href='#n403'>403</a>
<a id='n404' href='#n404'>404</a>
<a id='n405' href='#n405'>405</a>
<a id='n406' href='#n406'>406</a>
<a id='n407' href='#n407'>407</a>
<a id='n408' href='#n408'>408</a>
<a id='n409' href='#n409'>409</a>
<a id='n410' href='#n410'>410</a>
<a id='n411' href='#n411'>411</a>
<a id='n412' href='#n412'>412</a>
<a id='n413' href='#n413'>413</a>
<a id='n414' href='#n414'>414</a>
<a id='n415' href='#n415'>415</a>
<a id='n416' href='#n416'>416</a>
<a id='n417' href='#n417'>417</a>
<a id='n418' href='#n418'>418</a>
<a id='n419' href='#n419'>419</a>
<a id='n420' href='#n420'>420</a>
<a id='n421' href='#n421'>421</a>
<a id='n422' href='#n422'>422</a>
<a id='n423' href='#n423'>423</a>
<a id='n424' href='#n424'>424</a>
<a id='n425' href='#n425'>425</a>
<a id='n426' href='#n426'>426</a>
<a id='n427' href='#n427'>427</a>
<a id='n428' href='#n428'>428</a>
<a id='n429' href='#n429'>429</a>
<a id='n430' href='#n430'>430</a>
<a id='n431' href='#n431'>431</a>
<a id='n432' href='#n432'>432</a>
<a id='n433' href='#n433'>433</a>
<a id='n434' href='#n434'>434</a>
<a id='n435' href='#n435'>435</a>
<a id='n436' href='#n436'>436</a>
<a id='n437' href='#n437'>437</a>
<a id='n438' href='#n438'>438</a>
<a id='n439' href='#n439'>439</a>
<a id='n440' href='#n440'>440</a>
<a id='n441' href='#n441'>441</a>
<a id='n442' href='#n442'>442</a>
<a id='n443' href='#n443'>443</a>
<a id='n444' href='#n444'>444</a>
<a id='n445' href='#n445'>445</a>
<a id='n446' href='#n446'>446</a>
<a id='n447' href='#n447'>447</a>
<a id='n448' href='#n448'>448</a>
<a id='n449' href='#n449'>449</a>
<a id='n450' href='#n450'>450</a>
<a id='n451' href='#n451'>451</a>
<a id='n452' href='#n452'>452</a>
<a id='n453' href='#n453'>453</a>
<a id='n454' href='#n454'>454</a>
<a id='n455' href='#n455'>455</a>
<a id='n456' href='#n456'>456</a>
<a id='n457' href='#n457'>457</a>
<a id='n458' href='#n458'>458</a>
<a id='n459' href='#n459'>459</a>
<a id='n460' href='#n460'>460</a>
<a id='n461' href='#n461'>461</a>
<a id='n462' href='#n462'>462</a>
<a id='n463' href='#n463'>463</a>
<a id='n464' href='#n464'>464</a>
<a id='n465' href='#n465'>465</a>
<a id='n466' href='#n466'>466</a>
<a id='n467' href='#n467'>467</a>
<a id='n468' href='#n468'>468</a>
<a id='n469' href='#n469'>469</a>
<a id='n470' href='#n470'>470</a>
<a id='n471' href='#n471'>471</a>
<a id='n472' href='#n472'>472</a>
<a id='n473' href='#n473'>473</a>
<a id='n474' href='#n474'>474</a>
<a id='n475' href='#n475'>475</a>
<a id='n476' href='#n476'>476</a>
<a id='n477' href='#n477'>477</a>
<a id='n478' href='#n478'>478</a>
<a id='n479' href='#n479'>479</a>
<a id='n480' href='#n480'>480</a>
<a id='n481' href='#n481'>481</a>
<a id='n482' href='#n482'>482</a>
<a id='n483' href='#n483'>483</a>
<a id='n484' href='#n484'>484</a>
<a id='n485' href='#n485'>485</a>
<a id='n486' href='#n486'>486</a>
<a id='n487' href='#n487'>487</a>
<a id='n488' href='#n488'>488</a>
<a id='n489' href='#n489'>489</a>
<a id='n490' href='#n490'>490</a>
<a id='n491' href='#n491'>491</a>
<a id='n492' href='#n492'>492</a>
<a id='n493' href='#n493'>493</a>
<a id='n494' href='#n494'>494</a>
<a id='n495' href='#n495'>495</a>
<a id='n496' href='#n496'>496</a>
<a id='n497' href='#n497'>497</a>
<a id='n498' href='#n498'>498</a>
<a id='n499' href='#n499'>499</a>
<a id='n500' href='#n500'>500</a>
<a id='n501' href='#n501'>501</a>
<a id='n502' href='#n502'>502</a>
<a id='n503' href='#n503'>503</a>
<a id='n504' href='#n504'>504</a>
<a id='n505' href='#n505'>505</a>
<a id='n506' href='#n506'>506</a>
<a id='n507' href='#n507'>507</a>
<a id='n508' href='#n508'>508</a>
<a id='n509' href='#n509'>509</a>
<a id='n510' href='#n510'>510</a>
<a id='n511' href='#n511'>511</a>
<a id='n512' href='#n512'>512</a>
<a id='n513' href='#n513'>513</a>
<a id='n514' href='#n514'>514</a>
<a id='n515' href='#n515'>515</a>
<a id='n516' href='#n516'>516</a>
<a id='n517' href='#n517'>517</a>
<a id='n518' href='#n518'>518</a>
<a id='n519' href='#n519'>519</a>
<a id='n520' href='#n520'>520</a>
<a id='n521' href='#n521'>521</a>
<a id='n522' href='#n522'>522</a>
<a id='n523' href='#n523'>523</a>
<a id='n524' href='#n524'>524</a>
<a id='n525' href='#n525'>525</a>
<a id='n526' href='#n526'>526</a>
<a id='n527' href='#n527'>527</a>
<a id='n528' href='#n528'>528</a>
<a id='n529' href='#n529'>529</a>
<a id='n530' href='#n530'>530</a>
<a id='n531' href='#n531'>531</a>
<a id='n532' href='#n532'>532</a>
<a id='n533' href='#n533'>533</a>
<a id='n534' href='#n534'>534</a>
<a id='n535' href='#n535'>535</a>
<a id='n536' href='#n536'>536</a>
<a id='n537' href='#n537'>537</a>
<a id='n538' href='#n538'>538</a>
<a id='n539' href='#n539'>539</a>
<a id='n540' href='#n540'>540</a>
<a id='n541' href='#n541'>541</a>
<a id='n542' href='#n542'>542</a>
<a id='n543' href='#n543'>543</a>
<a id='n544' href='#n544'>544</a>
<a id='n545' href='#n545'>545</a>
<a id='n546' href='#n546'>546</a>
<a id='n547' href='#n547'>547</a>
<a id='n548' href='#n548'>548</a>
<a id='n549' href='#n549'>549</a>
<a id='n550' href='#n550'>550</a>
<a id='n551' href='#n551'>551</a>
<a id='n552' href='#n552'>552</a>
<a id='n553' href='#n553'>553</a>
<a id='n554' href='#n554'>554</a>
<a id='n555' href='#n555'>555</a>
<a id='n556' href='#n556'>556</a>
<a id='n557' href='#n557'>557</a>
<a id='n558' href='#n558'>558</a>
<a id='n559' href='#n559'>559</a>
<a id='n560' href='#n560'>560</a>
<a id='n561' href='#n561'>561</a>
<a id='n562' href='#n562'>562</a>
<a id='n563' href='#n563'>563</a>
<a id='n564' href='#n564'>564</a>
<a id='n565' href='#n565'>565</a>
<a id='n566' href='#n566'>566</a>
<a id='n567' href='#n567'>567</a>
<a id='n568' href='#n568'>568</a>
<a id='n569' href='#n569'>569</a>
<a id='n570' href='#n570'>570</a>
<a id='n571' href='#n571'>571</a>
<a id='n572' href='#n572'>572</a>
<a id='n573' href='#n573'>573</a>
<a id='n574' href='#n574'>574</a>
<a id='n575' href='#n575'>575</a>
<a id='n576' href='#n576'>576</a>
<a id='n577' href='#n577'>577</a>
<a id='n578' href='#n578'>578</a>
<a id='n579' href='#n579'>579</a>
<a id='n580' href='#n580'>580</a>
<a id='n581' href='#n581'>581</a>
<a id='n582' href='#n582'>582</a>
<a id='n583' href='#n583'>583</a>
<a id='n584' href='#n584'>584</a>
<a id='n585' href='#n585'>585</a>
<a id='n586' href='#n586'>586</a>
<a id='n587' href='#n587'>587</a>
<a id='n588' href='#n588'>588</a>
<a id='n589' href='#n589'>589</a>
<a id='n590' href='#n590'>590</a>
<a id='n591' href='#n591'>591</a>
<a id='n592' href='#n592'>592</a>
<a id='n593' href='#n593'>593</a>
<a id='n594' href='#n594'>594</a>
<a id='n595' href='#n595'>595</a>
<a id='n596' href='#n596'>596</a>
<a id='n597' href='#n597'>597</a>
<a id='n598' href='#n598'>598</a>
<a id='n599' href='#n599'>599</a>
<a id='n600' href='#n600'>600</a>
<a id='n601' href='#n601'>601</a>
<a id='n602' href='#n602'>602</a>
<a id='n603' href='#n603'>603</a>
<a id='n604' href='#n604'>604</a>
<a id='n605' href='#n605'>605</a>
<a id='n606' href='#n606'>606</a>
<a id='n607' href='#n607'>607</a>
<a id='n608' href='#n608'>608</a>
<a id='n609' href='#n609'>609</a>
<a id='n610' href='#n610'>610</a>
<a id='n611' href='#n611'>611</a>
<a id='n612' href='#n612'>612</a>
<a id='n613' href='#n613'>613</a>
<a id='n614' href='#n614'>614</a>
<a id='n615' href='#n615'>615</a>
<a id='n616' href='#n616'>616</a>
<a id='n617' href='#n617'>617</a>
<a id='n618' href='#n618'>618</a>
<a id='n619' href='#n619'>619</a>
<a id='n620' href='#n620'>620</a>
<a id='n621' href='#n621'>621</a>
<a id='n622' href='#n622'>622</a>
<a id='n623' href='#n623'>623</a>
<a id='n624' href='#n624'>624</a>
<a id='n625' href='#n625'>625</a>
<a id='n626' href='#n626'>626</a>
<a id='n627' href='#n627'>627</a>
<a id='n628' href='#n628'>628</a>
<a id='n629' href='#n629'>629</a>
<a id='n630' href='#n630'>630</a>
<a id='n631' href='#n631'>631</a>
<a id='n632' href='#n632'>632</a>
<a id='n633' href='#n633'>633</a>
<a id='n634' href='#n634'>634</a>
<a id='n635' href='#n635'>635</a>
<a id='n636' href='#n636'>636</a>
<a id='n637' href='#n637'>637</a>
<a id='n638' href='#n638'>638</a>
<a id='n639' href='#n639'>639</a>
<a id='n640' href='#n640'>640</a>
<a id='n641' href='#n641'>641</a>
<a id='n642' href='#n642'>642</a>
<a id='n643' href='#n643'>643</a>
<a id='n644' href='#n644'>644</a>
<a id='n645' href='#n645'>645</a>
<a id='n646' href='#n646'>646</a>
<a id='n647' href='#n647'>647</a>
<a id='n648' href='#n648'>648</a>
<a id='n649' href='#n649'>649</a>
<a id='n650' href='#n650'>650</a>
<a id='n651' href='#n651'>651</a>
<a id='n652' href='#n652'>652</a>
<a id='n653' href='#n653'>653</a>
<a id='n654' href='#n654'>654</a>
<a id='n655' href='#n655'>655</a>
<a id='n656' href='#n656'>656</a>
<a id='n657' href='#n657'>657</a>
<a id='n658' href='#n658'>658</a>
<a id='n659' href='#n659'>659</a>
<a id='n660' href='#n660'>660</a>
<a id='n661' href='#n661'>661</a>
<a id='n662' href='#n662'>662</a>
<a id='n663' href='#n663'>663</a>
<a id='n664' href='#n664'>664</a>
<a id='n665' href='#n665'>665</a>
<a id='n666' href='#n666'>666</a>
<a id='n667' href='#n667'>667</a>
<a id='n668' href='#n668'>668</a>
<a id='n669' href='#n669'>669</a>
<a id='n670' href='#n670'>670</a>
<a id='n671' href='#n671'>671</a>
<a id='n672' href='#n672'>672</a>
<a id='n673' href='#n673'>673</a>
<a id='n674' href='#n674'>674</a>
<a id='n675' href='#n675'>675</a>
<a id='n676' href='#n676'>676</a>
<a id='n677' href='#n677'>677</a>
<a id='n678' href='#n678'>678</a>
<a id='n679' href='#n679'>679</a>
<a id='n680' href='#n680'>680</a>
<a id='n681' href='#n681'>681</a>
<a id='n682' href='#n682'>682</a>
<a id='n683' href='#n683'>683</a>
<a id='n684' href='#n684'>684</a>
<a id='n685' href='#n685'>685</a>
<a id='n686' href='#n686'>686</a>
<a id='n687' href='#n687'>687</a>
<a id='n688' href='#n688'>688</a>
<a id='n689' href='#n689'>689</a>
<a id='n690' href='#n690'>690</a>
<a id='n691' href='#n691'>691</a>
<a id='n692' href='#n692'>692</a>
<a id='n693' href='#n693'>693</a>
<a id='n694' href='#n694'>694</a>
<a id='n695' href='#n695'>695</a>
<a id='n696' href='#n696'>696</a>
<a id='n697' href='#n697'>697</a>
<a id='n698' href='#n698'>698</a>
<a id='n699' href='#n699'>699</a>
<a id='n700' href='#n700'>700</a>
<a id='n701' href='#n701'>701</a>
<a id='n702' href='#n702'>702</a>
<a id='n703' href='#n703'>703</a>
<a id='n704' href='#n704'>704</a>
<a id='n705' href='#n705'>705</a>
<a id='n706' href='#n706'>706</a>
<a id='n707' href='#n707'>707</a>
<a id='n708' href='#n708'>708</a>
<a id='n709' href='#n709'>709</a>
<a id='n710' href='#n710'>710</a>
<a id='n711' href='#n711'>711</a>
<a id='n712' href='#n712'>712</a>
<a id='n713' href='#n713'>713</a>
<a id='n714' href='#n714'>714</a>
<a id='n715' href='#n715'>715</a>
<a id='n716' href='#n716'>716</a>
<a id='n717' href='#n717'>717</a>
<a id='n718' href='#n718'>718</a>
<a id='n719' href='#n719'>719</a>
<a id='n720' href='#n720'>720</a>
<a id='n721' href='#n721'>721</a>
<a id='n722' href='#n722'>722</a>
<a id='n723' href='#n723'>723</a>
<a id='n724' href='#n724'>724</a>
<a id='n725' href='#n725'>725</a>
<a id='n726' href='#n726'>726</a>
<a id='n727' href='#n727'>727</a>
<a id='n728' href='#n728'>728</a>
<a id='n729' href='#n729'>729</a>
<a id='n730' href='#n730'>730</a>
<a id='n731' href='#n731'>731</a>
<a id='n732' href='#n732'>732</a>
<a id='n733' href='#n733'>733</a>
<a id='n734' href='#n734'>734</a>
<a id='n735' href='#n735'>735</a>
<a id='n736' href='#n736'>736</a>
<a id='n737' href='#n737'>737</a>
<a id='n738' href='#n738'>738</a>
<a id='n739' href='#n739'>739</a>
<a id='n740' href='#n740'>740</a>
<a id='n741' href='#n741'>741</a>
<a id='n742' href='#n742'>742</a>
<a id='n743' href='#n743'>743</a>
<a id='n744' href='#n744'>744</a>
<a id='n745' href='#n745'>745</a>
<a id='n746' href='#n746'>746</a>
<a id='n747' href='#n747'>747</a>
<a id='n748' href='#n748'>748</a>
<a id='n749' href='#n749'>749</a>
<a id='n750' href='#n750'>750</a>
<a id='n751' href='#n751'>751</a>
<a id='n752' href='#n752'>752</a>
<a id='n753' href='#n753'>753</a>
<a id='n754' href='#n754'>754</a>
<a id='n755' href='#n755'>755</a>
<a id='n756' href='#n756'>756</a>
<a id='n757' href='#n757'>757</a>
<a id='n758' href='#n758'>758</a>
<a id='n759' href='#n759'>759</a>
<a id='n760' href='#n760'>760</a>
<a id='n761' href='#n761'>761</a>
<a id='n762' href='#n762'>762</a>
<a id='n763' href='#n763'>763</a>
<a id='n764' href='#n764'>764</a>
<a id='n765' href='#n765'>765</a>
<a id='n766' href='#n766'>766</a>
<a id='n767' href='#n767'>767</a>
<a id='n768' href='#n768'>768</a>
<a id='n769' href='#n769'>769</a>
<a id='n770' href='#n770'>770</a>
<a id='n771' href='#n771'>771</a>
<a id='n772' href='#n772'>772</a>
<a id='n773' href='#n773'>773</a>
<a id='n774' href='#n774'>774</a>
<a id='n775' href='#n775'>775</a>
<a id='n776' href='#n776'>776</a>
<a id='n777' href='#n777'>777</a>
<a id='n778' href='#n778'>778</a>
<a id='n779' href='#n779'>779</a>
<a id='n780' href='#n780'>780</a>
<a id='n781' href='#n781'>781</a>
<a id='n782' href='#n782'>782</a>
<a id='n783' href='#n783'>783</a>
<a id='n784' href='#n784'>784</a>
<a id='n785' href='#n785'>785</a>
<a id='n786' href='#n786'>786</a>
<a id='n787' href='#n787'>787</a>
<a id='n788' href='#n788'>788</a>
<a id='n789' href='#n789'>789</a>
<a id='n790' href='#n790'>790</a>
<a id='n791' href='#n791'>791</a>
<a id='n792' href='#n792'>792</a>
<a id='n793' href='#n793'>793</a>
<a id='n794' href='#n794'>794</a>
<a id='n795' href='#n795'>795</a>
<a id='n796' href='#n796'>796</a>
<a id='n797' href='#n797'>797</a>
<a id='n798' href='#n798'>798</a>
<a id='n799' href='#n799'>799</a>
<a id='n800' href='#n800'>800</a>
<a id='n801' href='#n801'>801</a>
<a id='n802' href='#n802'>802</a>
<a id='n803' href='#n803'>803</a>
<a id='n804' href='#n804'>804</a>
<a id='n805' href='#n805'>805</a>
<a id='n806' href='#n806'>806</a>
<a id='n807' href='#n807'>807</a>
<a id='n808' href='#n808'>808</a>
<a id='n809' href='#n809'>809</a>
<a id='n810' href='#n810'>810</a>
<a id='n811' href='#n811'>811</a>
<a id='n812' href='#n812'>812</a>
<a id='n813' href='#n813'>813</a>
<a id='n814' href='#n814'>814</a>
<a id='n815' href='#n815'>815</a>
<a id='n816' href='#n816'>816</a>
<a id='n817' href='#n817'>817</a>
<a id='n818' href='#n818'>818</a>
<a id='n819' href='#n819'>819</a>
<a id='n820' href='#n820'>820</a>
<a id='n821' href='#n821'>821</a>
<a id='n822' href='#n822'>822</a>
<a id='n823' href='#n823'>823</a>
<a id='n824' href='#n824'>824</a>
<a id='n825' href='#n825'>825</a>
<a id='n826' href='#n826'>826</a>
<a id='n827' href='#n827'>827</a>
<a id='n828' href='#n828'>828</a>
<a id='n829' href='#n829'>829</a>
<a id='n830' href='#n830'>830</a>
<a id='n831' href='#n831'>831</a>
<a id='n832' href='#n832'>832</a>
<a id='n833' href='#n833'>833</a>
<a id='n834' href='#n834'>834</a>
<a id='n835' href='#n835'>835</a>
<a id='n836' href='#n836'>836</a>
<a id='n837' href='#n837'>837</a>
<a id='n838' href='#n838'>838</a>
<a id='n839' href='#n839'>839</a>
<a id='n840' href='#n840'>840</a>
<a id='n841' href='#n841'>841</a>
<a id='n842' href='#n842'>842</a>
<a id='n843' href='#n843'>843</a>
<a id='n844' href='#n844'>844</a>
<a id='n845' href='#n845'>845</a>
<a id='n846' href='#n846'>846</a>
<a id='n847' href='#n847'>847</a>
<a id='n848' href='#n848'>848</a>
<a id='n849' href='#n849'>849</a>
<a id='n850' href='#n850'>850</a>
<a id='n851' href='#n851'>851</a>
<a id='n852' href='#n852'>852</a>
<a id='n853' href='#n853'>853</a>
<a id='n854' href='#n854'>854</a>
<a id='n855' href='#n855'>855</a>
<a id='n856' href='#n856'>856</a>
<a id='n857' href='#n857'>857</a>
<a id='n858' href='#n858'>858</a>
<a id='n859' href='#n859'>859</a>
<a id='n860' href='#n860'>860</a>
<a id='n861' href='#n861'>861</a>
<a id='n862' href='#n862'>862</a>
<a id='n863' href='#n863'>863</a>
<a id='n864' href='#n864'>864</a>
<a id='n865' href='#n865'>865</a>
<a id='n866' href='#n866'>866</a>
<a id='n867' href='#n867'>867</a>
<a id='n868' href='#n868'>868</a>
<a id='n869' href='#n869'>869</a>
<a id='n870' href='#n870'>870</a>
<a id='n871' href='#n871'>871</a>
<a id='n872' href='#n872'>872</a>
<a id='n873' href='#n873'>873</a>
<a id='n874' href='#n874'>874</a>
<a id='n875' href='#n875'>875</a>
<a id='n876' href='#n876'>876</a>
<a id='n877' href='#n877'>877</a>
<a id='n878' href='#n878'>878</a>
<a id='n879' href='#n879'>879</a>
<a id='n880' href='#n880'>880</a>
<a id='n881' href='#n881'>881</a>
<a id='n882' href='#n882'>882</a>
<a id='n883' href='#n883'>883</a>
<a id='n884' href='#n884'>884</a>
<a id='n885' href='#n885'>885</a>
<a id='n886' href='#n886'>886</a>
<a id='n887' href='#n887'>887</a>
<a id='n888' href='#n888'>888</a>
<a id='n889' href='#n889'>889</a>
<a id='n890' href='#n890'>890</a>
<a id='n891' href='#n891'>891</a>
<a id='n892' href='#n892'>892</a>
<a id='n893' href='#n893'>893</a>
<a id='n894' href='#n894'>894</a>
<a id='n895' href='#n895'>895</a>
<a id='n896' href='#n896'>896</a>
<a id='n897' href='#n897'>897</a>
<a id='n898' href='#n898'>898</a>
<a id='n899' href='#n899'>899</a>
<a id='n900' href='#n900'>900</a>
<a id='n901' href='#n901'>901</a>
<a id='n902' href='#n902'>902</a>
<a id='n903' href='#n903'>903</a>
<a id='n904' href='#n904'>904</a>
<a id='n905' href='#n905'>905</a>
<a id='n906' href='#n906'>906</a>
<a id='n907' href='#n907'>907</a>
<a id='n908' href='#n908'>908</a>
<a id='n909' href='#n909'>909</a>
<a id='n910' href='#n910'>910</a>
<a id='n911' href='#n911'>911</a>
<a id='n912' href='#n912'>912</a>
<a id='n913' href='#n913'>913</a>
<a id='n914' href='#n914'>914</a>
<a id='n915' href='#n915'>915</a>
<a id='n916' href='#n916'>916</a>
<a id='n917' href='#n917'>917</a>
<a id='n918' href='#n918'>918</a>
<a id='n919' href='#n919'>919</a>
<a id='n920' href='#n920'>920</a>
<a id='n921' href='#n921'>921</a>
<a id='n922' href='#n922'>922</a>
<a id='n923' href='#n923'>923</a>
<a id='n924' href='#n924'>924</a>
<a id='n925' href='#n925'>925</a>
<a id='n926' href='#n926'>926</a>
<a id='n927' href='#n927'>927</a>
<a id='n928' href='#n928'>928</a>
<a id='n929' href='#n929'>929</a>
<a id='n930' href='#n930'>930</a>
<a id='n931' href='#n931'>931</a>
<a id='n932' href='#n932'>932</a>
<a id='n933' href='#n933'>933</a>
<a id='n934' href='#n934'>934</a>
<a id='n935' href='#n935'>935</a>
<a id='n936' href='#n936'>936</a>
<a id='n937' href='#n937'>937</a>
<a id='n938' href='#n938'>938</a>
<a id='n939' href='#n939'>939</a>
<a id='n940' href='#n940'>940</a>
<a id='n941' href='#n941'>941</a>
<a id='n942' href='#n942'>942</a>
<a id='n943' href='#n943'>943</a>
<a id='n944' href='#n944'>944</a>
<a id='n945' href='#n945'>945</a>
<a id='n946' href='#n946'>946</a>
<a id='n947' href='#n947'>947</a>
<a id='n948' href='#n948'>948</a>
<a id='n949' href='#n949'>949</a>
<a id='n950' href='#n950'>950</a>
<a id='n951' href='#n951'>951</a>
<a id='n952' href='#n952'>952</a>
<a id='n953' href='#n953'>953</a>
<a id='n954' href='#n954'>954</a>
<a id='n955' href='#n955'>955</a>
<a id='n956' href='#n956'>956</a>
<a id='n957' href='#n957'>957</a>
<a id='n958' href='#n958'>958</a>
<a id='n959' href='#n959'>959</a>
<a id='n960' href='#n960'>960</a>
<a id='n961' href='#n961'>961</a>
<a id='n962' href='#n962'>962</a>
<a id='n963' href='#n963'>963</a>
<a id='n964' href='#n964'>964</a>
<a id='n965' href='#n965'>965</a>
<a id='n966' href='#n966'>966</a>
<a id='n967' href='#n967'>967</a>
<a id='n968' href='#n968'>968</a>
<a id='n969' href='#n969'>969</a>
<a id='n970' href='#n970'>970</a>
<a id='n971' href='#n971'>971</a>
<a id='n972' href='#n972'>972</a>
<a id='n973' href='#n973'>973</a>
<a id='n974' href='#n974'>974</a>
<a id='n975' href='#n975'>975</a>
<a id='n976' href='#n976'>976</a>
<a id='n977' href='#n977'>977</a>
<a id='n978' href='#n978'>978</a>
<a id='n979' href='#n979'>979</a>
<a id='n980' href='#n980'>980</a>
<a id='n981' href='#n981'>981</a>
<a id='n982' href='#n982'>982</a>
<a id='n983' href='#n983'>983</a>
<a id='n984' href='#n984'>984</a>
<a id='n985' href='#n985'>985</a>
<a id='n986' href='#n986'>986</a>
<a id='n987' href='#n987'>987</a>
<a id='n988' href='#n988'>988</a>
<a id='n989' href='#n989'>989</a>
<a id='n990' href='#n990'>990</a>
<a id='n991' href='#n991'>991</a>
<a id='n992' href='#n992'>992</a>
<a id='n993' href='#n993'>993</a>
<a id='n994' href='#n994'>994</a>
<a id='n995' href='#n995'>995</a>
<a id='n996' href='#n996'>996</a>
<a id='n997' href='#n997'>997</a>
<a id='n998' href='#n998'>998</a>
<a id='n999' href='#n999'>999</a>
<a id='n1000' href='#n1000'>1000</a>
<a id='n1001' href='#n1001'>1001</a>
<a id='n1002' href='#n1002'>1002</a>
<a id='n1003' href='#n1003'>1003</a>
<a id='n1004' href='#n1004'>1004</a>
<a id='n1005' href='#n1005'>1005</a>
<a id='n1006' href='#n1006'>1006</a>
<a id='n1007' href='#n1007'>1007</a>
<a id='n1008' href='#n1008'>1008</a>
<a id='n1009' href='#n1009'>1009</a>
<a id='n1010' href='#n1010'>1010</a>
<a id='n1011' href='#n1011'>1011</a>
<a id='n1012' href='#n1012'>1012</a>
<a id='n1013' href='#n1013'>1013</a>
<a id='n1014' href='#n1014'>1014</a>
<a id='n1015' href='#n1015'>1015</a>
<a id='n1016' href='#n1016'>1016</a>
<a id='n1017' href='#n1017'>1017</a>
<a id='n1018' href='#n1018'>1018</a>
<a id='n1019' href='#n1019'>1019</a>
<a id='n1020' href='#n1020'>1020</a>
<a id='n1021' href='#n1021'>1021</a>
<a id='n1022' href='#n1022'>1022</a>
<a id='n1023' href='#n1023'>1023</a>
<a id='n1024' href='#n1024'>1024</a>
<a id='n1025' href='#n1025'>1025</a>
<a id='n1026' href='#n1026'>1026</a>
<a id='n1027' href='#n1027'>1027</a>
<a id='n1028' href='#n1028'>1028</a>
<a id='n1029' href='#n1029'>1029</a>
<a id='n1030' href='#n1030'>1030</a>
<a id='n1031' href='#n1031'>1031</a>
<a id='n1032' href='#n1032'>1032</a>
<a id='n1033' href='#n1033'>1033</a>
<a id='n1034' href='#n1034'>1034</a>
<a id='n1035' href='#n1035'>1035</a>
<a id='n1036' href='#n1036'>1036</a>
<a id='n1037' href='#n1037'>1037</a>
<a id='n1038' href='#n1038'>1038</a>
<a id='n1039' href='#n1039'>1039</a>
<a id='n1040' href='#n1040'>1040</a>
<a id='n1041' href='#n1041'>1041</a>
<a id='n1042' href='#n1042'>1042</a>
<a id='n1043' href='#n1043'>1043</a>
<a id='n1044' href='#n1044'>1044</a>
<a id='n1045' href='#n1045'>1045</a>
<a id='n1046' href='#n1046'>1046</a>
<a id='n1047' href='#n1047'>1047</a>
<a id='n1048' href='#n1048'>1048</a>
<a id='n1049' href='#n1049'>1049</a>
<a id='n1050' href='#n1050'>1050</a>
<a id='n1051' href='#n1051'>1051</a>
<a id='n1052' href='#n1052'>1052</a>
<a id='n1053' href='#n1053'>1053</a>
<a id='n1054' href='#n1054'>1054</a>
<a id='n1055' href='#n1055'>1055</a>
<a id='n1056' href='#n1056'>1056</a>
<a id='n1057' href='#n1057'>1057</a>
<a id='n1058' href='#n1058'>1058</a>
<a id='n1059' href='#n1059'>1059</a>
<a id='n1060' href='#n1060'>1060</a>
<a id='n1061' href='#n1061'>1061</a>
<a id='n1062' href='#n1062'>1062</a>
<a id='n1063' href='#n1063'>1063</a>
<a id='n1064' href='#n1064'>1064</a>
<a id='n1065' href='#n1065'>1065</a>
<a id='n1066' href='#n1066'>1066</a>
<a id='n1067' href='#n1067'>1067</a>
<a id='n1068' href='#n1068'>1068</a>
<a id='n1069' href='#n1069'>1069</a>
<a id='n1070' href='#n1070'>1070</a>
<a id='n1071' href='#n1071'>1071</a>
<a id='n1072' href='#n1072'>1072</a>
<a id='n1073' href='#n1073'>1073</a>
<a id='n1074' href='#n1074'>1074</a>
<a id='n1075' href='#n1075'>1075</a>
<a id='n1076' href='#n1076'>1076</a>
<a id='n1077' href='#n1077'>1077</a>
<a id='n1078' href='#n1078'>1078</a>
<a id='n1079' href='#n1079'>1079</a>
<a id='n1080' href='#n1080'>1080</a>
<a id='n1081' href='#n1081'>1081</a>
<a id='n1082' href='#n1082'>1082</a>
<a id='n1083' href='#n1083'>1083</a>
<a id='n1084' href='#n1084'>1084</a>
<a id='n1085' href='#n1085'>1085</a>
<a id='n1086' href='#n1086'>1086</a>
<a id='n1087' href='#n1087'>1087</a>
<a id='n1088' href='#n1088'>1088</a>
<a id='n1089' href='#n1089'>1089</a>
<a id='n1090' href='#n1090'>1090</a>
<a id='n1091' href='#n1091'>1091</a>
<a id='n1092' href='#n1092'>1092</a>
<a id='n1093' href='#n1093'>1093</a>
<a id='n1094' href='#n1094'>1094</a>
<a id='n1095' href='#n1095'>1095</a>
<a id='n1096' href='#n1096'>1096</a>
<a id='n1097' href='#n1097'>1097</a>
<a id='n1098' href='#n1098'>1098</a>
<a id='n1099' href='#n1099'>1099</a>
<a id='n1100' href='#n1100'>1100</a>
<a id='n1101' href='#n1101'>1101</a>
<a id='n1102' href='#n1102'>1102</a>
<a id='n1103' href='#n1103'>1103</a>
<a id='n1104' href='#n1104'>1104</a>
<a id='n1105' href='#n1105'>1105</a>
<a id='n1106' href='#n1106'>1106</a>
<a id='n1107' href='#n1107'>1107</a>
<a id='n1108' href='#n1108'>1108</a>
<a id='n1109' href='#n1109'>1109</a>
<a id='n1110' href='#n1110'>1110</a>
<a id='n1111' href='#n1111'>1111</a>
<a id='n1112' href='#n1112'>1112</a>
<a id='n1113' href='#n1113'>1113</a>
<a id='n1114' href='#n1114'>1114</a>
<a id='n1115' href='#n1115'>1115</a>
<a id='n1116' href='#n1116'>1116</a>
<a id='n1117' href='#n1117'>1117</a>
<a id='n1118' href='#n1118'>1118</a>
<a id='n1119' href='#n1119'>1119</a>
<a id='n1120' href='#n1120'>1120</a>
<a id='n1121' href='#n1121'>1121</a>
<a id='n1122' href='#n1122'>1122</a>
<a id='n1123' href='#n1123'>1123</a>
<a id='n1124' href='#n1124'>1124</a>
<a id='n1125' href='#n1125'>1125</a>
<a id='n1126' href='#n1126'>1126</a>
<a id='n1127' href='#n1127'>1127</a>
<a id='n1128' href='#n1128'>1128</a>
<a id='n1129' href='#n1129'>1129</a>
<a id='n1130' href='#n1130'>1130</a>
<a id='n1131' href='#n1131'>1131</a>
<a id='n1132' href='#n1132'>1132</a>
<a id='n1133' href='#n1133'>1133</a>
<a id='n1134' href='#n1134'>1134</a>
<a id='n1135' href='#n1135'>1135</a>
<a id='n1136' href='#n1136'>1136</a>
<a id='n1137' href='#n1137'>1137</a>
<a id='n1138' href='#n1138'>1138</a>
<a id='n1139' href='#n1139'>1139</a>
<a id='n1140' href='#n1140'>1140</a>
<a id='n1141' href='#n1141'>1141</a>
<a id='n1142' href='#n1142'>1142</a>
<a id='n1143' href='#n1143'>1143</a>
<a id='n1144' href='#n1144'>1144</a>
<a id='n1145' href='#n1145'>1145</a>
<a id='n1146' href='#n1146'>1146</a>
<a id='n1147' href='#n1147'>1147</a>
<a id='n1148' href='#n1148'>1148</a>
<a id='n1149' href='#n1149'>1149</a>
<a id='n1150' href='#n1150'>1150</a>
<a id='n1151' href='#n1151'>1151</a>
<a id='n1152' href='#n1152'>1152</a>
<a id='n1153' href='#n1153'>1153</a>
<a id='n1154' href='#n1154'>1154</a>
<a id='n1155' href='#n1155'>1155</a>
<a id='n1156' href='#n1156'>1156</a>
<a id='n1157' href='#n1157'>1157</a>
<a id='n1158' href='#n1158'>1158</a>
<a id='n1159' href='#n1159'>1159</a>
<a id='n1160' href='#n1160'>1160</a>
<a id='n1161' href='#n1161'>1161</a>
<a id='n1162' href='#n1162'>1162</a>
<a id='n1163' href='#n1163'>1163</a>
<a id='n1164' href='#n1164'>1164</a>
<a id='n1165' href='#n1165'>1165</a>
<a id='n1166' href='#n1166'>1166</a>
<a id='n1167' href='#n1167'>1167</a>
<a id='n1168' href='#n1168'>1168</a>
<a id='n1169' href='#n1169'>1169</a>
<a id='n1170' href='#n1170'>1170</a>
<a id='n1171' href='#n1171'>1171</a>
<a id='n1172' href='#n1172'>1172</a>
<a id='n1173' href='#n1173'>1173</a>
<a id='n1174' href='#n1174'>1174</a>
<a id='n1175' href='#n1175'>1175</a>
<a id='n1176' href='#n1176'>1176</a>
<a id='n1177' href='#n1177'>1177</a>
<a id='n1178' href='#n1178'>1178</a>
<a id='n1179' href='#n1179'>1179</a>
<a id='n1180' href='#n1180'>1180</a>
<a id='n1181' href='#n1181'>1181</a>
<a id='n1182' href='#n1182'>1182</a>
<a id='n1183' href='#n1183'>1183</a>
<a id='n1184' href='#n1184'>1184</a>
<a id='n1185' href='#n1185'>1185</a>
<a id='n1186' href='#n1186'>1186</a>
<a id='n1187' href='#n1187'>1187</a>
<a id='n1188' href='#n1188'>1188</a>
<a id='n1189' href='#n1189'>1189</a>
<a id='n1190' href='#n1190'>1190</a>
<a id='n1191' href='#n1191'>1191</a>
<a id='n1192' href='#n1192'>1192</a>
<a id='n1193' href='#n1193'>1193</a>
<a id='n1194' href='#n1194'>1194</a>
<a id='n1195' href='#n1195'>1195</a>
<a id='n1196' href='#n1196'>1196</a>
<a id='n1197' href='#n1197'>1197</a>
<a id='n1198' href='#n1198'>1198</a>
<a id='n1199' href='#n1199'>1199</a>
<a id='n1200' href='#n1200'>1200</a>
<a id='n1201' href='#n1201'>1201</a>
<a id='n1202' href='#n1202'>1202</a>
<a id='n1203' href='#n1203'>1203</a>
<a id='n1204' href='#n1204'>1204</a>
<a id='n1205' href='#n1205'>1205</a>
<a id='n1206' href='#n1206'>1206</a>
<a id='n1207' href='#n1207'>1207</a>
<a id='n1208' href='#n1208'>1208</a>
<a id='n1209' href='#n1209'>1209</a>
<a id='n1210' href='#n1210'>1210</a>
<a id='n1211' href='#n1211'>1211</a>
<a id='n1212' href='#n1212'>1212</a>
<a id='n1213' href='#n1213'>1213</a>
<a id='n1214' href='#n1214'>1214</a>
<a id='n1215' href='#n1215'>1215</a>
<a id='n1216' href='#n1216'>1216</a>
<a id='n1217' href='#n1217'>1217</a>
<a id='n1218' href='#n1218'>1218</a>
<a id='n1219' href='#n1219'>1219</a>
<a id='n1220' href='#n1220'>1220</a>
<a id='n1221' href='#n1221'>1221</a>
<a id='n1222' href='#n1222'>1222</a>
<a id='n1223' href='#n1223'>1223</a>
<a id='n1224' href='#n1224'>1224</a>
<a id='n1225' href='#n1225'>1225</a>
<a id='n1226' href='#n1226'>1226</a>
<a id='n1227' href='#n1227'>1227</a>
<a id='n1228' href='#n1228'>1228</a>
<a id='n1229' href='#n1229'>1229</a>
<a id='n1230' href='#n1230'>1230</a>
<a id='n1231' href='#n1231'>1231</a>
<a id='n1232' href='#n1232'>1232</a>
<a id='n1233' href='#n1233'>1233</a>
<a id='n1234' href='#n1234'>1234</a>
<a id='n1235' href='#n1235'>1235</a>
<a id='n1236' href='#n1236'>1236</a>
<a id='n1237' href='#n1237'>1237</a>
<a id='n1238' href='#n1238'>1238</a>
<a id='n1239' href='#n1239'>1239</a>
<a id='n1240' href='#n1240'>1240</a>
<a id='n1241' href='#n1241'>1241</a>
<a id='n1242' href='#n1242'>1242</a>
<a id='n1243' href='#n1243'>1243</a>
<a id='n1244' href='#n1244'>1244</a>
<a id='n1245' href='#n1245'>1245</a>
<a id='n1246' href='#n1246'>1246</a>
<a id='n1247' href='#n1247'>1247</a>
<a id='n1248' href='#n1248'>1248</a>
<a id='n1249' href='#n1249'>1249</a>
<a id='n1250' href='#n1250'>1250</a>
<a id='n1251' href='#n1251'>1251</a>
<a id='n1252' href='#n1252'>1252</a>
<a id='n1253' href='#n1253'>1253</a>
<a id='n1254' href='#n1254'>1254</a>
<a id='n1255' href='#n1255'>1255</a>
<a id='n1256' href='#n1256'>1256</a>
<a id='n1257' href='#n1257'>1257</a>
<a id='n1258' href='#n1258'>1258</a>
<a id='n1259' href='#n1259'>1259</a>
<a id='n1260' href='#n1260'>1260</a>
<a id='n1261' href='#n1261'>1261</a>
<a id='n1262' href='#n1262'>1262</a>
<a id='n1263' href='#n1263'>1263</a>
<a id='n1264' href='#n1264'>1264</a>
<a id='n1265' href='#n1265'>1265</a>
<a id='n1266' href='#n1266'>1266</a>
<a id='n1267' href='#n1267'>1267</a>
<a id='n1268' href='#n1268'>1268</a>
<a id='n1269' href='#n1269'>1269</a>
<a id='n1270' href='#n1270'>1270</a>
<a id='n1271' href='#n1271'>1271</a>
<a id='n1272' href='#n1272'>1272</a>
<a id='n1273' href='#n1273'>1273</a>
<a id='n1274' href='#n1274'>1274</a>
<a id='n1275' href='#n1275'>1275</a>
<a id='n1276' href='#n1276'>1276</a>
<a id='n1277' href='#n1277'>1277</a>
<a id='n1278' href='#n1278'>1278</a>
<a id='n1279' href='#n1279'>1279</a>
<a id='n1280' href='#n1280'>1280</a>
<a id='n1281' href='#n1281'>1281</a>
<a id='n1282' href='#n1282'>1282</a>
<a id='n1283' href='#n1283'>1283</a>
<a id='n1284' href='#n1284'>1284</a>
<a id='n1285' href='#n1285'>1285</a>
<a id='n1286' href='#n1286'>1286</a>
<a id='n1287' href='#n1287'>1287</a>
<a id='n1288' href='#n1288'>1288</a>
<a id='n1289' href='#n1289'>1289</a>
<a id='n1290' href='#n1290'>1290</a>
<a id='n1291' href='#n1291'>1291</a>
<a id='n1292' href='#n1292'>1292</a>
<a id='n1293' href='#n1293'>1293</a>
<a id='n1294' href='#n1294'>1294</a>
<a id='n1295' href='#n1295'>1295</a>
<a id='n1296' href='#n1296'>1296</a>
<a id='n1297' href='#n1297'>1297</a>
<a id='n1298' href='#n1298'>1298</a>
<a id='n1299' href='#n1299'>1299</a>
<a id='n1300' href='#n1300'>1300</a>
<a id='n1301' href='#n1301'>1301</a>
<a id='n1302' href='#n1302'>1302</a>
<a id='n1303' href='#n1303'>1303</a>
<a id='n1304' href='#n1304'>1304</a>
<a id='n1305' href='#n1305'>1305</a>
<a id='n1306' href='#n1306'>1306</a>
<a id='n1307' href='#n1307'>1307</a>
<a id='n1308' href='#n1308'>1308</a>
<a id='n1309' href='#n1309'>1309</a>
<a id='n1310' href='#n1310'>1310</a>
<a id='n1311' href='#n1311'>1311</a>
<a id='n1312' href='#n1312'>1312</a>
<a id='n1313' href='#n1313'>1313</a>
<a id='n1314' href='#n1314'>1314</a>
<a id='n1315' href='#n1315'>1315</a>
<a id='n1316' href='#n1316'>1316</a>
<a id='n1317' href='#n1317'>1317</a>
<a id='n1318' href='#n1318'>1318</a>
<a id='n1319' href='#n1319'>1319</a>
<a id='n1320' href='#n1320'>1320</a>
<a id='n1321' href='#n1321'>1321</a>
<a id='n1322' href='#n1322'>1322</a>
<a id='n1323' href='#n1323'>1323</a>
<a id='n1324' href='#n1324'>1324</a>
<a id='n1325' href='#n1325'>1325</a>
<a id='n1326' href='#n1326'>1326</a>
<a id='n1327' href='#n1327'>1327</a>
<a id='n1328' href='#n1328'>1328</a>
<a id='n1329' href='#n1329'>1329</a>
<a id='n1330' href='#n1330'>1330</a>
<a id='n1331' href='#n1331'>1331</a>
<a id='n1332' href='#n1332'>1332</a>
<a id='n1333' href='#n1333'>1333</a>
<a id='n1334' href='#n1334'>1334</a>
<a id='n1335' href='#n1335'>1335</a>
<a id='n1336' href='#n1336'>1336</a>
<a id='n1337' href='#n1337'>1337</a>
<a id='n1338' href='#n1338'>1338</a>
<a id='n1339' href='#n1339'>1339</a>
<a id='n1340' href='#n1340'>1340</a>
<a id='n1341' href='#n1341'>1341</a>
<a id='n1342' href='#n1342'>1342</a>
<a id='n1343' href='#n1343'>1343</a>
<a id='n1344' href='#n1344'>1344</a>
<a id='n1345' href='#n1345'>1345</a>
<a id='n1346' href='#n1346'>1346</a>
<a id='n1347' href='#n1347'>1347</a>
<a id='n1348' href='#n1348'>1348</a>
<a id='n1349' href='#n1349'>1349</a>
<a id='n1350' href='#n1350'>1350</a>
<a id='n1351' href='#n1351'>1351</a>
<a id='n1352' href='#n1352'>1352</a>
<a id='n1353' href='#n1353'>1353</a>
<a id='n1354' href='#n1354'>1354</a>
<a id='n1355' href='#n1355'>1355</a>
<a id='n1356' href='#n1356'>1356</a>
<a id='n1357' href='#n1357'>1357</a>
<a id='n1358' href='#n1358'>1358</a>
<a id='n1359' href='#n1359'>1359</a>
<a id='n1360' href='#n1360'>1360</a>
<a id='n1361' href='#n1361'>1361</a>
<a id='n1362' href='#n1362'>1362</a>
<a id='n1363' href='#n1363'>1363</a>
<a id='n1364' href='#n1364'>1364</a>
<a id='n1365' href='#n1365'>1365</a>
<a id='n1366' href='#n1366'>1366</a>
<a id='n1367' href='#n1367'>1367</a>
<a id='n1368' href='#n1368'>1368</a>
<a id='n1369' href='#n1369'>1369</a>
<a id='n1370' href='#n1370'>1370</a>
<a id='n1371' href='#n1371'>1371</a>
<a id='n1372' href='#n1372'>1372</a>
<a id='n1373' href='#n1373'>1373</a>
<a id='n1374' href='#n1374'>1374</a>
<a id='n1375' href='#n1375'>1375</a>
<a id='n1376' href='#n1376'>1376</a>
<a id='n1377' href='#n1377'>1377</a>
<a id='n1378' href='#n1378'>1378</a>
<a id='n1379' href='#n1379'>1379</a>
<a id='n1380' href='#n1380'>1380</a>
<a id='n1381' href='#n1381'>1381</a>
<a id='n1382' href='#n1382'>1382</a>
<a id='n1383' href='#n1383'>1383</a>
<a id='n1384' href='#n1384'>1384</a>
<a id='n1385' href='#n1385'>1385</a>
<a id='n1386' href='#n1386'>1386</a>
<a id='n1387' href='#n1387'>1387</a>
<a id='n1388' href='#n1388'>1388</a>
<a id='n1389' href='#n1389'>1389</a>
<a id='n1390' href='#n1390'>1390</a>
<a id='n1391' href='#n1391'>1391</a>
<a id='n1392' href='#n1392'>1392</a>
<a id='n1393' href='#n1393'>1393</a>
<a id='n1394' href='#n1394'>1394</a>
<a id='n1395' href='#n1395'>1395</a>
<a id='n1396' href='#n1396'>1396</a>
<a id='n1397' href='#n1397'>1397</a>
<a id='n1398' href='#n1398'>1398</a>
<a id='n1399' href='#n1399'>1399</a>
<a id='n1400' href='#n1400'>1400</a>
<a id='n1401' href='#n1401'>1401</a>
<a id='n1402' href='#n1402'>1402</a>
<a id='n1403' href='#n1403'>1403</a>
<a id='n1404' href='#n1404'>1404</a>
<a id='n1405' href='#n1405'>1405</a>
<a id='n1406' href='#n1406'>1406</a>
<a id='n1407' href='#n1407'>1407</a>
<a id='n1408' href='#n1408'>1408</a>
<a id='n1409' href='#n1409'>1409</a>
<a id='n1410' href='#n1410'>1410</a>
<a id='n1411' href='#n1411'>1411</a>
<a id='n1412' href='#n1412'>1412</a>
<a id='n1413' href='#n1413'>1413</a>
<a id='n1414' href='#n1414'>1414</a>
<a id='n1415' href='#n1415'>1415</a>
<a id='n1416' href='#n1416'>1416</a>
<a id='n1417' href='#n1417'>1417</a>
<a id='n1418' href='#n1418'>1418</a>
<a id='n1419' href='#n1419'>1419</a>
<a id='n1420' href='#n1420'>1420</a>
<a id='n1421' href='#n1421'>1421</a>
<a id='n1422' href='#n1422'>1422</a>
<a id='n1423' href='#n1423'>1423</a>
<a id='n1424' href='#n1424'>1424</a>
<a id='n1425' href='#n1425'>1425</a>
<a id='n1426' href='#n1426'>1426</a>
<a id='n1427' href='#n1427'>1427</a>
<a id='n1428' href='#n1428'>1428</a>
<a id='n1429' href='#n1429'>1429</a>
<a id='n1430' href='#n1430'>1430</a>
<a id='n1431' href='#n1431'>1431</a>
<a id='n1432' href='#n1432'>1432</a>
<a id='n1433' href='#n1433'>1433</a>
<a id='n1434' href='#n1434'>1434</a>
<a id='n1435' href='#n1435'>1435</a>
<a id='n1436' href='#n1436'>1436</a>
<a id='n1437' href='#n1437'>1437</a>
<a id='n1438' href='#n1438'>1438</a>
<a id='n1439' href='#n1439'>1439</a>
<a id='n1440' href='#n1440'>1440</a>
<a id='n1441' href='#n1441'>1441</a>
<a id='n1442' href='#n1442'>1442</a>
<a id='n1443' href='#n1443'>1443</a>
<a id='n1444' href='#n1444'>1444</a>
<a id='n1445' href='#n1445'>1445</a>
<a id='n1446' href='#n1446'>1446</a>
<a id='n1447' href='#n1447'>1447</a>
<a id='n1448' href='#n1448'>1448</a>
<a id='n1449' href='#n1449'>1449</a>
<a id='n1450' href='#n1450'>1450</a>
<a id='n1451' href='#n1451'>1451</a>
<a id='n1452' href='#n1452'>1452</a>
<a id='n1453' href='#n1453'>1453</a>
<a id='n1454' href='#n1454'>1454</a>
<a id='n1455' href='#n1455'>1455</a>
<a id='n1456' href='#n1456'>1456</a>
<a id='n1457' href='#n1457'>1457</a>
<a id='n1458' href='#n1458'>1458</a>
<a id='n1459' href='#n1459'>1459</a>
<a id='n1460' href='#n1460'>1460</a>
<a id='n1461' href='#n1461'>1461</a>
<a id='n1462' href='#n1462'>1462</a>
<a id='n1463' href='#n1463'>1463</a>
<a id='n1464' href='#n1464'>1464</a>
<a id='n1465' href='#n1465'>1465</a>
<a id='n1466' href='#n1466'>1466</a>
<a id='n1467' href='#n1467'>1467</a>
<a id='n1468' href='#n1468'>1468</a>
<a id='n1469' href='#n1469'>1469</a>
<a id='n1470' href='#n1470'>1470</a>
<a id='n1471' href='#n1471'>1471</a>
<a id='n1472' href='#n1472'>1472</a>
<a id='n1473' href='#n1473'>1473</a>
<a id='n1474' href='#n1474'>1474</a>
<a id='n1475' href='#n1475'>1475</a>
<a id='n1476' href='#n1476'>1476</a>
<a id='n1477' href='#n1477'>1477</a>
<a id='n1478' href='#n1478'>1478</a>
<a id='n1479' href='#n1479'>1479</a>
<a id='n1480' href='#n1480'>1480</a>
<a id='n1481' href='#n1481'>1481</a>
<a id='n1482' href='#n1482'>1482</a>
<a id='n1483' href='#n1483'>1483</a>
<a id='n1484' href='#n1484'>1484</a>
<a id='n1485' href='#n1485'>1485</a>
<a id='n1486' href='#n1486'>1486</a>
<a id='n1487' href='#n1487'>1487</a>
<a id='n1488' href='#n1488'>1488</a>
<a id='n1489' href='#n1489'>1489</a>
<a id='n1490' href='#n1490'>1490</a>
<a id='n1491' href='#n1491'>1491</a>
<a id='n1492' href='#n1492'>1492</a>
<a id='n1493' href='#n1493'>1493</a>
<a id='n1494' href='#n1494'>1494</a>
<a id='n1495' href='#n1495'>1495</a>
<a id='n1496' href='#n1496'>1496</a>
<a id='n1497' href='#n1497'>1497</a>
<a id='n1498' href='#n1498'>1498</a>
<a id='n1499' href='#n1499'>1499</a>
<a id='n1500' href='#n1500'>1500</a>
<a id='n1501' href='#n1501'>1501</a>
<a id='n1502' href='#n1502'>1502</a>
<a id='n1503' href='#n1503'>1503</a>
<a id='n1504' href='#n1504'>1504</a>
<a id='n1505' href='#n1505'>1505</a>
<a id='n1506' href='#n1506'>1506</a>
<a id='n1507' href='#n1507'>1507</a>
<a id='n1508' href='#n1508'>1508</a>
<a id='n1509' href='#n1509'>1509</a>
<a id='n1510' href='#n1510'>1510</a>
<a id='n1511' href='#n1511'>1511</a>
<a id='n1512' href='#n1512'>1512</a>
<a id='n1513' href='#n1513'>1513</a>
<a id='n1514' href='#n1514'>1514</a>
<a id='n1515' href='#n1515'>1515</a>
<a id='n1516' href='#n1516'>1516</a>
<a id='n1517' href='#n1517'>1517</a>
<a id='n1518' href='#n1518'>1518</a>
<a id='n1519' href='#n1519'>1519</a>
<a id='n1520' href='#n1520'>1520</a>
<a id='n1521' href='#n1521'>1521</a>
<a id='n1522' href='#n1522'>1522</a>
<a id='n1523' href='#n1523'>1523</a>
<a id='n1524' href='#n1524'>1524</a>
<a id='n1525' href='#n1525'>1525</a>
<a id='n1526' href='#n1526'>1526</a>
<a id='n1527' href='#n1527'>1527</a>
<a id='n1528' href='#n1528'>1528</a>
<a id='n1529' href='#n1529'>1529</a>
<a id='n1530' href='#n1530'>1530</a>
<a id='n1531' href='#n1531'>1531</a>
<a id='n1532' href='#n1532'>1532</a>
<a id='n1533' href='#n1533'>1533</a>
<a id='n1534' href='#n1534'>1534</a>
<a id='n1535' href='#n1535'>1535</a>
<a id='n1536' href='#n1536'>1536</a>
<a id='n1537' href='#n1537'>1537</a>
<a id='n1538' href='#n1538'>1538</a>
<a id='n1539' href='#n1539'>1539</a>
<a id='n1540' href='#n1540'>1540</a>
<a id='n1541' href='#n1541'>1541</a>
<a id='n1542' href='#n1542'>1542</a>
<a id='n1543' href='#n1543'>1543</a>
<a id='n1544' href='#n1544'>1544</a>
<a id='n1545' href='#n1545'>1545</a>
<a id='n1546' href='#n1546'>1546</a>
<a id='n1547' href='#n1547'>1547</a>
<a id='n1548' href='#n1548'>1548</a>
<a id='n1549' href='#n1549'>1549</a>
<a id='n1550' href='#n1550'>1550</a>
<a id='n1551' href='#n1551'>1551</a>
<a id='n1552' href='#n1552'>1552</a>
<a id='n1553' href='#n1553'>1553</a>
<a id='n1554' href='#n1554'>1554</a>
<a id='n1555' href='#n1555'>1555</a>
<a id='n1556' href='#n1556'>1556</a>
<a id='n1557' href='#n1557'>1557</a>
<a id='n1558' href='#n1558'>1558</a>
<a id='n1559' href='#n1559'>1559</a>
<a id='n1560' href='#n1560'>1560</a>
<a id='n1561' href='#n1561'>1561</a>
<a id='n1562' href='#n1562'>1562</a>
<a id='n1563' href='#n1563'>1563</a>
<a id='n1564' href='#n1564'>1564</a>
<a id='n1565' href='#n1565'>1565</a>
<a id='n1566' href='#n1566'>1566</a>
<a id='n1567' href='#n1567'>1567</a>
<a id='n1568' href='#n1568'>1568</a>
<a id='n1569' href='#n1569'>1569</a>
<a id='n1570' href='#n1570'>1570</a>
<a id='n1571' href='#n1571'>1571</a>
<a id='n1572' href='#n1572'>1572</a>
<a id='n1573' href='#n1573'>1573</a>
<a id='n1574' href='#n1574'>1574</a>
<a id='n1575' href='#n1575'>1575</a>
<a id='n1576' href='#n1576'>1576</a>
<a id='n1577' href='#n1577'>1577</a>
<a id='n1578' href='#n1578'>1578</a>
<a id='n1579' href='#n1579'>1579</a>
<a id='n1580' href='#n1580'>1580</a>
<a id='n1581' href='#n1581'>1581</a>
<a id='n1582' href='#n1582'>1582</a>
<a id='n1583' href='#n1583'>1583</a>
<a id='n1584' href='#n1584'>1584</a>
<a id='n1585' href='#n1585'>1585</a>
<a id='n1586' href='#n1586'>1586</a>
<a id='n1587' href='#n1587'>1587</a>
<a id='n1588' href='#n1588'>1588</a>
<a id='n1589' href='#n1589'>1589</a>
<a id='n1590' href='#n1590'>1590</a>
<a id='n1591' href='#n1591'>1591</a>
<a id='n1592' href='#n1592'>1592</a>
<a id='n1593' href='#n1593'>1593</a>
<a id='n1594' href='#n1594'>1594</a>
<a id='n1595' href='#n1595'>1595</a>
<a id='n1596' href='#n1596'>1596</a>
<a id='n1597' href='#n1597'>1597</a>
<a id='n1598' href='#n1598'>1598</a>
<a id='n1599' href='#n1599'>1599</a>
<a id='n1600' href='#n1600'>1600</a>
<a id='n1601' href='#n1601'>1601</a>
<a id='n1602' href='#n1602'>1602</a>
<a id='n1603' href='#n1603'>1603</a>
<a id='n1604' href='#n1604'>1604</a>
<a id='n1605' href='#n1605'>1605</a>
<a id='n1606' href='#n1606'>1606</a>
<a id='n1607' href='#n1607'>1607</a>
<a id='n1608' href='#n1608'>1608</a>
<a id='n1609' href='#n1609'>1609</a>
<a id='n1610' href='#n1610'>1610</a>
<a id='n1611' href='#n1611'>1611</a>
<a id='n1612' href='#n1612'>1612</a>
<a id='n1613' href='#n1613'>1613</a>
<a id='n1614' href='#n1614'>1614</a>
<a id='n1615' href='#n1615'>1615</a>
<a id='n1616' href='#n1616'>1616</a>
<a id='n1617' href='#n1617'>1617</a>
<a id='n1618' href='#n1618'>1618</a>
<a id='n1619' href='#n1619'>1619</a>
<a id='n1620' href='#n1620'>1620</a>
<a id='n1621' href='#n1621'>1621</a>
<a id='n1622' href='#n1622'>1622</a>
<a id='n1623' href='#n1623'>1623</a>
<a id='n1624' href='#n1624'>1624</a>
<a id='n1625' href='#n1625'>1625</a>
<a id='n1626' href='#n1626'>1626</a>
<a id='n1627' href='#n1627'>1627</a>
<a id='n1628' href='#n1628'>1628</a>
<a id='n1629' href='#n1629'>1629</a>
<a id='n1630' href='#n1630'>1630</a>
<a id='n1631' href='#n1631'>1631</a>
<a id='n1632' href='#n1632'>1632</a>
<a id='n1633' href='#n1633'>1633</a>
<a id='n1634' href='#n1634'>1634</a>
<a id='n1635' href='#n1635'>1635</a>
<a id='n1636' href='#n1636'>1636</a>
<a id='n1637' href='#n1637'>1637</a>
<a id='n1638' href='#n1638'>1638</a>
<a id='n1639' href='#n1639'>1639</a>
<a id='n1640' href='#n1640'>1640</a>
<a id='n1641' href='#n1641'>1641</a>
<a id='n1642' href='#n1642'>1642</a>
<a id='n1643' href='#n1643'>1643</a>
<a id='n1644' href='#n1644'>1644</a>
<a id='n1645' href='#n1645'>1645</a>
<a id='n1646' href='#n1646'>1646</a>
<a id='n1647' href='#n1647'>1647</a>
<a id='n1648' href='#n1648'>1648</a>
<a id='n1649' href='#n1649'>1649</a>
<a id='n1650' href='#n1650'>1650</a>
<a id='n1651' href='#n1651'>1651</a>
<a id='n1652' href='#n1652'>1652</a>
<a id='n1653' href='#n1653'>1653</a>
<a id='n1654' href='#n1654'>1654</a>
<a id='n1655' href='#n1655'>1655</a>
<a id='n1656' href='#n1656'>1656</a>
<a id='n1657' href='#n1657'>1657</a>
<a id='n1658' href='#n1658'>1658</a>
<a id='n1659' href='#n1659'>1659</a>
<a id='n1660' href='#n1660'>1660</a>
<a id='n1661' href='#n1661'>1661</a>
<a id='n1662' href='#n1662'>1662</a>
<a id='n1663' href='#n1663'>1663</a>
<a id='n1664' href='#n1664'>1664</a>
<a id='n1665' href='#n1665'>1665</a>
<a id='n1666' href='#n1666'>1666</a>
<a id='n1667' href='#n1667'>1667</a>
<a id='n1668' href='#n1668'>1668</a>
<a id='n1669' href='#n1669'>1669</a>
<a id='n1670' href='#n1670'>1670</a>
<a id='n1671' href='#n1671'>1671</a>
<a id='n1672' href='#n1672'>1672</a>
<a id='n1673' href='#n1673'>1673</a>
<a id='n1674' href='#n1674'>1674</a>
<a id='n1675' href='#n1675'>1675</a>
<a id='n1676' href='#n1676'>1676</a>
<a id='n1677' href='#n1677'>1677</a>
<a id='n1678' href='#n1678'>1678</a>
<a id='n1679' href='#n1679'>1679</a>
<a id='n1680' href='#n1680'>1680</a>
<a id='n1681' href='#n1681'>1681</a>
<a id='n1682' href='#n1682'>1682</a>
<a id='n1683' href='#n1683'>1683</a>
<a id='n1684' href='#n1684'>1684</a>
<a id='n1685' href='#n1685'>1685</a>
<a id='n1686' href='#n1686'>1686</a>
<a id='n1687' href='#n1687'>1687</a>
<a id='n1688' href='#n1688'>1688</a>
<a id='n1689' href='#n1689'>1689</a>
<a id='n1690' href='#n1690'>1690</a>
<a id='n1691' href='#n1691'>1691</a>
<a id='n1692' href='#n1692'>1692</a>
<a id='n1693' href='#n1693'>1693</a>
<a id='n1694' href='#n1694'>1694</a>
<a id='n1695' href='#n1695'>1695</a>
<a id='n1696' href='#n1696'>1696</a>
<a id='n1697' href='#n1697'>1697</a>
<a id='n1698' href='#n1698'>1698</a>
<a id='n1699' href='#n1699'>1699</a>
<a id='n1700' href='#n1700'>1700</a>
<a id='n1701' href='#n1701'>1701</a>
<a id='n1702' href='#n1702'>1702</a>
<a id='n1703' href='#n1703'>1703</a>
<a id='n1704' href='#n1704'>1704</a>
<a id='n1705' href='#n1705'>1705</a>
<a id='n1706' href='#n1706'>1706</a>
<a id='n1707' href='#n1707'>1707</a>
<a id='n1708' href='#n1708'>1708</a>
<a id='n1709' href='#n1709'>1709</a>
<a id='n1710' href='#n1710'>1710</a>
<a id='n1711' href='#n1711'>1711</a>
<a id='n1712' href='#n1712'>1712</a>
<a id='n1713' href='#n1713'>1713</a>
<a id='n1714' href='#n1714'>1714</a>
<a id='n1715' href='#n1715'>1715</a>
<a id='n1716' href='#n1716'>1716</a>
<a id='n1717' href='#n1717'>1717</a>
<a id='n1718' href='#n1718'>1718</a>
<a id='n1719' href='#n1719'>1719</a>
<a id='n1720' href='#n1720'>1720</a>
<a id='n1721' href='#n1721'>1721</a>
<a id='n1722' href='#n1722'>1722</a>
<a id='n1723' href='#n1723'>1723</a>
<a id='n1724' href='#n1724'>1724</a>
<a id='n1725' href='#n1725'>1725</a>
<a id='n1726' href='#n1726'>1726</a>
<a id='n1727' href='#n1727'>1727</a>
<a id='n1728' href='#n1728'>1728</a>
<a id='n1729' href='#n1729'>1729</a>
<a id='n1730' href='#n1730'>1730</a>
<a id='n1731' href='#n1731'>1731</a>
<a id='n1732' href='#n1732'>1732</a>
<a id='n1733' href='#n1733'>1733</a>
<a id='n1734' href='#n1734'>1734</a>
<a id='n1735' href='#n1735'>1735</a>
<a id='n1736' href='#n1736'>1736</a>
<a id='n1737' href='#n1737'>1737</a>
<a id='n1738' href='#n1738'>1738</a>
<a id='n1739' href='#n1739'>1739</a>
<a id='n1740' href='#n1740'>1740</a>
<a id='n1741' href='#n1741'>1741</a>
<a id='n1742' href='#n1742'>1742</a>
<a id='n1743' href='#n1743'>1743</a>
<a id='n1744' href='#n1744'>1744</a>
<a id='n1745' href='#n1745'>1745</a>
<a id='n1746' href='#n1746'>1746</a>
<a id='n1747' href='#n1747'>1747</a>
<a id='n1748' href='#n1748'>1748</a>
<a id='n1749' href='#n1749'>1749</a>
<a id='n1750' href='#n1750'>1750</a>
<a id='n1751' href='#n1751'>1751</a>
<a id='n1752' href='#n1752'>1752</a>
<a id='n1753' href='#n1753'>1753</a>
<a id='n1754' href='#n1754'>1754</a>
<a id='n1755' href='#n1755'>1755</a>
<a id='n1756' href='#n1756'>1756</a>
<a id='n1757' href='#n1757'>1757</a>
<a id='n1758' href='#n1758'>1758</a>
<a id='n1759' href='#n1759'>1759</a>
<a id='n1760' href='#n1760'>1760</a>
<a id='n1761' href='#n1761'>1761</a>
<a id='n1762' href='#n1762'>1762</a>
<a id='n1763' href='#n1763'>1763</a>
<a id='n1764' href='#n1764'>1764</a>
<a id='n1765' href='#n1765'>1765</a>
<a id='n1766' href='#n1766'>1766</a>
<a id='n1767' href='#n1767'>1767</a>
<a id='n1768' href='#n1768'>1768</a>
<a id='n1769' href='#n1769'>1769</a>
<a id='n1770' href='#n1770'>1770</a>
<a id='n1771' href='#n1771'>1771</a>
<a id='n1772' href='#n1772'>1772</a>
<a id='n1773' href='#n1773'>1773</a>
<a id='n1774' href='#n1774'>1774</a>
<a id='n1775' href='#n1775'>1775</a>
<a id='n1776' href='#n1776'>1776</a>
<a id='n1777' href='#n1777'>1777</a>
<a id='n1778' href='#n1778'>1778</a>
<a id='n1779' href='#n1779'>1779</a>
<a id='n1780' href='#n1780'>1780</a>
<a id='n1781' href='#n1781'>1781</a>
<a id='n1782' href='#n1782'>1782</a>
<a id='n1783' href='#n1783'>1783</a>
<a id='n1784' href='#n1784'>1784</a>
<a id='n1785' href='#n1785'>1785</a>
<a id='n1786' href='#n1786'>1786</a>
<a id='n1787' href='#n1787'>1787</a>
<a id='n1788' href='#n1788'>1788</a>
<a id='n1789' href='#n1789'>1789</a>
<a id='n1790' href='#n1790'>1790</a>
<a id='n1791' href='#n1791'>1791</a>
<a id='n1792' href='#n1792'>1792</a>
<a id='n1793' href='#n1793'>1793</a>
<a id='n1794' href='#n1794'>1794</a>
<a id='n1795' href='#n1795'>1795</a>
<a id='n1796' href='#n1796'>1796</a>
<a id='n1797' href='#n1797'>1797</a>
<a id='n1798' href='#n1798'>1798</a>
<a id='n1799' href='#n1799'>1799</a>
<a id='n1800' href='#n1800'>1800</a>
<a id='n1801' href='#n1801'>1801</a>
<a id='n1802' href='#n1802'>1802</a>
<a id='n1803' href='#n1803'>1803</a>
<a id='n1804' href='#n1804'>1804</a>
<a id='n1805' href='#n1805'>1805</a>
<a id='n1806' href='#n1806'>1806</a>
<a id='n1807' href='#n1807'>1807</a>
<a id='n1808' href='#n1808'>1808</a>
<a id='n1809' href='#n1809'>1809</a>
<a id='n1810' href='#n1810'>1810</a>
<a id='n1811' href='#n1811'>1811</a>
<a id='n1812' href='#n1812'>1812</a>
<a id='n1813' href='#n1813'>1813</a>
<a id='n1814' href='#n1814'>1814</a>
<a id='n1815' href='#n1815'>1815</a>
<a id='n1816' href='#n1816'>1816</a>
<a id='n1817' href='#n1817'>1817</a>
<a id='n1818' href='#n1818'>1818</a>
<a id='n1819' href='#n1819'>1819</a>
<a id='n1820' href='#n1820'>1820</a>
<a id='n1821' href='#n1821'>1821</a>
<a id='n1822' href='#n1822'>1822</a>
<a id='n1823' href='#n1823'>1823</a>
<a id='n1824' href='#n1824'>1824</a>
<a id='n1825' href='#n1825'>1825</a>
<a id='n1826' href='#n1826'>1826</a>
<a id='n1827' href='#n1827'>1827</a>
<a id='n1828' href='#n1828'>1828</a>
<a id='n1829' href='#n1829'>1829</a>
<a id='n1830' href='#n1830'>1830</a>
<a id='n1831' href='#n1831'>1831</a>
<a id='n1832' href='#n1832'>1832</a>
<a id='n1833' href='#n1833'>1833</a>
<a id='n1834' href='#n1834'>1834</a>
<a id='n1835' href='#n1835'>1835</a>
<a id='n1836' href='#n1836'>1836</a>
<a id='n1837' href='#n1837'>1837</a>
<a id='n1838' href='#n1838'>1838</a>
<a id='n1839' href='#n1839'>1839</a>
<a id='n1840' href='#n1840'>1840</a>
<a id='n1841' href='#n1841'>1841</a>
<a id='n1842' href='#n1842'>1842</a>
<a id='n1843' href='#n1843'>1843</a>
<a id='n1844' href='#n1844'>1844</a>
<a id='n1845' href='#n1845'>1845</a>
<a id='n1846' href='#n1846'>1846</a>
<a id='n1847' href='#n1847'>1847</a>
<a id='n1848' href='#n1848'>1848</a>
<a id='n1849' href='#n1849'>1849</a>
<a id='n1850' href='#n1850'>1850</a>
<a id='n1851' href='#n1851'>1851</a>
<a id='n1852' href='#n1852'>1852</a>
<a id='n1853' href='#n1853'>1853</a>
<a id='n1854' href='#n1854'>1854</a>
<a id='n1855' href='#n1855'>1855</a>
<a id='n1856' href='#n1856'>1856</a>
<a id='n1857' href='#n1857'>1857</a>
<a id='n1858' href='#n1858'>1858</a>
<a id='n1859' href='#n1859'>1859</a>
<a id='n1860' href='#n1860'>1860</a>
<a id='n1861' href='#n1861'>1861</a>
<a id='n1862' href='#n1862'>1862</a>
<a id='n1863' href='#n1863'>1863</a>
<a id='n1864' href='#n1864'>1864</a>
<a id='n1865' href='#n1865'>1865</a>
<a id='n1866' href='#n1866'>1866</a>
<a id='n1867' href='#n1867'>1867</a>
<a id='n1868' href='#n1868'>1868</a>
<a id='n1869' href='#n1869'>1869</a>
<a id='n1870' href='#n1870'>1870</a>
<a id='n1871' href='#n1871'>1871</a>
<a id='n1872' href='#n1872'>1872</a>
<a id='n1873' href='#n1873'>1873</a>
<a id='n1874' href='#n1874'>1874</a>
<a id='n1875' href='#n1875'>1875</a>
<a id='n1876' href='#n1876'>1876</a>
<a id='n1877' href='#n1877'>1877</a>
<a id='n1878' href='#n1878'>1878</a>
<a id='n1879' href='#n1879'>1879</a>
<a id='n1880' href='#n1880'>1880</a>
<a id='n1881' href='#n1881'>1881</a>
<a id='n1882' href='#n1882'>1882</a>
<a id='n1883' href='#n1883'>1883</a>
<a id='n1884' href='#n1884'>1884</a>
<a id='n1885' href='#n1885'>1885</a>
<a id='n1886' href='#n1886'>1886</a>
<a id='n1887' href='#n1887'>1887</a>
<a id='n1888' href='#n1888'>1888</a>
<a id='n1889' href='#n1889'>1889</a>
<a id='n1890' href='#n1890'>1890</a>
<a id='n1891' href='#n1891'>1891</a>
<a id='n1892' href='#n1892'>1892</a>
<a id='n1893' href='#n1893'>1893</a>
<a id='n1894' href='#n1894'>1894</a>
<a id='n1895' href='#n1895'>1895</a>
<a id='n1896' href='#n1896'>1896</a>
<a id='n1897' href='#n1897'>1897</a>
<a id='n1898' href='#n1898'>1898</a>
<a id='n1899' href='#n1899'>1899</a>
<a id='n1900' href='#n1900'>1900</a>
<a id='n1901' href='#n1901'>1901</a>
<a id='n1902' href='#n1902'>1902</a>
<a id='n1903' href='#n1903'>1903</a>
<a id='n1904' href='#n1904'>1904</a>
<a id='n1905' href='#n1905'>1905</a>
<a id='n1906' href='#n1906'>1906</a>
<a id='n1907' href='#n1907'>1907</a>
<a id='n1908' href='#n1908'>1908</a>
<a id='n1909' href='#n1909'>1909</a>
<a id='n1910' href='#n1910'>1910</a>
<a id='n1911' href='#n1911'>1911</a>
<a id='n1912' href='#n1912'>1912</a>
<a id='n1913' href='#n1913'>1913</a>
<a id='n1914' href='#n1914'>1914</a>
<a id='n1915' href='#n1915'>1915</a>
<a id='n1916' href='#n1916'>1916</a>
<a id='n1917' href='#n1917'>1917</a>
<a id='n1918' href='#n1918'>1918</a>
<a id='n1919' href='#n1919'>1919</a>
<a id='n1920' href='#n1920'>1920</a>
<a id='n1921' href='#n1921'>1921</a>
<a id='n1922' href='#n1922'>1922</a>
<a id='n1923' href='#n1923'>1923</a>
<a id='n1924' href='#n1924'>1924</a>
<a id='n1925' href='#n1925'>1925</a>
<a id='n1926' href='#n1926'>1926</a>
<a id='n1927' href='#n1927'>1927</a>
<a id='n1928' href='#n1928'>1928</a>
<a id='n1929' href='#n1929'>1929</a>
<a id='n1930' href='#n1930'>1930</a>
<a id='n1931' href='#n1931'>1931</a>
<a id='n1932' href='#n1932'>1932</a>
<a id='n1933' href='#n1933'>1933</a>
<a id='n1934' href='#n1934'>1934</a>
<a id='n1935' href='#n1935'>1935</a>
<a id='n1936' href='#n1936'>1936</a>
<a id='n1937' href='#n1937'>1937</a>
<a id='n1938' href='#n1938'>1938</a>
<a id='n1939' href='#n1939'>1939</a>
<a id='n1940' href='#n1940'>1940</a>
<a id='n1941' href='#n1941'>1941</a>
<a id='n1942' href='#n1942'>1942</a>
<a id='n1943' href='#n1943'>1943</a>
<a id='n1944' href='#n1944'>1944</a>
<a id='n1945' href='#n1945'>1945</a>
<a id='n1946' href='#n1946'>1946</a>
<a id='n1947' href='#n1947'>1947</a>
<a id='n1948' href='#n1948'>1948</a>
<a id='n1949' href='#n1949'>1949</a>
<a id='n1950' href='#n1950'>1950</a>
<a id='n1951' href='#n1951'>1951</a>
<a id='n1952' href='#n1952'>1952</a>
<a id='n1953' href='#n1953'>1953</a>
<a id='n1954' href='#n1954'>1954</a>
<a id='n1955' href='#n1955'>1955</a>
<a id='n1956' href='#n1956'>1956</a>
<a id='n1957' href='#n1957'>1957</a>
<a id='n1958' href='#n1958'>1958</a>
<a id='n1959' href='#n1959'>1959</a>
<a id='n1960' href='#n1960'>1960</a>
<a id='n1961' href='#n1961'>1961</a>
<a id='n1962' href='#n1962'>1962</a>
<a id='n1963' href='#n1963'>1963</a>
<a id='n1964' href='#n1964'>1964</a>
<a id='n1965' href='#n1965'>1965</a>
<a id='n1966' href='#n1966'>1966</a>
<a id='n1967' href='#n1967'>1967</a>
<a id='n1968' href='#n1968'>1968</a>
<a id='n1969' href='#n1969'>1969</a>
<a id='n1970' href='#n1970'>1970</a>
<a id='n1971' href='#n1971'>1971</a>
<a id='n1972' href='#n1972'>1972</a>
<a id='n1973' href='#n1973'>1973</a>
<a id='n1974' href='#n1974'>1974</a>
<a id='n1975' href='#n1975'>1975</a>
<a id='n1976' href='#n1976'>1976</a>
<a id='n1977' href='#n1977'>1977</a>
<a id='n1978' href='#n1978'>1978</a>
<a id='n1979' href='#n1979'>1979</a>
<a id='n1980' href='#n1980'>1980</a>
<a id='n1981' href='#n1981'>1981</a>
<a id='n1982' href='#n1982'>1982</a>
<a id='n1983' href='#n1983'>1983</a>
<a id='n1984' href='#n1984'>1984</a>
<a id='n1985' href='#n1985'>1985</a>
<a id='n1986' href='#n1986'>1986</a>
<a id='n1987' href='#n1987'>1987</a>
<a id='n1988' href='#n1988'>1988</a>
<a id='n1989' href='#n1989'>1989</a>
<a id='n1990' href='#n1990'>1990</a>
<a id='n1991' href='#n1991'>1991</a>
<a id='n1992' href='#n1992'>1992</a>
<a id='n1993' href='#n1993'>1993</a>
<a id='n1994' href='#n1994'>1994</a>
<a id='n1995' href='#n1995'>1995</a>
<a id='n1996' href='#n1996'>1996</a>
<a id='n1997' href='#n1997'>1997</a>
<a id='n1998' href='#n1998'>1998</a>
<a id='n1999' href='#n1999'>1999</a>
<a id='n2000' href='#n2000'>2000</a>
<a id='n2001' href='#n2001'>2001</a>
<a id='n2002' href='#n2002'>2002</a>
<a id='n2003' href='#n2003'>2003</a>
<a id='n2004' href='#n2004'>2004</a>
<a id='n2005' href='#n2005'>2005</a>
<a id='n2006' href='#n2006'>2006</a>
<a id='n2007' href='#n2007'>2007</a>
<a id='n2008' href='#n2008'>2008</a>
<a id='n2009' href='#n2009'>2009</a>
<a id='n2010' href='#n2010'>2010</a>
<a id='n2011' href='#n2011'>2011</a>
<a id='n2012' href='#n2012'>2012</a>
<a id='n2013' href='#n2013'>2013</a>
<a id='n2014' href='#n2014'>2014</a>
<a id='n2015' href='#n2015'>2015</a>
<a id='n2016' href='#n2016'>2016</a>
<a id='n2017' href='#n2017'>2017</a>
<a id='n2018' href='#n2018'>2018</a>
<a id='n2019' href='#n2019'>2019</a>
<a id='n2020' href='#n2020'>2020</a>
<a id='n2021' href='#n2021'>2021</a>
<a id='n2022' href='#n2022'>2022</a>
<a id='n2023' href='#n2023'>2023</a>
<a id='n2024' href='#n2024'>2024</a>
<a id='n2025' href='#n2025'>2025</a>
<a id='n2026' href='#n2026'>2026</a>
<a id='n2027' href='#n2027'>2027</a>
<a id='n2028' href='#n2028'>2028</a>
<a id='n2029' href='#n2029'>2029</a>
<a id='n2030' href='#n2030'>2030</a>
<a id='n2031' href='#n2031'>2031</a>
<a id='n2032' href='#n2032'>2032</a>
<a id='n2033' href='#n2033'>2033</a>
<a id='n2034' href='#n2034'>2034</a>
<a id='n2035' href='#n2035'>2035</a>
<a id='n2036' href='#n2036'>2036</a>
<a id='n2037' href='#n2037'>2037</a>
<a id='n2038' href='#n2038'>2038</a>
<a id='n2039' href='#n2039'>2039</a>
<a id='n2040' href='#n2040'>2040</a>
<a id='n2041' href='#n2041'>2041</a>
<a id='n2042' href='#n2042'>2042</a>
<a id='n2043' href='#n2043'>2043</a>
<a id='n2044' href='#n2044'>2044</a>
<a id='n2045' href='#n2045'>2045</a>
<a id='n2046' href='#n2046'>2046</a>
<a id='n2047' href='#n2047'>2047</a>
<a id='n2048' href='#n2048'>2048</a>
<a id='n2049' href='#n2049'>2049</a>
<a id='n2050' href='#n2050'>2050</a>
<a id='n2051' href='#n2051'>2051</a>
<a id='n2052' href='#n2052'>2052</a>
<a id='n2053' href='#n2053'>2053</a>
<a id='n2054' href='#n2054'>2054</a>
<a id='n2055' href='#n2055'>2055</a>
<a id='n2056' href='#n2056'>2056</a>
<a id='n2057' href='#n2057'>2057</a>
<a id='n2058' href='#n2058'>2058</a>
<a id='n2059' href='#n2059'>2059</a>
<a id='n2060' href='#n2060'>2060</a>
<a id='n2061' href='#n2061'>2061</a>
<a id='n2062' href='#n2062'>2062</a>
<a id='n2063' href='#n2063'>2063</a>
<a id='n2064' href='#n2064'>2064</a>
<a id='n2065' href='#n2065'>2065</a>
<a id='n2066' href='#n2066'>2066</a>
<a id='n2067' href='#n2067'>2067</a>
<a id='n2068' href='#n2068'>2068</a>
<a id='n2069' href='#n2069'>2069</a>
<a id='n2070' href='#n2070'>2070</a>
<a id='n2071' href='#n2071'>2071</a>
<a id='n2072' href='#n2072'>2072</a>
<a id='n2073' href='#n2073'>2073</a>
<a id='n2074' href='#n2074'>2074</a>
<a id='n2075' href='#n2075'>2075</a>
<a id='n2076' href='#n2076'>2076</a>
<a id='n2077' href='#n2077'>2077</a>
<a id='n2078' href='#n2078'>2078</a>
<a id='n2079' href='#n2079'>2079</a>
<a id='n2080' href='#n2080'>2080</a>
<a id='n2081' href='#n2081'>2081</a>
<a id='n2082' href='#n2082'>2082</a>
<a id='n2083' href='#n2083'>2083</a>
<a id='n2084' href='#n2084'>2084</a>
<a id='n2085' href='#n2085'>2085</a>
<a id='n2086' href='#n2086'>2086</a>
<a id='n2087' href='#n2087'>2087</a>
<a id='n2088' href='#n2088'>2088</a>
<a id='n2089' href='#n2089'>2089</a>
<a id='n2090' href='#n2090'>2090</a>
<a id='n2091' href='#n2091'>2091</a>
<a id='n2092' href='#n2092'>2092</a>
<a id='n2093' href='#n2093'>2093</a>
<a id='n2094' href='#n2094'>2094</a>
<a id='n2095' href='#n2095'>2095</a>
<a id='n2096' href='#n2096'>2096</a>
<a id='n2097' href='#n2097'>2097</a>
<a id='n2098' href='#n2098'>2098</a>
<a id='n2099' href='#n2099'>2099</a>
<a id='n2100' href='#n2100'>2100</a>
<a id='n2101' href='#n2101'>2101</a>
<a id='n2102' href='#n2102'>2102</a>
<a id='n2103' href='#n2103'>2103</a>
<a id='n2104' href='#n2104'>2104</a>
<a id='n2105' href='#n2105'>2105</a>
<a id='n2106' href='#n2106'>2106</a>
<a id='n2107' href='#n2107'>2107</a>
<a id='n2108' href='#n2108'>2108</a>
<a id='n2109' href='#n2109'>2109</a>
<a id='n2110' href='#n2110'>2110</a>
<a id='n2111' href='#n2111'>2111</a>
<a id='n2112' href='#n2112'>2112</a>
<a id='n2113' href='#n2113'>2113</a>
<a id='n2114' href='#n2114'>2114</a>
<a id='n2115' href='#n2115'>2115</a>
<a id='n2116' href='#n2116'>2116</a>
<a id='n2117' href='#n2117'>2117</a>
<a id='n2118' href='#n2118'>2118</a>
<a id='n2119' href='#n2119'>2119</a>
<a id='n2120' href='#n2120'>2120</a>
<a id='n2121' href='#n2121'>2121</a>
<a id='n2122' href='#n2122'>2122</a>
<a id='n2123' href='#n2123'>2123</a>
<a id='n2124' href='#n2124'>2124</a>
<a id='n2125' href='#n2125'>2125</a>
<a id='n2126' href='#n2126'>2126</a>
<a id='n2127' href='#n2127'>2127</a>
<a id='n2128' href='#n2128'>2128</a>
<a id='n2129' href='#n2129'>2129</a>
<a id='n2130' href='#n2130'>2130</a>
<a id='n2131' href='#n2131'>2131</a>
<a id='n2132' href='#n2132'>2132</a>
<a id='n2133' href='#n2133'>2133</a>
<a id='n2134' href='#n2134'>2134</a>
<a id='n2135' href='#n2135'>2135</a>
<a id='n2136' href='#n2136'>2136</a>
<a id='n2137' href='#n2137'>2137</a>
<a id='n2138' href='#n2138'>2138</a>
<a id='n2139' href='#n2139'>2139</a>
<a id='n2140' href='#n2140'>2140</a>
<a id='n2141' href='#n2141'>2141</a>
<a id='n2142' href='#n2142'>2142</a>
<a id='n2143' href='#n2143'>2143</a>
<a id='n2144' href='#n2144'>2144</a>
<a id='n2145' href='#n2145'>2145</a>
<a id='n2146' href='#n2146'>2146</a>
<a id='n2147' href='#n2147'>2147</a>
<a id='n2148' href='#n2148'>2148</a>
<a id='n2149' href='#n2149'>2149</a>
<a id='n2150' href='#n2150'>2150</a>
<a id='n2151' href='#n2151'>2151</a>
<a id='n2152' href='#n2152'>2152</a>
<a id='n2153' href='#n2153'>2153</a>
<a id='n2154' href='#n2154'>2154</a>
<a id='n2155' href='#n2155'>2155</a>
<a id='n2156' href='#n2156'>2156</a>
<a id='n2157' href='#n2157'>2157</a>
<a id='n2158' href='#n2158'>2158</a>
<a id='n2159' href='#n2159'>2159</a>
<a id='n2160' href='#n2160'>2160</a>
<a id='n2161' href='#n2161'>2161</a>
<a id='n2162' href='#n2162'>2162</a>
<a id='n2163' href='#n2163'>2163</a>
<a id='n2164' href='#n2164'>2164</a>
<a id='n2165' href='#n2165'>2165</a>
<a id='n2166' href='#n2166'>2166</a>
<a id='n2167' href='#n2167'>2167</a>
<a id='n2168' href='#n2168'>2168</a>
<a id='n2169' href='#n2169'>2169</a>
<a id='n2170' href='#n2170'>2170</a>
<a id='n2171' href='#n2171'>2171</a>
<a id='n2172' href='#n2172'>2172</a>
<a id='n2173' href='#n2173'>2173</a>
<a id='n2174' href='#n2174'>2174</a>
<a id='n2175' href='#n2175'>2175</a>
<a id='n2176' href='#n2176'>2176</a>
<a id='n2177' href='#n2177'>2177</a>
<a id='n2178' href='#n2178'>2178</a>
<a id='n2179' href='#n2179'>2179</a>
<a id='n2180' href='#n2180'>2180</a>
<a id='n2181' href='#n2181'>2181</a>
<a id='n2182' href='#n2182'>2182</a>
<a id='n2183' href='#n2183'>2183</a>
<a id='n2184' href='#n2184'>2184</a>
<a id='n2185' href='#n2185'>2185</a>
<a id='n2186' href='#n2186'>2186</a>
<a id='n2187' href='#n2187'>2187</a>
<a id='n2188' href='#n2188'>2188</a>
<a id='n2189' href='#n2189'>2189</a>
<a id='n2190' href='#n2190'>2190</a>
<a id='n2191' href='#n2191'>2191</a>
<a id='n2192' href='#n2192'>2192</a>
<a id='n2193' href='#n2193'>2193</a>
<a id='n2194' href='#n2194'>2194</a>
<a id='n2195' href='#n2195'>2195</a>
<a id='n2196' href='#n2196'>2196</a>
<a id='n2197' href='#n2197'>2197</a>
<a id='n2198' href='#n2198'>2198</a>
<a id='n2199' href='#n2199'>2199</a>
<a id='n2200' href='#n2200'>2200</a>
<a id='n2201' href='#n2201'>2201</a>
<a id='n2202' href='#n2202'>2202</a>
<a id='n2203' href='#n2203'>2203</a>
<a id='n2204' href='#n2204'>2204</a>
<a id='n2205' href='#n2205'>2205</a>
<a id='n2206' href='#n2206'>2206</a>
<a id='n2207' href='#n2207'>2207</a>
<a id='n2208' href='#n2208'>2208</a>
<a id='n2209' href='#n2209'>2209</a>
<a id='n2210' href='#n2210'>2210</a>
<a id='n2211' href='#n2211'>2211</a>
<a id='n2212' href='#n2212'>2212</a>
<a id='n2213' href='#n2213'>2213</a>
<a id='n2214' href='#n2214'>2214</a>
<a id='n2215' href='#n2215'>2215</a>
<a id='n2216' href='#n2216'>2216</a>
<a id='n2217' href='#n2217'>2217</a>
<a id='n2218' href='#n2218'>2218</a>
<a id='n2219' href='#n2219'>2219</a>
<a id='n2220' href='#n2220'>2220</a>
<a id='n2221' href='#n2221'>2221</a>
<a id='n2222' href='#n2222'>2222</a>
<a id='n2223' href='#n2223'>2223</a>
<a id='n2224' href='#n2224'>2224</a>
<a id='n2225' href='#n2225'>2225</a>
<a id='n2226' href='#n2226'>2226</a>
<a id='n2227' href='#n2227'>2227</a>
<a id='n2228' href='#n2228'>2228</a>
<a id='n2229' href='#n2229'>2229</a>
<a id='n2230' href='#n2230'>2230</a>
<a id='n2231' href='#n2231'>2231</a>
<a id='n2232' href='#n2232'>2232</a>
<a id='n2233' href='#n2233'>2233</a>
<a id='n2234' href='#n2234'>2234</a>
<a id='n2235' href='#n2235'>2235</a>
<a id='n2236' href='#n2236'>2236</a>
<a id='n2237' href='#n2237'>2237</a>
<a id='n2238' href='#n2238'>2238</a>
<a id='n2239' href='#n2239'>2239</a>
<a id='n2240' href='#n2240'>2240</a>
<a id='n2241' href='#n2241'>2241</a>
<a id='n2242' href='#n2242'>2242</a>
<a id='n2243' href='#n2243'>2243</a>
<a id='n2244' href='#n2244'>2244</a>
<a id='n2245' href='#n2245'>2245</a>
<a id='n2246' href='#n2246'>2246</a>
<a id='n2247' href='#n2247'>2247</a>
<a id='n2248' href='#n2248'>2248</a>
<a id='n2249' href='#n2249'>2249</a>
<a id='n2250' href='#n2250'>2250</a>
<a id='n2251' href='#n2251'>2251</a>
<a id='n2252' href='#n2252'>2252</a>
<a id='n2253' href='#n2253'>2253</a>
<a id='n2254' href='#n2254'>2254</a>
<a id='n2255' href='#n2255'>2255</a>
<a id='n2256' href='#n2256'>2256</a>
<a id='n2257' href='#n2257'>2257</a>
<a id='n2258' href='#n2258'>2258</a>
<a id='n2259' href='#n2259'>2259</a>
<a id='n2260' href='#n2260'>2260</a>
<a id='n2261' href='#n2261'>2261</a>
<a id='n2262' href='#n2262'>2262</a>
<a id='n2263' href='#n2263'>2263</a>
<a id='n2264' href='#n2264'>2264</a>
<a id='n2265' href='#n2265'>2265</a>
<a id='n2266' href='#n2266'>2266</a>
<a id='n2267' href='#n2267'>2267</a>
<a id='n2268' href='#n2268'>2268</a>
<a id='n2269' href='#n2269'>2269</a>
<a id='n2270' href='#n2270'>2270</a>
<a id='n2271' href='#n2271'>2271</a>
<a id='n2272' href='#n2272'>2272</a>
<a id='n2273' href='#n2273'>2273</a>
<a id='n2274' href='#n2274'>2274</a>
<a id='n2275' href='#n2275'>2275</a>
<a id='n2276' href='#n2276'>2276</a>
<a id='n2277' href='#n2277'>2277</a>
<a id='n2278' href='#n2278'>2278</a>
<a id='n2279' href='#n2279'>2279</a>
<a id='n2280' href='#n2280'>2280</a>
<a id='n2281' href='#n2281'>2281</a>
<a id='n2282' href='#n2282'>2282</a>
<a id='n2283' href='#n2283'>2283</a>
<a id='n2284' href='#n2284'>2284</a>
<a id='n2285' href='#n2285'>2285</a>
<a id='n2286' href='#n2286'>2286</a>
<a id='n2287' href='#n2287'>2287</a>
<a id='n2288' href='#n2288'>2288</a>
<a id='n2289' href='#n2289'>2289</a>
<a id='n2290' href='#n2290'>2290</a>
<a id='n2291' href='#n2291'>2291</a>
<a id='n2292' href='#n2292'>2292</a>
<a id='n2293' href='#n2293'>2293</a>
<a id='n2294' href='#n2294'>2294</a>
<a id='n2295' href='#n2295'>2295</a>
<a id='n2296' href='#n2296'>2296</a>
<a id='n2297' href='#n2297'>2297</a>
<a id='n2298' href='#n2298'>2298</a>
<a id='n2299' href='#n2299'>2299</a>
<a id='n2300' href='#n2300'>2300</a>
<a id='n2301' href='#n2301'>2301</a>
<a id='n2302' href='#n2302'>2302</a>
<a id='n2303' href='#n2303'>2303</a>
<a id='n2304' href='#n2304'>2304</a>
<a id='n2305' href='#n2305'>2305</a>
<a id='n2306' href='#n2306'>2306</a>
<a id='n2307' href='#n2307'>2307</a>
<a id='n2308' href='#n2308'>2308</a>
<a id='n2309' href='#n2309'>2309</a>
<a id='n2310' href='#n2310'>2310</a>
<a id='n2311' href='#n2311'>2311</a>
<a id='n2312' href='#n2312'>2312</a>
<a id='n2313' href='#n2313'>2313</a>
<a id='n2314' href='#n2314'>2314</a>
<a id='n2315' href='#n2315'>2315</a>
<a id='n2316' href='#n2316'>2316</a>
<a id='n2317' href='#n2317'>2317</a>
<a id='n2318' href='#n2318'>2318</a>
<a id='n2319' href='#n2319'>2319</a>
<a id='n2320' href='#n2320'>2320</a>
<a id='n2321' href='#n2321'>2321</a>
<a id='n2322' href='#n2322'>2322</a>
<a id='n2323' href='#n2323'>2323</a>
<a id='n2324' href='#n2324'>2324</a>
<a id='n2325' href='#n2325'>2325</a>
<a id='n2326' href='#n2326'>2326</a>
<a id='n2327' href='#n2327'>2327</a>
<a id='n2328' href='#n2328'>2328</a>
<a id='n2329' href='#n2329'>2329</a>
<a id='n2330' href='#n2330'>2330</a>
<a id='n2331' href='#n2331'>2331</a>
<a id='n2332' href='#n2332'>2332</a>
<a id='n2333' href='#n2333'>2333</a>
<a id='n2334' href='#n2334'>2334</a>
<a id='n2335' href='#n2335'>2335</a>
<a id='n2336' href='#n2336'>2336</a>
<a id='n2337' href='#n2337'>2337</a>
<a id='n2338' href='#n2338'>2338</a>
<a id='n2339' href='#n2339'>2339</a>
<a id='n2340' href='#n2340'>2340</a>
<a id='n2341' href='#n2341'>2341</a>
<a id='n2342' href='#n2342'>2342</a>
<a id='n2343' href='#n2343'>2343</a>
<a id='n2344' href='#n2344'>2344</a>
<a id='n2345' href='#n2345'>2345</a>
<a id='n2346' href='#n2346'>2346</a>
<a id='n2347' href='#n2347'>2347</a>
<a id='n2348' href='#n2348'>2348</a>
<a id='n2349' href='#n2349'>2349</a>
<a id='n2350' href='#n2350'>2350</a>
<a id='n2351' href='#n2351'>2351</a>
<a id='n2352' href='#n2352'>2352</a>
<a id='n2353' href='#n2353'>2353</a>
<a id='n2354' href='#n2354'>2354</a>
<a id='n2355' href='#n2355'>2355</a>
<a id='n2356' href='#n2356'>2356</a>
<a id='n2357' href='#n2357'>2357</a>
<a id='n2358' href='#n2358'>2358</a>
<a id='n2359' href='#n2359'>2359</a>
<a id='n2360' href='#n2360'>2360</a>
<a id='n2361' href='#n2361'>2361</a>
<a id='n2362' href='#n2362'>2362</a>
<a id='n2363' href='#n2363'>2363</a>
<a id='n2364' href='#n2364'>2364</a>
<a id='n2365' href='#n2365'>2365</a>
<a id='n2366' href='#n2366'>2366</a>
<a id='n2367' href='#n2367'>2367</a>
<a id='n2368' href='#n2368'>2368</a>
<a id='n2369' href='#n2369'>2369</a>
<a id='n2370' href='#n2370'>2370</a>
<a id='n2371' href='#n2371'>2371</a>
<a id='n2372' href='#n2372'>2372</a>
<a id='n2373' href='#n2373'>2373</a>
<a id='n2374' href='#n2374'>2374</a>
<a id='n2375' href='#n2375'>2375</a>
<a id='n2376' href='#n2376'>2376</a>
<a id='n2377' href='#n2377'>2377</a>
<a id='n2378' href='#n2378'>2378</a>
<a id='n2379' href='#n2379'>2379</a>
<a id='n2380' href='#n2380'>2380</a>
<a id='n2381' href='#n2381'>2381</a>
<a id='n2382' href='#n2382'>2382</a>
<a id='n2383' href='#n2383'>2383</a>
<a id='n2384' href='#n2384'>2384</a>
<a id='n2385' href='#n2385'>2385</a>
<a id='n2386' href='#n2386'>2386</a>
<a id='n2387' href='#n2387'>2387</a>
<a id='n2388' href='#n2388'>2388</a>
<a id='n2389' href='#n2389'>2389</a>
<a id='n2390' href='#n2390'>2390</a>
<a id='n2391' href='#n2391'>2391</a>
<a id='n2392' href='#n2392'>2392</a>
<a id='n2393' href='#n2393'>2393</a>
<a id='n2394' href='#n2394'>2394</a>
<a id='n2395' href='#n2395'>2395</a>
<a id='n2396' href='#n2396'>2396</a>
<a id='n2397' href='#n2397'>2397</a>
<a id='n2398' href='#n2398'>2398</a>
<a id='n2399' href='#n2399'>2399</a>
<a id='n2400' href='#n2400'>2400</a>
<a id='n2401' href='#n2401'>2401</a>
<a id='n2402' href='#n2402'>2402</a>
<a id='n2403' href='#n2403'>2403</a>
<a id='n2404' href='#n2404'>2404</a>
<a id='n2405' href='#n2405'>2405</a>
<a id='n2406' href='#n2406'>2406</a>
<a id='n2407' href='#n2407'>2407</a>
<a id='n2408' href='#n2408'>2408</a>
<a id='n2409' href='#n2409'>2409</a>
<a id='n2410' href='#n2410'>2410</a>
<a id='n2411' href='#n2411'>2411</a>
<a id='n2412' href='#n2412'>2412</a>
<a id='n2413' href='#n2413'>2413</a>
<a id='n2414' href='#n2414'>2414</a>
<a id='n2415' href='#n2415'>2415</a>
<a id='n2416' href='#n2416'>2416</a>
<a id='n2417' href='#n2417'>2417</a>
<a id='n2418' href='#n2418'>2418</a>
<a id='n2419' href='#n2419'>2419</a>
<a id='n2420' href='#n2420'>2420</a>
<a id='n2421' href='#n2421'>2421</a>
<a id='n2422' href='#n2422'>2422</a>
<a id='n2423' href='#n2423'>2423</a>
<a id='n2424' href='#n2424'>2424</a>
<a id='n2425' href='#n2425'>2425</a>
<a id='n2426' href='#n2426'>2426</a>
<a id='n2427' href='#n2427'>2427</a>
<a id='n2428' href='#n2428'>2428</a>
<a id='n2429' href='#n2429'>2429</a>
<a id='n2430' href='#n2430'>2430</a>
<a id='n2431' href='#n2431'>2431</a>
<a id='n2432' href='#n2432'>2432</a>
<a id='n2433' href='#n2433'>2433</a>
<a id='n2434' href='#n2434'>2434</a>
<a id='n2435' href='#n2435'>2435</a>
<a id='n2436' href='#n2436'>2436</a>
<a id='n2437' href='#n2437'>2437</a>
<a id='n2438' href='#n2438'>2438</a>
<a id='n2439' href='#n2439'>2439</a>
<a id='n2440' href='#n2440'>2440</a>
<a id='n2441' href='#n2441'>2441</a>
<a id='n2442' href='#n2442'>2442</a>
<a id='n2443' href='#n2443'>2443</a>
<a id='n2444' href='#n2444'>2444</a>
<a id='n2445' href='#n2445'>2445</a>
<a id='n2446' href='#n2446'>2446</a>
<a id='n2447' href='#n2447'>2447</a>
<a id='n2448' href='#n2448'>2448</a>
<a id='n2449' href='#n2449'>2449</a>
<a id='n2450' href='#n2450'>2450</a>
<a id='n2451' href='#n2451'>2451</a>
<a id='n2452' href='#n2452'>2452</a>
<a id='n2453' href='#n2453'>2453</a>
<a id='n2454' href='#n2454'>2454</a>
<a id='n2455' href='#n2455'>2455</a>
<a id='n2456' href='#n2456'>2456</a>
<a id='n2457' href='#n2457'>2457</a>
<a id='n2458' href='#n2458'>2458</a>
<a id='n2459' href='#n2459'>2459</a>
<a id='n2460' href='#n2460'>2460</a>
<a id='n2461' href='#n2461'>2461</a>
<a id='n2462' href='#n2462'>2462</a>
<a id='n2463' href='#n2463'>2463</a>
<a id='n2464' href='#n2464'>2464</a>
<a id='n2465' href='#n2465'>2465</a>
<a id='n2466' href='#n2466'>2466</a>
<a id='n2467' href='#n2467'>2467</a>
<a id='n2468' href='#n2468'>2468</a>
<a id='n2469' href='#n2469'>2469</a>
<a id='n2470' href='#n2470'>2470</a>
<a id='n2471' href='#n2471'>2471</a>
<a id='n2472' href='#n2472'>2472</a>
<a id='n2473' href='#n2473'>2473</a>
<a id='n2474' href='#n2474'>2474</a>
<a id='n2475' href='#n2475'>2475</a>
<a id='n2476' href='#n2476'>2476</a>
<a id='n2477' href='#n2477'>2477</a>
<a id='n2478' href='#n2478'>2478</a>
<a id='n2479' href='#n2479'>2479</a>
<a id='n2480' href='#n2480'>2480</a>
<a id='n2481' href='#n2481'>2481</a>
<a id='n2482' href='#n2482'>2482</a>
<a id='n2483' href='#n2483'>2483</a>
<a id='n2484' href='#n2484'>2484</a>
<a id='n2485' href='#n2485'>2485</a>
<a id='n2486' href='#n2486'>2486</a>
<a id='n2487' href='#n2487'>2487</a>
<a id='n2488' href='#n2488'>2488</a>
<a id='n2489' href='#n2489'>2489</a>
<a id='n2490' href='#n2490'>2490</a>
<a id='n2491' href='#n2491'>2491</a>
<a id='n2492' href='#n2492'>2492</a>
<a id='n2493' href='#n2493'>2493</a>
<a id='n2494' href='#n2494'>2494</a>
<a id='n2495' href='#n2495'>2495</a>
<a id='n2496' href='#n2496'>2496</a>
<a id='n2497' href='#n2497'>2497</a>
<a id='n2498' href='#n2498'>2498</a>
<a id='n2499' href='#n2499'>2499</a>
<a id='n2500' href='#n2500'>2500</a>
<a id='n2501' href='#n2501'>2501</a>
<a id='n2502' href='#n2502'>2502</a>
<a id='n2503' href='#n2503'>2503</a>
<a id='n2504' href='#n2504'>2504</a>
<a id='n2505' href='#n2505'>2505</a>
<a id='n2506' href='#n2506'>2506</a>
<a id='n2507' href='#n2507'>2507</a>
<a id='n2508' href='#n2508'>2508</a>
<a id='n2509' href='#n2509'>2509</a>
<a id='n2510' href='#n2510'>2510</a>
<a id='n2511' href='#n2511'>2511</a>
<a id='n2512' href='#n2512'>2512</a>
<a id='n2513' href='#n2513'>2513</a>
<a id='n2514' href='#n2514'>2514</a>
<a id='n2515' href='#n2515'>2515</a>
<a id='n2516' href='#n2516'>2516</a>
<a id='n2517' href='#n2517'>2517</a>
<a id='n2518' href='#n2518'>2518</a>
<a id='n2519' href='#n2519'>2519</a>
<a id='n2520' href='#n2520'>2520</a>
<a id='n2521' href='#n2521'>2521</a>
<a id='n2522' href='#n2522'>2522</a>
<a id='n2523' href='#n2523'>2523</a>
<a id='n2524' href='#n2524'>2524</a>
<a id='n2525' href='#n2525'>2525</a>
<a id='n2526' href='#n2526'>2526</a>
<a id='n2527' href='#n2527'>2527</a>
<a id='n2528' href='#n2528'>2528</a>
<a id='n2529' href='#n2529'>2529</a>
<a id='n2530' href='#n2530'>2530</a>
<a id='n2531' href='#n2531'>2531</a>
<a id='n2532' href='#n2532'>2532</a>
<a id='n2533' href='#n2533'>2533</a>
<a id='n2534' href='#n2534'>2534</a>
<a id='n2535' href='#n2535'>2535</a>
<a id='n2536' href='#n2536'>2536</a>
<a id='n2537' href='#n2537'>2537</a>
<a id='n2538' href='#n2538'>2538</a>
<a id='n2539' href='#n2539'>2539</a>
<a id='n2540' href='#n2540'>2540</a>
<a id='n2541' href='#n2541'>2541</a>
<a id='n2542' href='#n2542'>2542</a>
<a id='n2543' href='#n2543'>2543</a>
<a id='n2544' href='#n2544'>2544</a>
<a id='n2545' href='#n2545'>2545</a>
<a id='n2546' href='#n2546'>2546</a>
<a id='n2547' href='#n2547'>2547</a>
<a id='n2548' href='#n2548'>2548</a>
<a id='n2549' href='#n2549'>2549</a>
<a id='n2550' href='#n2550'>2550</a>
<a id='n2551' href='#n2551'>2551</a>
<a id='n2552' href='#n2552'>2552</a>
<a id='n2553' href='#n2553'>2553</a>
<a id='n2554' href='#n2554'>2554</a>
<a id='n2555' href='#n2555'>2555</a>
<a id='n2556' href='#n2556'>2556</a>
<a id='n2557' href='#n2557'>2557</a>
<a id='n2558' href='#n2558'>2558</a>
<a id='n2559' href='#n2559'>2559</a>
<a id='n2560' href='#n2560'>2560</a>
<a id='n2561' href='#n2561'>2561</a>
<a id='n2562' href='#n2562'>2562</a>
<a id='n2563' href='#n2563'>2563</a>
<a id='n2564' href='#n2564'>2564</a>
<a id='n2565' href='#n2565'>2565</a>
<a id='n2566' href='#n2566'>2566</a>
<a id='n2567' href='#n2567'>2567</a>
<a id='n2568' href='#n2568'>2568</a>
<a id='n2569' href='#n2569'>2569</a>
<a id='n2570' href='#n2570'>2570</a>
<a id='n2571' href='#n2571'>2571</a>
<a id='n2572' href='#n2572'>2572</a>
<a id='n2573' href='#n2573'>2573</a>
<a id='n2574' href='#n2574'>2574</a>
<a id='n2575' href='#n2575'>2575</a>
<a id='n2576' href='#n2576'>2576</a>
<a id='n2577' href='#n2577'>2577</a>
<a id='n2578' href='#n2578'>2578</a>
<a id='n2579' href='#n2579'>2579</a>
<a id='n2580' href='#n2580'>2580</a>
<a id='n2581' href='#n2581'>2581</a>
<a id='n2582' href='#n2582'>2582</a>
<a id='n2583' href='#n2583'>2583</a>
<a id='n2584' href='#n2584'>2584</a>
<a id='n2585' href='#n2585'>2585</a>
<a id='n2586' href='#n2586'>2586</a>
<a id='n2587' href='#n2587'>2587</a>
<a id='n2588' href='#n2588'>2588</a>
<a id='n2589' href='#n2589'>2589</a>
<a id='n2590' href='#n2590'>2590</a>
<a id='n2591' href='#n2591'>2591</a>
<a id='n2592' href='#n2592'>2592</a>
<a id='n2593' href='#n2593'>2593</a>
<a id='n2594' href='#n2594'>2594</a>
<a id='n2595' href='#n2595'>2595</a>
<a id='n2596' href='#n2596'>2596</a>
<a id='n2597' href='#n2597'>2597</a>
<a id='n2598' href='#n2598'>2598</a>
<a id='n2599' href='#n2599'>2599</a>
<a id='n2600' href='#n2600'>2600</a>
<a id='n2601' href='#n2601'>2601</a>
<a id='n2602' href='#n2602'>2602</a>
<a id='n2603' href='#n2603'>2603</a>
<a id='n2604' href='#n2604'>2604</a>
<a id='n2605' href='#n2605'>2605</a>
<a id='n2606' href='#n2606'>2606</a>
<a id='n2607' href='#n2607'>2607</a>
<a id='n2608' href='#n2608'>2608</a>
<a id='n2609' href='#n2609'>2609</a>
<a id='n2610' href='#n2610'>2610</a>
<a id='n2611' href='#n2611'>2611</a>
<a id='n2612' href='#n2612'>2612</a>
<a id='n2613' href='#n2613'>2613</a>
<a id='n2614' href='#n2614'>2614</a>
<a id='n2615' href='#n2615'>2615</a>
<a id='n2616' href='#n2616'>2616</a>
<a id='n2617' href='#n2617'>2617</a>
<a id='n2618' href='#n2618'>2618</a>
<a id='n2619' href='#n2619'>2619</a>
<a id='n2620' href='#n2620'>2620</a>
<a id='n2621' href='#n2621'>2621</a>
<a id='n2622' href='#n2622'>2622</a>
<a id='n2623' href='#n2623'>2623</a>
<a id='n2624' href='#n2624'>2624</a>
<a id='n2625' href='#n2625'>2625</a>
<a id='n2626' href='#n2626'>2626</a>
<a id='n2627' href='#n2627'>2627</a>
<a id='n2628' href='#n2628'>2628</a>
<a id='n2629' href='#n2629'>2629</a>
<a id='n2630' href='#n2630'>2630</a>
<a id='n2631' href='#n2631'>2631</a>
<a id='n2632' href='#n2632'>2632</a>
<a id='n2633' href='#n2633'>2633</a>
<a id='n2634' href='#n2634'>2634</a>
<a id='n2635' href='#n2635'>2635</a>
<a id='n2636' href='#n2636'>2636</a>
<a id='n2637' href='#n2637'>2637</a>
<a id='n2638' href='#n2638'>2638</a>
<a id='n2639' href='#n2639'>2639</a>
<a id='n2640' href='#n2640'>2640</a>
<a id='n2641' href='#n2641'>2641</a>
<a id='n2642' href='#n2642'>2642</a>
<a id='n2643' href='#n2643'>2643</a>
<a id='n2644' href='#n2644'>2644</a>
<a id='n2645' href='#n2645'>2645</a>
<a id='n2646' href='#n2646'>2646</a>
<a id='n2647' href='#n2647'>2647</a>
<a id='n2648' href='#n2648'>2648</a>
<a id='n2649' href='#n2649'>2649</a>
<a id='n2650' href='#n2650'>2650</a>
<a id='n2651' href='#n2651'>2651</a>
<a id='n2652' href='#n2652'>2652</a>
<a id='n2653' href='#n2653'>2653</a>
<a id='n2654' href='#n2654'>2654</a>
<a id='n2655' href='#n2655'>2655</a>
<a id='n2656' href='#n2656'>2656</a>
<a id='n2657' href='#n2657'>2657</a>
<a id='n2658' href='#n2658'>2658</a>
<a id='n2659' href='#n2659'>2659</a>
<a id='n2660' href='#n2660'>2660</a>
<a id='n2661' href='#n2661'>2661</a>
<a id='n2662' href='#n2662'>2662</a>
<a id='n2663' href='#n2663'>2663</a>
<a id='n2664' href='#n2664'>2664</a>
<a id='n2665' href='#n2665'>2665</a>
<a id='n2666' href='#n2666'>2666</a>
<a id='n2667' href='#n2667'>2667</a>
<a id='n2668' href='#n2668'>2668</a>
<a id='n2669' href='#n2669'>2669</a>
<a id='n2670' href='#n2670'>2670</a>
<a id='n2671' href='#n2671'>2671</a>
<a id='n2672' href='#n2672'>2672</a>
<a id='n2673' href='#n2673'>2673</a>
<a id='n2674' href='#n2674'>2674</a>
<a id='n2675' href='#n2675'>2675</a>
<a id='n2676' href='#n2676'>2676</a>
<a id='n2677' href='#n2677'>2677</a>
<a id='n2678' href='#n2678'>2678</a>
<a id='n2679' href='#n2679'>2679</a>
<a id='n2680' href='#n2680'>2680</a>
<a id='n2681' href='#n2681'>2681</a>
<a id='n2682' href='#n2682'>2682</a>
<a id='n2683' href='#n2683'>2683</a>
<a id='n2684' href='#n2684'>2684</a>
<a id='n2685' href='#n2685'>2685</a>
<a id='n2686' href='#n2686'>2686</a>
<a id='n2687' href='#n2687'>2687</a>
<a id='n2688' href='#n2688'>2688</a>
<a id='n2689' href='#n2689'>2689</a>
<a id='n2690' href='#n2690'>2690</a>
<a id='n2691' href='#n2691'>2691</a>
<a id='n2692' href='#n2692'>2692</a>
<a id='n2693' href='#n2693'>2693</a>
<a id='n2694' href='#n2694'>2694</a>
<a id='n2695' href='#n2695'>2695</a>
<a id='n2696' href='#n2696'>2696</a>
<a id='n2697' href='#n2697'>2697</a>
<a id='n2698' href='#n2698'>2698</a>
<a id='n2699' href='#n2699'>2699</a>
<a id='n2700' href='#n2700'>2700</a>
<a id='n2701' href='#n2701'>2701</a>
<a id='n2702' href='#n2702'>2702</a>
<a id='n2703' href='#n2703'>2703</a>
<a id='n2704' href='#n2704'>2704</a>
<a id='n2705' href='#n2705'>2705</a>
<a id='n2706' href='#n2706'>2706</a>
<a id='n2707' href='#n2707'>2707</a>
<a id='n2708' href='#n2708'>2708</a>
<a id='n2709' href='#n2709'>2709</a>
<a id='n2710' href='#n2710'>2710</a>
<a id='n2711' href='#n2711'>2711</a>
<a id='n2712' href='#n2712'>2712</a>
<a id='n2713' href='#n2713'>2713</a>
<a id='n2714' href='#n2714'>2714</a>
<a id='n2715' href='#n2715'>2715</a>
<a id='n2716' href='#n2716'>2716</a>
<a id='n2717' href='#n2717'>2717</a>
<a id='n2718' href='#n2718'>2718</a>
<a id='n2719' href='#n2719'>2719</a>
<a id='n2720' href='#n2720'>2720</a>
<a id='n2721' href='#n2721'>2721</a>
<a id='n2722' href='#n2722'>2722</a>
<a id='n2723' href='#n2723'>2723</a>
<a id='n2724' href='#n2724'>2724</a>
<a id='n2725' href='#n2725'>2725</a>
<a id='n2726' href='#n2726'>2726</a>
<a id='n2727' href='#n2727'>2727</a>
<a id='n2728' href='#n2728'>2728</a>
<a id='n2729' href='#n2729'>2729</a>
<a id='n2730' href='#n2730'>2730</a>
<a id='n2731' href='#n2731'>2731</a>
<a id='n2732' href='#n2732'>2732</a>
<a id='n2733' href='#n2733'>2733</a>
<a id='n2734' href='#n2734'>2734</a>
<a id='n2735' href='#n2735'>2735</a>
<a id='n2736' href='#n2736'>2736</a>
<a id='n2737' href='#n2737'>2737</a>
<a id='n2738' href='#n2738'>2738</a>
<a id='n2739' href='#n2739'>2739</a>
<a id='n2740' href='#n2740'>2740</a>
<a id='n2741' href='#n2741'>2741</a>
<a id='n2742' href='#n2742'>2742</a>
<a id='n2743' href='#n2743'>2743</a>
<a id='n2744' href='#n2744'>2744</a>
<a id='n2745' href='#n2745'>2745</a>
<a id='n2746' href='#n2746'>2746</a>
<a id='n2747' href='#n2747'>2747</a>
<a id='n2748' href='#n2748'>2748</a>
<a id='n2749' href='#n2749'>2749</a>
<a id='n2750' href='#n2750'>2750</a>
<a id='n2751' href='#n2751'>2751</a>
<a id='n2752' href='#n2752'>2752</a>
<a id='n2753' href='#n2753'>2753</a>
<a id='n2754' href='#n2754'>2754</a>
<a id='n2755' href='#n2755'>2755</a>
<a id='n2756' href='#n2756'>2756</a>
<a id='n2757' href='#n2757'>2757</a>
<a id='n2758' href='#n2758'>2758</a>
<a id='n2759' href='#n2759'>2759</a>
<a id='n2760' href='#n2760'>2760</a>
<a id='n2761' href='#n2761'>2761</a>
<a id='n2762' href='#n2762'>2762</a>
<a id='n2763' href='#n2763'>2763</a>
<a id='n2764' href='#n2764'>2764</a>
<a id='n2765' href='#n2765'>2765</a>
<a id='n2766' href='#n2766'>2766</a>
<a id='n2767' href='#n2767'>2767</a>
<a id='n2768' href='#n2768'>2768</a>
<a id='n2769' href='#n2769'>2769</a>
<a id='n2770' href='#n2770'>2770</a>
<a id='n2771' href='#n2771'>2771</a>
<a id='n2772' href='#n2772'>2772</a>
<a id='n2773' href='#n2773'>2773</a>
<a id='n2774' href='#n2774'>2774</a>
<a id='n2775' href='#n2775'>2775</a>
<a id='n2776' href='#n2776'>2776</a>
<a id='n2777' href='#n2777'>2777</a>
<a id='n2778' href='#n2778'>2778</a>
<a id='n2779' href='#n2779'>2779</a>
<a id='n2780' href='#n2780'>2780</a>
<a id='n2781' href='#n2781'>2781</a>
<a id='n2782' href='#n2782'>2782</a>
<a id='n2783' href='#n2783'>2783</a>
<a id='n2784' href='#n2784'>2784</a>
<a id='n2785' href='#n2785'>2785</a>
<a id='n2786' href='#n2786'>2786</a>
<a id='n2787' href='#n2787'>2787</a>
<a id='n2788' href='#n2788'>2788</a>
<a id='n2789' href='#n2789'>2789</a>
<a id='n2790' href='#n2790'>2790</a>
<a id='n2791' href='#n2791'>2791</a>
<a id='n2792' href='#n2792'>2792</a>
<a id='n2793' href='#n2793'>2793</a>
<a id='n2794' href='#n2794'>2794</a>
<a id='n2795' href='#n2795'>2795</a>
<a id='n2796' href='#n2796'>2796</a>
<a id='n2797' href='#n2797'>2797</a>
<a id='n2798' href='#n2798'>2798</a>
<a id='n2799' href='#n2799'>2799</a>
<a id='n2800' href='#n2800'>2800</a>
<a id='n2801' href='#n2801'>2801</a>
<a id='n2802' href='#n2802'>2802</a>
<a id='n2803' href='#n2803'>2803</a>
<a id='n2804' href='#n2804'>2804</a>
<a id='n2805' href='#n2805'>2805</a>
<a id='n2806' href='#n2806'>2806</a>
<a id='n2807' href='#n2807'>2807</a>
<a id='n2808' href='#n2808'>2808</a>
<a id='n2809' href='#n2809'>2809</a>
<a id='n2810' href='#n2810'>2810</a>
<a id='n2811' href='#n2811'>2811</a>
<a id='n2812' href='#n2812'>2812</a>
<a id='n2813' href='#n2813'>2813</a>
<a id='n2814' href='#n2814'>2814</a>
<a id='n2815' href='#n2815'>2815</a>
<a id='n2816' href='#n2816'>2816</a>
<a id='n2817' href='#n2817'>2817</a>
<a id='n2818' href='#n2818'>2818</a>
<a id='n2819' href='#n2819'>2819</a>
<a id='n2820' href='#n2820'>2820</a>
<a id='n2821' href='#n2821'>2821</a>
<a id='n2822' href='#n2822'>2822</a>
<a id='n2823' href='#n2823'>2823</a>
<a id='n2824' href='#n2824'>2824</a>
<a id='n2825' href='#n2825'>2825</a>
<a id='n2826' href='#n2826'>2826</a>
<a id='n2827' href='#n2827'>2827</a>
<a id='n2828' href='#n2828'>2828</a>
<a id='n2829' href='#n2829'>2829</a>
<a id='n2830' href='#n2830'>2830</a>
<a id='n2831' href='#n2831'>2831</a>
<a id='n2832' href='#n2832'>2832</a>
<a id='n2833' href='#n2833'>2833</a>
<a id='n2834' href='#n2834'>2834</a>
<a id='n2835' href='#n2835'>2835</a>
<a id='n2836' href='#n2836'>2836</a>
<a id='n2837' href='#n2837'>2837</a>
<a id='n2838' href='#n2838'>2838</a>
<a id='n2839' href='#n2839'>2839</a>
<a id='n2840' href='#n2840'>2840</a>
<a id='n2841' href='#n2841'>2841</a>
<a id='n2842' href='#n2842'>2842</a>
<a id='n2843' href='#n2843'>2843</a>
<a id='n2844' href='#n2844'>2844</a>
<a id='n2845' href='#n2845'>2845</a>
<a id='n2846' href='#n2846'>2846</a>
<a id='n2847' href='#n2847'>2847</a>
<a id='n2848' href='#n2848'>2848</a>
<a id='n2849' href='#n2849'>2849</a>
<a id='n2850' href='#n2850'>2850</a>
<a id='n2851' href='#n2851'>2851</a>
<a id='n2852' href='#n2852'>2852</a>
<a id='n2853' href='#n2853'>2853</a>
<a id='n2854' href='#n2854'>2854</a>
<a id='n2855' href='#n2855'>2855</a>
<a id='n2856' href='#n2856'>2856</a>
<a id='n2857' href='#n2857'>2857</a>
<a id='n2858' href='#n2858'>2858</a>
<a id='n2859' href='#n2859'>2859</a>
<a id='n2860' href='#n2860'>2860</a>
<a id='n2861' href='#n2861'>2861</a>
<a id='n2862' href='#n2862'>2862</a>
<a id='n2863' href='#n2863'>2863</a>
<a id='n2864' href='#n2864'>2864</a>
<a id='n2865' href='#n2865'>2865</a>
<a id='n2866' href='#n2866'>2866</a>
<a id='n2867' href='#n2867'>2867</a>
<a id='n2868' href='#n2868'>2868</a>
<a id='n2869' href='#n2869'>2869</a>
<a id='n2870' href='#n2870'>2870</a>
<a id='n2871' href='#n2871'>2871</a>
<a id='n2872' href='#n2872'>2872</a>
<a id='n2873' href='#n2873'>2873</a>
<a id='n2874' href='#n2874'>2874</a>
<a id='n2875' href='#n2875'>2875</a>
<a id='n2876' href='#n2876'>2876</a>
<a id='n2877' href='#n2877'>2877</a>
<a id='n2878' href='#n2878'>2878</a>
<a id='n2879' href='#n2879'>2879</a>
<a id='n2880' href='#n2880'>2880</a>
<a id='n2881' href='#n2881'>2881</a>
<a id='n2882' href='#n2882'>2882</a>
<a id='n2883' href='#n2883'>2883</a>
<a id='n2884' href='#n2884'>2884</a>
<a id='n2885' href='#n2885'>2885</a>
<a id='n2886' href='#n2886'>2886</a>
<a id='n2887' href='#n2887'>2887</a>
<a id='n2888' href='#n2888'>2888</a>
<a id='n2889' href='#n2889'>2889</a>
<a id='n2890' href='#n2890'>2890</a>
<a id='n2891' href='#n2891'>2891</a>
<a id='n2892' href='#n2892'>2892</a>
<a id='n2893' href='#n2893'>2893</a>
<a id='n2894' href='#n2894'>2894</a>
<a id='n2895' href='#n2895'>2895</a>
<a id='n2896' href='#n2896'>2896</a>
<a id='n2897' href='#n2897'>2897</a>
<a id='n2898' href='#n2898'>2898</a>
<a id='n2899' href='#n2899'>2899</a>
<a id='n2900' href='#n2900'>2900</a>
<a id='n2901' href='#n2901'>2901</a>
<a id='n2902' href='#n2902'>2902</a>
<a id='n2903' href='#n2903'>2903</a>
<a id='n2904' href='#n2904'>2904</a>
<a id='n2905' href='#n2905'>2905</a>
<a id='n2906' href='#n2906'>2906</a>
<a id='n2907' href='#n2907'>2907</a>
<a id='n2908' href='#n2908'>2908</a>
<a id='n2909' href='#n2909'>2909</a>
<a id='n2910' href='#n2910'>2910</a>
<a id='n2911' href='#n2911'>2911</a>
<a id='n2912' href='#n2912'>2912</a>
<a id='n2913' href='#n2913'>2913</a>
<a id='n2914' href='#n2914'>2914</a>
<a id='n2915' href='#n2915'>2915</a>
<a id='n2916' href='#n2916'>2916</a>
<a id='n2917' href='#n2917'>2917</a>
<a id='n2918' href='#n2918'>2918</a>
<a id='n2919' href='#n2919'>2919</a>
<a id='n2920' href='#n2920'>2920</a>
<a id='n2921' href='#n2921'>2921</a>
<a id='n2922' href='#n2922'>2922</a>
<a id='n2923' href='#n2923'>2923</a>
<a id='n2924' href='#n2924'>2924</a>
<a id='n2925' href='#n2925'>2925</a>
<a id='n2926' href='#n2926'>2926</a>
<a id='n2927' href='#n2927'>2927</a>
<a id='n2928' href='#n2928'>2928</a>
<a id='n2929' href='#n2929'>2929</a>
<a id='n2930' href='#n2930'>2930</a>
<a id='n2931' href='#n2931'>2931</a>
<a id='n2932' href='#n2932'>2932</a>
<a id='n2933' href='#n2933'>2933</a>
<a id='n2934' href='#n2934'>2934</a>
<a id='n2935' href='#n2935'>2935</a>
<a id='n2936' href='#n2936'>2936</a>
<a id='n2937' href='#n2937'>2937</a>
<a id='n2938' href='#n2938'>2938</a>
<a id='n2939' href='#n2939'>2939</a>
<a id='n2940' href='#n2940'>2940</a>
<a id='n2941' href='#n2941'>2941</a>
<a id='n2942' href='#n2942'>2942</a>
<a id='n2943' href='#n2943'>2943</a>
<a id='n2944' href='#n2944'>2944</a>
<a id='n2945' href='#n2945'>2945</a>
<a id='n2946' href='#n2946'>2946</a>
<a id='n2947' href='#n2947'>2947</a>
<a id='n2948' href='#n2948'>2948</a>
<a id='n2949' href='#n2949'>2949</a>
<a id='n2950' href='#n2950'>2950</a>
<a id='n2951' href='#n2951'>2951</a>
<a id='n2952' href='#n2952'>2952</a>
<a id='n2953' href='#n2953'>2953</a>
<a id='n2954' href='#n2954'>2954</a>
<a id='n2955' href='#n2955'>2955</a>
<a id='n2956' href='#n2956'>2956</a>
<a id='n2957' href='#n2957'>2957</a>
<a id='n2958' href='#n2958'>2958</a>
<a id='n2959' href='#n2959'>2959</a>
<a id='n2960' href='#n2960'>2960</a>
<a id='n2961' href='#n2961'>2961</a>
<a id='n2962' href='#n2962'>2962</a>
<a id='n2963' href='#n2963'>2963</a>
<a id='n2964' href='#n2964'>2964</a>
<a id='n2965' href='#n2965'>2965</a>
<a id='n2966' href='#n2966'>2966</a>
<a id='n2967' href='#n2967'>2967</a>
<a id='n2968' href='#n2968'>2968</a>
<a id='n2969' href='#n2969'>2969</a>
<a id='n2970' href='#n2970'>2970</a>
<a id='n2971' href='#n2971'>2971</a>
<a id='n2972' href='#n2972'>2972</a>
<a id='n2973' href='#n2973'>2973</a>
<a id='n2974' href='#n2974'>2974</a>
<a id='n2975' href='#n2975'>2975</a>
<a id='n2976' href='#n2976'>2976</a>
<a id='n2977' href='#n2977'>2977</a>
<a id='n2978' href='#n2978'>2978</a>
<a id='n2979' href='#n2979'>2979</a>
<a id='n2980' href='#n2980'>2980</a>
<a id='n2981' href='#n2981'>2981</a>
<a id='n2982' href='#n2982'>2982</a>
<a id='n2983' href='#n2983'>2983</a>
<a id='n2984' href='#n2984'>2984</a>
<a id='n2985' href='#n2985'>2985</a>
<a id='n2986' href='#n2986'>2986</a>
<a id='n2987' href='#n2987'>2987</a>
<a id='n2988' href='#n2988'>2988</a>
<a id='n2989' href='#n2989'>2989</a>
<a id='n2990' href='#n2990'>2990</a>
<a id='n2991' href='#n2991'>2991</a>
<a id='n2992' href='#n2992'>2992</a>
<a id='n2993' href='#n2993'>2993</a>
<a id='n2994' href='#n2994'>2994</a>
<a id='n2995' href='#n2995'>2995</a>
<a id='n2996' href='#n2996'>2996</a>
<a id='n2997' href='#n2997'>2997</a>
<a id='n2998' href='#n2998'>2998</a>
<a id='n2999' href='#n2999'>2999</a>
<a id='n3000' href='#n3000'>3000</a>
<a id='n3001' href='#n3001'>3001</a>
<a id='n3002' href='#n3002'>3002</a>
<a id='n3003' href='#n3003'>3003</a>
<a id='n3004' href='#n3004'>3004</a>
<a id='n3005' href='#n3005'>3005</a>
<a id='n3006' href='#n3006'>3006</a>
<a id='n3007' href='#n3007'>3007</a>
<a id='n3008' href='#n3008'>3008</a>
<a id='n3009' href='#n3009'>3009</a>
<a id='n3010' href='#n3010'>3010</a>
<a id='n3011' href='#n3011'>3011</a>
<a id='n3012' href='#n3012'>3012</a>
<a id='n3013' href='#n3013'>3013</a>
<a id='n3014' href='#n3014'>3014</a>
<a id='n3015' href='#n3015'>3015</a>
<a id='n3016' href='#n3016'>3016</a>
<a id='n3017' href='#n3017'>3017</a>
<a id='n3018' href='#n3018'>3018</a>
<a id='n3019' href='#n3019'>3019</a>
<a id='n3020' href='#n3020'>3020</a>
<a id='n3021' href='#n3021'>3021</a>
<a id='n3022' href='#n3022'>3022</a>
<a id='n3023' href='#n3023'>3023</a>
<a id='n3024' href='#n3024'>3024</a>
<a id='n3025' href='#n3025'>3025</a>
<a id='n3026' href='#n3026'>3026</a>
<a id='n3027' href='#n3027'>3027</a>
<a id='n3028' href='#n3028'>3028</a>
<a id='n3029' href='#n3029'>3029</a>
<a id='n3030' href='#n3030'>3030</a>
<a id='n3031' href='#n3031'>3031</a>
<a id='n3032' href='#n3032'>3032</a>
<a id='n3033' href='#n3033'>3033</a>
<a id='n3034' href='#n3034'>3034</a>
<a id='n3035' href='#n3035'>3035</a>
<a id='n3036' href='#n3036'>3036</a>
<a id='n3037' href='#n3037'>3037</a>
<a id='n3038' href='#n3038'>3038</a>
<a id='n3039' href='#n3039'>3039</a>
<a id='n3040' href='#n3040'>3040</a>
<a id='n3041' href='#n3041'>3041</a>
<a id='n3042' href='#n3042'>3042</a>
<a id='n3043' href='#n3043'>3043</a>
<a id='n3044' href='#n3044'>3044</a>
<a id='n3045' href='#n3045'>3045</a>
<a id='n3046' href='#n3046'>3046</a>
<a id='n3047' href='#n3047'>3047</a>
<a id='n3048' href='#n3048'>3048</a>
<a id='n3049' href='#n3049'>3049</a>
<a id='n3050' href='#n3050'>3050</a>
<a id='n3051' href='#n3051'>3051</a>
<a id='n3052' href='#n3052'>3052</a>
<a id='n3053' href='#n3053'>3053</a>
<a id='n3054' href='#n3054'>3054</a>
<a id='n3055' href='#n3055'>3055</a>
<a id='n3056' href='#n3056'>3056</a>
<a id='n3057' href='#n3057'>3057</a>
<a id='n3058' href='#n3058'>3058</a>
<a id='n3059' href='#n3059'>3059</a>
<a id='n3060' href='#n3060'>3060</a>
<a id='n3061' href='#n3061'>3061</a>
<a id='n3062' href='#n3062'>3062</a>
<a id='n3063' href='#n3063'>3063</a>
<a id='n3064' href='#n3064'>3064</a>
<a id='n3065' href='#n3065'>3065</a>
<a id='n3066' href='#n3066'>3066</a>
<a id='n3067' href='#n3067'>3067</a>
<a id='n3068' href='#n3068'>3068</a>
<a id='n3069' href='#n3069'>3069</a>
<a id='n3070' href='#n3070'>3070</a>
<a id='n3071' href='#n3071'>3071</a>
<a id='n3072' href='#n3072'>3072</a>
<a id='n3073' href='#n3073'>3073</a>
<a id='n3074' href='#n3074'>3074</a>
<a id='n3075' href='#n3075'>3075</a>
<a id='n3076' href='#n3076'>3076</a>
<a id='n3077' href='#n3077'>3077</a>
<a id='n3078' href='#n3078'>3078</a>
<a id='n3079' href='#n3079'>3079</a>
<a id='n3080' href='#n3080'>3080</a>
<a id='n3081' href='#n3081'>3081</a>
<a id='n3082' href='#n3082'>3082</a>
<a id='n3083' href='#n3083'>3083</a>
<a id='n3084' href='#n3084'>3084</a>
<a id='n3085' href='#n3085'>3085</a>
<a id='n3086' href='#n3086'>3086</a>
<a id='n3087' href='#n3087'>3087</a>
<a id='n3088' href='#n3088'>3088</a>
<a id='n3089' href='#n3089'>3089</a>
<a id='n3090' href='#n3090'>3090</a>
<a id='n3091' href='#n3091'>3091</a>
<a id='n3092' href='#n3092'>3092</a>
<a id='n3093' href='#n3093'>3093</a>
<a id='n3094' href='#n3094'>3094</a>
<a id='n3095' href='#n3095'>3095</a>
<a id='n3096' href='#n3096'>3096</a>
<a id='n3097' href='#n3097'>3097</a>
<a id='n3098' href='#n3098'>3098</a>
<a id='n3099' href='#n3099'>3099</a>
<a id='n3100' href='#n3100'>3100</a>
<a id='n3101' href='#n3101'>3101</a>
<a id='n3102' href='#n3102'>3102</a>
<a id='n3103' href='#n3103'>3103</a>
<a id='n3104' href='#n3104'>3104</a>
<a id='n3105' href='#n3105'>3105</a>
<a id='n3106' href='#n3106'>3106</a>
<a id='n3107' href='#n3107'>3107</a>
<a id='n3108' href='#n3108'>3108</a>
<a id='n3109' href='#n3109'>3109</a>
<a id='n3110' href='#n3110'>3110</a>
<a id='n3111' href='#n3111'>3111</a>
<a id='n3112' href='#n3112'>3112</a>
<a id='n3113' href='#n3113'>3113</a>
<a id='n3114' href='#n3114'>3114</a>
<a id='n3115' href='#n3115'>3115</a>
<a id='n3116' href='#n3116'>3116</a>
<a id='n3117' href='#n3117'>3117</a>
<a id='n3118' href='#n3118'>3118</a>
<a id='n3119' href='#n3119'>3119</a>
<a id='n3120' href='#n3120'>3120</a>
<a id='n3121' href='#n3121'>3121</a>
<a id='n3122' href='#n3122'>3122</a>
<a id='n3123' href='#n3123'>3123</a>
<a id='n3124' href='#n3124'>3124</a>
<a id='n3125' href='#n3125'>3125</a>
<a id='n3126' href='#n3126'>3126</a>
<a id='n3127' href='#n3127'>3127</a>
<a id='n3128' href='#n3128'>3128</a>
<a id='n3129' href='#n3129'>3129</a>
<a id='n3130' href='#n3130'>3130</a>
<a id='n3131' href='#n3131'>3131</a>
<a id='n3132' href='#n3132'>3132</a>
<a id='n3133' href='#n3133'>3133</a>
<a id='n3134' href='#n3134'>3134</a>
<a id='n3135' href='#n3135'>3135</a>
<a id='n3136' href='#n3136'>3136</a>
<a id='n3137' href='#n3137'>3137</a>
<a id='n3138' href='#n3138'>3138</a>
<a id='n3139' href='#n3139'>3139</a>
<a id='n3140' href='#n3140'>3140</a>
<a id='n3141' href='#n3141'>3141</a>
<a id='n3142' href='#n3142'>3142</a>
<a id='n3143' href='#n3143'>3143</a>
<a id='n3144' href='#n3144'>3144</a>
<a id='n3145' href='#n3145'>3145</a>
<a id='n3146' href='#n3146'>3146</a>
<a id='n3147' href='#n3147'>3147</a>
<a id='n3148' href='#n3148'>3148</a>
<a id='n3149' href='#n3149'>3149</a>
<a id='n3150' href='#n3150'>3150</a>
<a id='n3151' href='#n3151'>3151</a>
<a id='n3152' href='#n3152'>3152</a>
<a id='n3153' href='#n3153'>3153</a>
<a id='n3154' href='#n3154'>3154</a>
<a id='n3155' href='#n3155'>3155</a>
<a id='n3156' href='#n3156'>3156</a>
<a id='n3157' href='#n3157'>3157</a>
<a id='n3158' href='#n3158'>3158</a>
<a id='n3159' href='#n3159'>3159</a>
<a id='n3160' href='#n3160'>3160</a>
<a id='n3161' href='#n3161'>3161</a>
<a id='n3162' href='#n3162'>3162</a>
<a id='n3163' href='#n3163'>3163</a>
<a id='n3164' href='#n3164'>3164</a>
<a id='n3165' href='#n3165'>3165</a>
<a id='n3166' href='#n3166'>3166</a>
<a id='n3167' href='#n3167'>3167</a>
<a id='n3168' href='#n3168'>3168</a>
<a id='n3169' href='#n3169'>3169</a>
<a id='n3170' href='#n3170'>3170</a>
<a id='n3171' href='#n3171'>3171</a>
<a id='n3172' href='#n3172'>3172</a>
<a id='n3173' href='#n3173'>3173</a>
<a id='n3174' href='#n3174'>3174</a>
<a id='n3175' href='#n3175'>3175</a>
<a id='n3176' href='#n3176'>3176</a>
<a id='n3177' href='#n3177'>3177</a>
<a id='n3178' href='#n3178'>3178</a>
<a id='n3179' href='#n3179'>3179</a>
<a id='n3180' href='#n3180'>3180</a>
<a id='n3181' href='#n3181'>3181</a>
<a id='n3182' href='#n3182'>3182</a>
<a id='n3183' href='#n3183'>3183</a>
<a id='n3184' href='#n3184'>3184</a>
<a id='n3185' href='#n3185'>3185</a>
<a id='n3186' href='#n3186'>3186</a>
<a id='n3187' href='#n3187'>3187</a>
<a id='n3188' href='#n3188'>3188</a>
<a id='n3189' href='#n3189'>3189</a>
<a id='n3190' href='#n3190'>3190</a>
<a id='n3191' href='#n3191'>3191</a>
<a id='n3192' href='#n3192'>3192</a>
<a id='n3193' href='#n3193'>3193</a>
<a id='n3194' href='#n3194'>3194</a>
<a id='n3195' href='#n3195'>3195</a>
<a id='n3196' href='#n3196'>3196</a>
<a id='n3197' href='#n3197'>3197</a>
<a id='n3198' href='#n3198'>3198</a>
<a id='n3199' href='#n3199'>3199</a>
<a id='n3200' href='#n3200'>3200</a>
<a id='n3201' href='#n3201'>3201</a>
<a id='n3202' href='#n3202'>3202</a>
<a id='n3203' href='#n3203'>3203</a>
<a id='n3204' href='#n3204'>3204</a>
<a id='n3205' href='#n3205'>3205</a>
<a id='n3206' href='#n3206'>3206</a>
<a id='n3207' href='#n3207'>3207</a>
<a id='n3208' href='#n3208'>3208</a>
<a id='n3209' href='#n3209'>3209</a>
<a id='n3210' href='#n3210'>3210</a>
<a id='n3211' href='#n3211'>3211</a>
<a id='n3212' href='#n3212'>3212</a>
<a id='n3213' href='#n3213'>3213</a>
<a id='n3214' href='#n3214'>3214</a>
<a id='n3215' href='#n3215'>3215</a>
<a id='n3216' href='#n3216'>3216</a>
<a id='n3217' href='#n3217'>3217</a>
<a id='n3218' href='#n3218'>3218</a>
<a id='n3219' href='#n3219'>3219</a>
<a id='n3220' href='#n3220'>3220</a>
<a id='n3221' href='#n3221'>3221</a>
<a id='n3222' href='#n3222'>3222</a>
<a id='n3223' href='#n3223'>3223</a>
<a id='n3224' href='#n3224'>3224</a>
<a id='n3225' href='#n3225'>3225</a>
<a id='n3226' href='#n3226'>3226</a>
<a id='n3227' href='#n3227'>3227</a>
<a id='n3228' href='#n3228'>3228</a>
<a id='n3229' href='#n3229'>3229</a>
<a id='n3230' href='#n3230'>3230</a>
<a id='n3231' href='#n3231'>3231</a>
<a id='n3232' href='#n3232'>3232</a>
<a id='n3233' href='#n3233'>3233</a>
<a id='n3234' href='#n3234'>3234</a>
<a id='n3235' href='#n3235'>3235</a>
<a id='n3236' href='#n3236'>3236</a>
<a id='n3237' href='#n3237'>3237</a>
<a id='n3238' href='#n3238'>3238</a>
<a id='n3239' href='#n3239'>3239</a>
<a id='n3240' href='#n3240'>3240</a>
<a id='n3241' href='#n3241'>3241</a>
<a id='n3242' href='#n3242'>3242</a>
<a id='n3243' href='#n3243'>3243</a>
<a id='n3244' href='#n3244'>3244</a>
<a id='n3245' href='#n3245'>3245</a>
<a id='n3246' href='#n3246'>3246</a>
<a id='n3247' href='#n3247'>3247</a>
<a id='n3248' href='#n3248'>3248</a>
<a id='n3249' href='#n3249'>3249</a>
<a id='n3250' href='#n3250'>3250</a>
<a id='n3251' href='#n3251'>3251</a>
<a id='n3252' href='#n3252'>3252</a>
<a id='n3253' href='#n3253'>3253</a>
<a id='n3254' href='#n3254'>3254</a>
<a id='n3255' href='#n3255'>3255</a>
<a id='n3256' href='#n3256'>3256</a>
<a id='n3257' href='#n3257'>3257</a>
<a id='n3258' href='#n3258'>3258</a>
<a id='n3259' href='#n3259'>3259</a>
<a id='n3260' href='#n3260'>3260</a>
<a id='n3261' href='#n3261'>3261</a>
<a id='n3262' href='#n3262'>3262</a>
<a id='n3263' href='#n3263'>3263</a>
<a id='n3264' href='#n3264'>3264</a>
<a id='n3265' href='#n3265'>3265</a>
<a id='n3266' href='#n3266'>3266</a>
<a id='n3267' href='#n3267'>3267</a>
<a id='n3268' href='#n3268'>3268</a>
<a id='n3269' href='#n3269'>3269</a>
<a id='n3270' href='#n3270'>3270</a>
<a id='n3271' href='#n3271'>3271</a>
<a id='n3272' href='#n3272'>3272</a>
<a id='n3273' href='#n3273'>3273</a>
<a id='n3274' href='#n3274'>3274</a>
<a id='n3275' href='#n3275'>3275</a>
<a id='n3276' href='#n3276'>3276</a>
<a id='n3277' href='#n3277'>3277</a>
<a id='n3278' href='#n3278'>3278</a>
<a id='n3279' href='#n3279'>3279</a>
<a id='n3280' href='#n3280'>3280</a>
<a id='n3281' href='#n3281'>3281</a>
<a id='n3282' href='#n3282'>3282</a>
<a id='n3283' href='#n3283'>3283</a>
<a id='n3284' href='#n3284'>3284</a>
<a id='n3285' href='#n3285'>3285</a>
<a id='n3286' href='#n3286'>3286</a>
<a id='n3287' href='#n3287'>3287</a>
<a id='n3288' href='#n3288'>3288</a>
<a id='n3289' href='#n3289'>3289</a>
<a id='n3290' href='#n3290'>3290</a>
<a id='n3291' href='#n3291'>3291</a>
<a id='n3292' href='#n3292'>3292</a>
<a id='n3293' href='#n3293'>3293</a>
<a id='n3294' href='#n3294'>3294</a>
<a id='n3295' href='#n3295'>3295</a>
<a id='n3296' href='#n3296'>3296</a>
<a id='n3297' href='#n3297'>3297</a>
<a id='n3298' href='#n3298'>3298</a>
<a id='n3299' href='#n3299'>3299</a>
<a id='n3300' href='#n3300'>3300</a>
<a id='n3301' href='#n3301'>3301</a>
<a id='n3302' href='#n3302'>3302</a>
<a id='n3303' href='#n3303'>3303</a>
<a id='n3304' href='#n3304'>3304</a>
<a id='n3305' href='#n3305'>3305</a>
<a id='n3306' href='#n3306'>3306</a>
<a id='n3307' href='#n3307'>3307</a>
<a id='n3308' href='#n3308'>3308</a>
<a id='n3309' href='#n3309'>3309</a>
<a id='n3310' href='#n3310'>3310</a>
<a id='n3311' href='#n3311'>3311</a>
<a id='n3312' href='#n3312'>3312</a>
<a id='n3313' href='#n3313'>3313</a>
<a id='n3314' href='#n3314'>3314</a>
<a id='n3315' href='#n3315'>3315</a>
<a id='n3316' href='#n3316'>3316</a>
<a id='n3317' href='#n3317'>3317</a>
<a id='n3318' href='#n3318'>3318</a>
<a id='n3319' href='#n3319'>3319</a>
<a id='n3320' href='#n3320'>3320</a>
<a id='n3321' href='#n3321'>3321</a>
<a id='n3322' href='#n3322'>3322</a>
<a id='n3323' href='#n3323'>3323</a>
<a id='n3324' href='#n3324'>3324</a>
<a id='n3325' href='#n3325'>3325</a>
<a id='n3326' href='#n3326'>3326</a>
<a id='n3327' href='#n3327'>3327</a>
<a id='n3328' href='#n3328'>3328</a>
<a id='n3329' href='#n3329'>3329</a>
<a id='n3330' href='#n3330'>3330</a>
<a id='n3331' href='#n3331'>3331</a>
<a id='n3332' href='#n3332'>3332</a>
<a id='n3333' href='#n3333'>3333</a>
<a id='n3334' href='#n3334'>3334</a>
<a id='n3335' href='#n3335'>3335</a>
<a id='n3336' href='#n3336'>3336</a>
<a id='n3337' href='#n3337'>3337</a>
<a id='n3338' href='#n3338'>3338</a>
<a id='n3339' href='#n3339'>3339</a>
<a id='n3340' href='#n3340'>3340</a>
<a id='n3341' href='#n3341'>3341</a>
<a id='n3342' href='#n3342'>3342</a>
<a id='n3343' href='#n3343'>3343</a>
<a id='n3344' href='#n3344'>3344</a>
<a id='n3345' href='#n3345'>3345</a>
<a id='n3346' href='#n3346'>3346</a>
<a id='n3347' href='#n3347'>3347</a>
<a id='n3348' href='#n3348'>3348</a>
<a id='n3349' href='#n3349'>3349</a>
<a id='n3350' href='#n3350'>3350</a>
<a id='n3351' href='#n3351'>3351</a>
<a id='n3352' href='#n3352'>3352</a>
<a id='n3353' href='#n3353'>3353</a>
<a id='n3354' href='#n3354'>3354</a>
<a id='n3355' href='#n3355'>3355</a>
<a id='n3356' href='#n3356'>3356</a>
<a id='n3357' href='#n3357'>3357</a>
<a id='n3358' href='#n3358'>3358</a>
<a id='n3359' href='#n3359'>3359</a>
<a id='n3360' href='#n3360'>3360</a>
<a id='n3361' href='#n3361'>3361</a>
<a id='n3362' href='#n3362'>3362</a>
<a id='n3363' href='#n3363'>3363</a>
<a id='n3364' href='#n3364'>3364</a>
<a id='n3365' href='#n3365'>3365</a>
<a id='n3366' href='#n3366'>3366</a>
<a id='n3367' href='#n3367'>3367</a>
<a id='n3368' href='#n3368'>3368</a>
<a id='n3369' href='#n3369'>3369</a>
<a id='n3370' href='#n3370'>3370</a>
<a id='n3371' href='#n3371'>3371</a>
<a id='n3372' href='#n3372'>3372</a>
<a id='n3373' href='#n3373'>3373</a>
<a id='n3374' href='#n3374'>3374</a>
<a id='n3375' href='#n3375'>3375</a>
<a id='n3376' href='#n3376'>3376</a>
<a id='n3377' href='#n3377'>3377</a>
<a id='n3378' href='#n3378'>3378</a>
<a id='n3379' href='#n3379'>3379</a>
<a id='n3380' href='#n3380'>3380</a>
<a id='n3381' href='#n3381'>3381</a>
<a id='n3382' href='#n3382'>3382</a>
<a id='n3383' href='#n3383'>3383</a>
<a id='n3384' href='#n3384'>3384</a>
<a id='n3385' href='#n3385'>3385</a>
<a id='n3386' href='#n3386'>3386</a>
<a id='n3387' href='#n3387'>3387</a>
<a id='n3388' href='#n3388'>3388</a>
<a id='n3389' href='#n3389'>3389</a>
<a id='n3390' href='#n3390'>3390</a>
<a id='n3391' href='#n3391'>3391</a>
<a id='n3392' href='#n3392'>3392</a>
<a id='n3393' href='#n3393'>3393</a>
<a id='n3394' href='#n3394'>3394</a>
<a id='n3395' href='#n3395'>3395</a>
<a id='n3396' href='#n3396'>3396</a>
<a id='n3397' href='#n3397'>3397</a>
<a id='n3398' href='#n3398'>3398</a>
<a id='n3399' href='#n3399'>3399</a>
<a id='n3400' href='#n3400'>3400</a>
<a id='n3401' href='#n3401'>3401</a>
<a id='n3402' href='#n3402'>3402</a>
<a id='n3403' href='#n3403'>3403</a>
<a id='n3404' href='#n3404'>3404</a>
<a id='n3405' href='#n3405'>3405</a>
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<a id='n3408' href='#n3408'>3408</a>
<a id='n3409' href='#n3409'>3409</a>
<a id='n3410' href='#n3410'>3410</a>
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<a id='n3412' href='#n3412'>3412</a>
<a id='n3413' href='#n3413'>3413</a>
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<a id='n3421' href='#n3421'>3421</a>
<a id='n3422' href='#n3422'>3422</a>
<a id='n3423' href='#n3423'>3423</a>
<a id='n3424' href='#n3424'>3424</a>
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<a id='n3431' href='#n3431'>3431</a>
<a id='n3432' href='#n3432'>3432</a>
<a id='n3433' href='#n3433'>3433</a>
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<a id='n3459' href='#n3459'>3459</a>
<a id='n3460' href='#n3460'>3460</a>
<a id='n3461' href='#n3461'>3461</a>
<a id='n3462' href='#n3462'>3462</a>
<a id='n3463' href='#n3463'>3463</a>
<a id='n3464' href='#n3464'>3464</a>
<a id='n3465' href='#n3465'>3465</a>
<a id='n3466' href='#n3466'>3466</a>
<a id='n3467' href='#n3467'>3467</a>
<a id='n3468' href='#n3468'>3468</a>
<a id='n3469' href='#n3469'>3469</a>
<a id='n3470' href='#n3470'>3470</a>
<a id='n3471' href='#n3471'>3471</a>
<a id='n3472' href='#n3472'>3472</a>
<a id='n3473' href='#n3473'>3473</a>
<a id='n3474' href='#n3474'>3474</a>
<a id='n3475' href='#n3475'>3475</a>
<a id='n3476' href='#n3476'>3476</a>
<a id='n3477' href='#n3477'>3477</a>
<a id='n3478' href='#n3478'>3478</a>
<a id='n3479' href='#n3479'>3479</a>
<a id='n3480' href='#n3480'>3480</a>
<a id='n3481' href='#n3481'>3481</a>
<a id='n3482' href='#n3482'>3482</a>
<a id='n3483' href='#n3483'>3483</a>
<a id='n3484' href='#n3484'>3484</a>
<a id='n3485' href='#n3485'>3485</a>
<a id='n3486' href='#n3486'>3486</a>
<a id='n3487' href='#n3487'>3487</a>
<a id='n3488' href='#n3488'>3488</a>
<a id='n3489' href='#n3489'>3489</a>
<a id='n3490' href='#n3490'>3490</a>
<a id='n3491' href='#n3491'>3491</a>
<a id='n3492' href='#n3492'>3492</a>
<a id='n3493' href='#n3493'>3493</a>
<a id='n3494' href='#n3494'>3494</a>
<a id='n3495' href='#n3495'>3495</a>
<a id='n3496' href='#n3496'>3496</a>
<a id='n3497' href='#n3497'>3497</a>
<a id='n3498' href='#n3498'>3498</a>
<a id='n3499' href='#n3499'>3499</a>
<a id='n3500' href='#n3500'>3500</a>
<a id='n3501' href='#n3501'>3501</a>
<a id='n3502' href='#n3502'>3502</a>
<a id='n3503' href='#n3503'>3503</a>
<a id='n3504' href='#n3504'>3504</a>
<a id='n3505' href='#n3505'>3505</a>
<a id='n3506' href='#n3506'>3506</a>
<a id='n3507' href='#n3507'>3507</a>
<a id='n3508' href='#n3508'>3508</a>
<a id='n3509' href='#n3509'>3509</a>
<a id='n3510' href='#n3510'>3510</a>
<a id='n3511' href='#n3511'>3511</a>
<a id='n3512' href='#n3512'>3512</a>
<a id='n3513' href='#n3513'>3513</a>
<a id='n3514' href='#n3514'>3514</a>
<a id='n3515' href='#n3515'>3515</a>
<a id='n3516' href='#n3516'>3516</a>
<a id='n3517' href='#n3517'>3517</a>
<a id='n3518' href='#n3518'>3518</a>
<a id='n3519' href='#n3519'>3519</a>
<a id='n3520' href='#n3520'>3520</a>
<a id='n3521' href='#n3521'>3521</a>
<a id='n3522' href='#n3522'>3522</a>
<a id='n3523' href='#n3523'>3523</a>
<a id='n3524' href='#n3524'>3524</a>
<a id='n3525' href='#n3525'>3525</a>
<a id='n3526' href='#n3526'>3526</a>
<a id='n3527' href='#n3527'>3527</a>
<a id='n3528' href='#n3528'>3528</a>
<a id='n3529' href='#n3529'>3529</a>
<a id='n3530' href='#n3530'>3530</a>
<a id='n3531' href='#n3531'>3531</a>
<a id='n3532' href='#n3532'>3532</a>
<a id='n3533' href='#n3533'>3533</a>
<a id='n3534' href='#n3534'>3534</a>
<a id='n3535' href='#n3535'>3535</a>
<a id='n3536' href='#n3536'>3536</a>
<a id='n3537' href='#n3537'>3537</a>
<a id='n3538' href='#n3538'>3538</a>
<a id='n3539' href='#n3539'>3539</a>
<a id='n3540' href='#n3540'>3540</a>
<a id='n3541' href='#n3541'>3541</a>
<a id='n3542' href='#n3542'>3542</a>
<a id='n3543' href='#n3543'>3543</a>
<a id='n3544' href='#n3544'>3544</a>
<a id='n3545' href='#n3545'>3545</a>
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<a id='n3547' href='#n3547'>3547</a>
<a id='n3548' href='#n3548'>3548</a>
<a id='n3549' href='#n3549'>3549</a>
<a id='n3550' href='#n3550'>3550</a>
<a id='n3551' href='#n3551'>3551</a>
<a id='n3552' href='#n3552'>3552</a>
<a id='n3553' href='#n3553'>3553</a>
<a id='n3554' href='#n3554'>3554</a>
<a id='n3555' href='#n3555'>3555</a>
<a id='n3556' href='#n3556'>3556</a>
<a id='n3557' href='#n3557'>3557</a>
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<a id='n3560' href='#n3560'>3560</a>
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<a id='n3562' href='#n3562'>3562</a>
<a id='n3563' href='#n3563'>3563</a>
<a id='n3564' href='#n3564'>3564</a>
<a id='n3565' href='#n3565'>3565</a>
<a id='n3566' href='#n3566'>3566</a>
<a id='n3567' href='#n3567'>3567</a>
<a id='n3568' href='#n3568'>3568</a>
<a id='n3569' href='#n3569'>3569</a>
<a id='n3570' href='#n3570'>3570</a>
<a id='n3571' href='#n3571'>3571</a>
<a id='n3572' href='#n3572'>3572</a>
<a id='n3573' href='#n3573'>3573</a>
<a id='n3574' href='#n3574'>3574</a>
<a id='n3575' href='#n3575'>3575</a>
<a id='n3576' href='#n3576'>3576</a>
<a id='n3577' href='#n3577'>3577</a>
<a id='n3578' href='#n3578'>3578</a>
<a id='n3579' href='#n3579'>3579</a>
<a id='n3580' href='#n3580'>3580</a>
<a id='n3581' href='#n3581'>3581</a>
<a id='n3582' href='#n3582'>3582</a>
<a id='n3583' href='#n3583'>3583</a>
<a id='n3584' href='#n3584'>3584</a>
<a id='n3585' href='#n3585'>3585</a>
<a id='n3586' href='#n3586'>3586</a>
<a id='n3587' href='#n3587'>3587</a>
<a id='n3588' href='#n3588'>3588</a>
<a id='n3589' href='#n3589'>3589</a>
<a id='n3590' href='#n3590'>3590</a>
<a id='n3591' href='#n3591'>3591</a>
<a id='n3592' href='#n3592'>3592</a>
<a id='n3593' href='#n3593'>3593</a>
<a id='n3594' href='#n3594'>3594</a>
<a id='n3595' href='#n3595'>3595</a>
<a id='n3596' href='#n3596'>3596</a>
<a id='n3597' href='#n3597'>3597</a>
<a id='n3598' href='#n3598'>3598</a>
<a id='n3599' href='#n3599'>3599</a>
<a id='n3600' href='#n3600'>3600</a>
<a id='n3601' href='#n3601'>3601</a>
<a id='n3602' href='#n3602'>3602</a>
<a id='n3603' href='#n3603'>3603</a>
<a id='n3604' href='#n3604'>3604</a>
<a id='n3605' href='#n3605'>3605</a>
<a id='n3606' href='#n3606'>3606</a>
<a id='n3607' href='#n3607'>3607</a>
<a id='n3608' href='#n3608'>3608</a>
<a id='n3609' href='#n3609'>3609</a>
<a id='n3610' href='#n3610'>3610</a>
<a id='n3611' href='#n3611'>3611</a>
<a id='n3612' href='#n3612'>3612</a>
<a id='n3613' href='#n3613'>3613</a>
<a id='n3614' href='#n3614'>3614</a>
<a id='n3615' href='#n3615'>3615</a>
<a id='n3616' href='#n3616'>3616</a>
<a id='n3617' href='#n3617'>3617</a>
<a id='n3618' href='#n3618'>3618</a>
<a id='n3619' href='#n3619'>3619</a>
<a id='n3620' href='#n3620'>3620</a>
<a id='n3621' href='#n3621'>3621</a>
<a id='n3622' href='#n3622'>3622</a>
<a id='n3623' href='#n3623'>3623</a>
<a id='n3624' href='#n3624'>3624</a>
<a id='n3625' href='#n3625'>3625</a>
<a id='n3626' href='#n3626'>3626</a>
<a id='n3627' href='#n3627'>3627</a>
<a id='n3628' href='#n3628'>3628</a>
<a id='n3629' href='#n3629'>3629</a>
<a id='n3630' href='#n3630'>3630</a>
<a id='n3631' href='#n3631'>3631</a>
<a id='n3632' href='#n3632'>3632</a>
<a id='n3633' href='#n3633'>3633</a>
<a id='n3634' href='#n3634'>3634</a>
<a id='n3635' href='#n3635'>3635</a>
<a id='n3636' href='#n3636'>3636</a>
<a id='n3637' href='#n3637'>3637</a>
<a id='n3638' href='#n3638'>3638</a>
<a id='n3639' href='#n3639'>3639</a>
<a id='n3640' href='#n3640'>3640</a>
<a id='n3641' href='#n3641'>3641</a>
<a id='n3642' href='#n3642'>3642</a>
<a id='n3643' href='#n3643'>3643</a>
<a id='n3644' href='#n3644'>3644</a>
<a id='n3645' href='#n3645'>3645</a>
<a id='n3646' href='#n3646'>3646</a>
<a id='n3647' href='#n3647'>3647</a>
<a id='n3648' href='#n3648'>3648</a>
<a id='n3649' href='#n3649'>3649</a>
<a id='n3650' href='#n3650'>3650</a>
<a id='n3651' href='#n3651'>3651</a>
<a id='n3652' href='#n3652'>3652</a>
<a id='n3653' href='#n3653'>3653</a>
<a id='n3654' href='#n3654'>3654</a>
<a id='n3655' href='#n3655'>3655</a>
<a id='n3656' href='#n3656'>3656</a>
<a id='n3657' href='#n3657'>3657</a>
<a id='n3658' href='#n3658'>3658</a>
<a id='n3659' href='#n3659'>3659</a>
<a id='n3660' href='#n3660'>3660</a>
<a id='n3661' href='#n3661'>3661</a>
<a id='n3662' href='#n3662'>3662</a>
<a id='n3663' href='#n3663'>3663</a>
<a id='n3664' href='#n3664'>3664</a>
<a id='n3665' href='#n3665'>3665</a>
<a id='n3666' href='#n3666'>3666</a>
<a id='n3667' href='#n3667'>3667</a>
<a id='n3668' href='#n3668'>3668</a>
<a id='n3669' href='#n3669'>3669</a>
<a id='n3670' href='#n3670'>3670</a>
<a id='n3671' href='#n3671'>3671</a>
<a id='n3672' href='#n3672'>3672</a>
<a id='n3673' href='#n3673'>3673</a>
<a id='n3674' href='#n3674'>3674</a>
<a id='n3675' href='#n3675'>3675</a>
<a id='n3676' href='#n3676'>3676</a>
<a id='n3677' href='#n3677'>3677</a>
<a id='n3678' href='#n3678'>3678</a>
<a id='n3679' href='#n3679'>3679</a>
<a id='n3680' href='#n3680'>3680</a>
<a id='n3681' href='#n3681'>3681</a>
<a id='n3682' href='#n3682'>3682</a>
<a id='n3683' href='#n3683'>3683</a>
<a id='n3684' href='#n3684'>3684</a>
<a id='n3685' href='#n3685'>3685</a>
<a id='n3686' href='#n3686'>3686</a>
<a id='n3687' href='#n3687'>3687</a>
<a id='n3688' href='#n3688'>3688</a>
<a id='n3689' href='#n3689'>3689</a>
<a id='n3690' href='#n3690'>3690</a>
<a id='n3691' href='#n3691'>3691</a>
<a id='n3692' href='#n3692'>3692</a>
<a id='n3693' href='#n3693'>3693</a>
<a id='n3694' href='#n3694'>3694</a>
<a id='n3695' href='#n3695'>3695</a>
<a id='n3696' href='#n3696'>3696</a>
<a id='n3697' href='#n3697'>3697</a>
<a id='n3698' href='#n3698'>3698</a>
<a id='n3699' href='#n3699'>3699</a>
<a id='n3700' href='#n3700'>3700</a>
<a id='n3701' href='#n3701'>3701</a>
<a id='n3702' href='#n3702'>3702</a>
<a id='n3703' href='#n3703'>3703</a>
<a id='n3704' href='#n3704'>3704</a>
<a id='n3705' href='#n3705'>3705</a>
<a id='n3706' href='#n3706'>3706</a>
<a id='n3707' href='#n3707'>3707</a>
<a id='n3708' href='#n3708'>3708</a>
<a id='n3709' href='#n3709'>3709</a>
<a id='n3710' href='#n3710'>3710</a>
<a id='n3711' href='#n3711'>3711</a>
<a id='n3712' href='#n3712'>3712</a>
<a id='n3713' href='#n3713'>3713</a>
<a id='n3714' href='#n3714'>3714</a>
<a id='n3715' href='#n3715'>3715</a>
<a id='n3716' href='#n3716'>3716</a>
<a id='n3717' href='#n3717'>3717</a>
<a id='n3718' href='#n3718'>3718</a>
<a id='n3719' href='#n3719'>3719</a>
<a id='n3720' href='#n3720'>3720</a>
<a id='n3721' href='#n3721'>3721</a>
<a id='n3722' href='#n3722'>3722</a>
<a id='n3723' href='#n3723'>3723</a>
<a id='n3724' href='#n3724'>3724</a>
<a id='n3725' href='#n3725'>3725</a>
<a id='n3726' href='#n3726'>3726</a>
<a id='n3727' href='#n3727'>3727</a>
<a id='n3728' href='#n3728'>3728</a>
<a id='n3729' href='#n3729'>3729</a>
<a id='n3730' href='#n3730'>3730</a>
<a id='n3731' href='#n3731'>3731</a>
<a id='n3732' href='#n3732'>3732</a>
<a id='n3733' href='#n3733'>3733</a>
<a id='n3734' href='#n3734'>3734</a>
<a id='n3735' href='#n3735'>3735</a>
<a id='n3736' href='#n3736'>3736</a>
<a id='n3737' href='#n3737'>3737</a>
<a id='n3738' href='#n3738'>3738</a>
<a id='n3739' href='#n3739'>3739</a>
<a id='n3740' href='#n3740'>3740</a>
<a id='n3741' href='#n3741'>3741</a>
<a id='n3742' href='#n3742'>3742</a>
<a id='n3743' href='#n3743'>3743</a>
<a id='n3744' href='#n3744'>3744</a>
<a id='n3745' href='#n3745'>3745</a>
<a id='n3746' href='#n3746'>3746</a>
<a id='n3747' href='#n3747'>3747</a>
<a id='n3748' href='#n3748'>3748</a>
<a id='n3749' href='#n3749'>3749</a>
<a id='n3750' href='#n3750'>3750</a>
<a id='n3751' href='#n3751'>3751</a>
<a id='n3752' href='#n3752'>3752</a>
<a id='n3753' href='#n3753'>3753</a>
<a id='n3754' href='#n3754'>3754</a>
<a id='n3755' href='#n3755'>3755</a>
<a id='n3756' href='#n3756'>3756</a>
<a id='n3757' href='#n3757'>3757</a>
<a id='n3758' href='#n3758'>3758</a>
<a id='n3759' href='#n3759'>3759</a>
<a id='n3760' href='#n3760'>3760</a>
<a id='n3761' href='#n3761'>3761</a>
<a id='n3762' href='#n3762'>3762</a>
<a id='n3763' href='#n3763'>3763</a>
<a id='n3764' href='#n3764'>3764</a>
<a id='n3765' href='#n3765'>3765</a>
<a id='n3766' href='#n3766'>3766</a>
<a id='n3767' href='#n3767'>3767</a>
<a id='n3768' href='#n3768'>3768</a>
<a id='n3769' href='#n3769'>3769</a>
<a id='n3770' href='#n3770'>3770</a>
<a id='n3771' href='#n3771'>3771</a>
<a id='n3772' href='#n3772'>3772</a>
<a id='n3773' href='#n3773'>3773</a>
<a id='n3774' href='#n3774'>3774</a>
<a id='n3775' href='#n3775'>3775</a>
<a id='n3776' href='#n3776'>3776</a>
<a id='n3777' href='#n3777'>3777</a>
<a id='n3778' href='#n3778'>3778</a>
<a id='n3779' href='#n3779'>3779</a>
<a id='n3780' href='#n3780'>3780</a>
<a id='n3781' href='#n3781'>3781</a>
<a id='n3782' href='#n3782'>3782</a>
<a id='n3783' href='#n3783'>3783</a>
<a id='n3784' href='#n3784'>3784</a>
<a id='n3785' href='#n3785'>3785</a>
<a id='n3786' href='#n3786'>3786</a>
<a id='n3787' href='#n3787'>3787</a>
<a id='n3788' href='#n3788'>3788</a>
<a id='n3789' href='#n3789'>3789</a>
<a id='n3790' href='#n3790'>3790</a>
<a id='n3791' href='#n3791'>3791</a>
<a id='n3792' href='#n3792'>3792</a>
<a id='n3793' href='#n3793'>3793</a>
<a id='n3794' href='#n3794'>3794</a>
<a id='n3795' href='#n3795'>3795</a>
<a id='n3796' href='#n3796'>3796</a>
<a id='n3797' href='#n3797'>3797</a>
<a id='n3798' href='#n3798'>3798</a>
<a id='n3799' href='#n3799'>3799</a>
<a id='n3800' href='#n3800'>3800</a>
<a id='n3801' href='#n3801'>3801</a>
<a id='n3802' href='#n3802'>3802</a>
<a id='n3803' href='#n3803'>3803</a>
<a id='n3804' href='#n3804'>3804</a>
<a id='n3805' href='#n3805'>3805</a>
<a id='n3806' href='#n3806'>3806</a>
<a id='n3807' href='#n3807'>3807</a>
<a id='n3808' href='#n3808'>3808</a>
<a id='n3809' href='#n3809'>3809</a>
<a id='n3810' href='#n3810'>3810</a>
<a id='n3811' href='#n3811'>3811</a>
<a id='n3812' href='#n3812'>3812</a>
<a id='n3813' href='#n3813'>3813</a>
<a id='n3814' href='#n3814'>3814</a>
<a id='n3815' href='#n3815'>3815</a>
<a id='n3816' href='#n3816'>3816</a>
<a id='n3817' href='#n3817'>3817</a>
<a id='n3818' href='#n3818'>3818</a>
<a id='n3819' href='#n3819'>3819</a>
<a id='n3820' href='#n3820'>3820</a>
<a id='n3821' href='#n3821'>3821</a>
<a id='n3822' href='#n3822'>3822</a>
<a id='n3823' href='#n3823'>3823</a>
<a id='n3824' href='#n3824'>3824</a>
<a id='n3825' href='#n3825'>3825</a>
<a id='n3826' href='#n3826'>3826</a>
<a id='n3827' href='#n3827'>3827</a>
<a id='n3828' href='#n3828'>3828</a>
<a id='n3829' href='#n3829'>3829</a>
<a id='n3830' href='#n3830'>3830</a>
<a id='n3831' href='#n3831'>3831</a>
<a id='n3832' href='#n3832'>3832</a>
<a id='n3833' href='#n3833'>3833</a>
<a id='n3834' href='#n3834'>3834</a>
<a id='n3835' href='#n3835'>3835</a>
<a id='n3836' href='#n3836'>3836</a>
<a id='n3837' href='#n3837'>3837</a>
<a id='n3838' href='#n3838'>3838</a>
<a id='n3839' href='#n3839'>3839</a>
<a id='n3840' href='#n3840'>3840</a>
<a id='n3841' href='#n3841'>3841</a>
<a id='n3842' href='#n3842'>3842</a>
<a id='n3843' href='#n3843'>3843</a>
<a id='n3844' href='#n3844'>3844</a>
<a id='n3845' href='#n3845'>3845</a>
<a id='n3846' href='#n3846'>3846</a>
<a id='n3847' href='#n3847'>3847</a>
<a id='n3848' href='#n3848'>3848</a>
<a id='n3849' href='#n3849'>3849</a>
<a id='n3850' href='#n3850'>3850</a>
<a id='n3851' href='#n3851'>3851</a>
<a id='n3852' href='#n3852'>3852</a>
<a id='n3853' href='#n3853'>3853</a>
<a id='n3854' href='#n3854'>3854</a>
<a id='n3855' href='#n3855'>3855</a>
<a id='n3856' href='#n3856'>3856</a>
<a id='n3857' href='#n3857'>3857</a>
<a id='n3858' href='#n3858'>3858</a>
<a id='n3859' href='#n3859'>3859</a>
<a id='n3860' href='#n3860'>3860</a>
<a id='n3861' href='#n3861'>3861</a>
<a id='n3862' href='#n3862'>3862</a>
<a id='n3863' href='#n3863'>3863</a>
<a id='n3864' href='#n3864'>3864</a>
<a id='n3865' href='#n3865'>3865</a>
<a id='n3866' href='#n3866'>3866</a>
<a id='n3867' href='#n3867'>3867</a>
<a id='n3868' href='#n3868'>3868</a>
<a id='n3869' href='#n3869'>3869</a>
<a id='n3870' href='#n3870'>3870</a>
<a id='n3871' href='#n3871'>3871</a>
<a id='n3872' href='#n3872'>3872</a>
<a id='n3873' href='#n3873'>3873</a>
<a id='n3874' href='#n3874'>3874</a>
<a id='n3875' href='#n3875'>3875</a>
<a id='n3876' href='#n3876'>3876</a>
<a id='n3877' href='#n3877'>3877</a>
<a id='n3878' href='#n3878'>3878</a>
<a id='n3879' href='#n3879'>3879</a>
<a id='n3880' href='#n3880'>3880</a>
<a id='n3881' href='#n3881'>3881</a>
<a id='n3882' href='#n3882'>3882</a>
<a id='n3883' href='#n3883'>3883</a>
<a id='n3884' href='#n3884'>3884</a>
<a id='n3885' href='#n3885'>3885</a>
<a id='n3886' href='#n3886'>3886</a>
<a id='n3887' href='#n3887'>3887</a>
<a id='n3888' href='#n3888'>3888</a>
<a id='n3889' href='#n3889'>3889</a>
<a id='n3890' href='#n3890'>3890</a>
<a id='n3891' href='#n3891'>3891</a>
<a id='n3892' href='#n3892'>3892</a>
<a id='n3893' href='#n3893'>3893</a>
<a id='n3894' href='#n3894'>3894</a>
<a id='n3895' href='#n3895'>3895</a>
<a id='n3896' href='#n3896'>3896</a>
<a id='n3897' href='#n3897'>3897</a>
<a id='n3898' href='#n3898'>3898</a>
<a id='n3899' href='#n3899'>3899</a>
<a id='n3900' href='#n3900'>3900</a>
<a id='n3901' href='#n3901'>3901</a>
<a id='n3902' href='#n3902'>3902</a>
<a id='n3903' href='#n3903'>3903</a>
<a id='n3904' href='#n3904'>3904</a>
<a id='n3905' href='#n3905'>3905</a>
<a id='n3906' href='#n3906'>3906</a>
<a id='n3907' href='#n3907'>3907</a>
<a id='n3908' href='#n3908'>3908</a>
<a id='n3909' href='#n3909'>3909</a>
<a id='n3910' href='#n3910'>3910</a>
<a id='n3911' href='#n3911'>3911</a>
<a id='n3912' href='#n3912'>3912</a>
<a id='n3913' href='#n3913'>3913</a>
<a id='n3914' href='#n3914'>3914</a>
<a id='n3915' href='#n3915'>3915</a>
<a id='n3916' href='#n3916'>3916</a>
<a id='n3917' href='#n3917'>3917</a>
<a id='n3918' href='#n3918'>3918</a>
<a id='n3919' href='#n3919'>3919</a>
<a id='n3920' href='#n3920'>3920</a>
<a id='n3921' href='#n3921'>3921</a>
<a id='n3922' href='#n3922'>3922</a>
<a id='n3923' href='#n3923'>3923</a>
<a id='n3924' href='#n3924'>3924</a>
<a id='n3925' href='#n3925'>3925</a>
<a id='n3926' href='#n3926'>3926</a>
<a id='n3927' href='#n3927'>3927</a>
<a id='n3928' href='#n3928'>3928</a>
<a id='n3929' href='#n3929'>3929</a>
<a id='n3930' href='#n3930'>3930</a>
<a id='n3931' href='#n3931'>3931</a>
<a id='n3932' href='#n3932'>3932</a>
<a id='n3933' href='#n3933'>3933</a>
<a id='n3934' href='#n3934'>3934</a>
<a id='n3935' href='#n3935'>3935</a>
<a id='n3936' href='#n3936'>3936</a>
<a id='n3937' href='#n3937'>3937</a>
<a id='n3938' href='#n3938'>3938</a>
<a id='n3939' href='#n3939'>3939</a>
<a id='n3940' href='#n3940'>3940</a>
<a id='n3941' href='#n3941'>3941</a>
<a id='n3942' href='#n3942'>3942</a>
<a id='n3943' href='#n3943'>3943</a>
<a id='n3944' href='#n3944'>3944</a>
<a id='n3945' href='#n3945'>3945</a>
<a id='n3946' href='#n3946'>3946</a>
<a id='n3947' href='#n3947'>3947</a>
<a id='n3948' href='#n3948'>3948</a>
<a id='n3949' href='#n3949'>3949</a>
<a id='n3950' href='#n3950'>3950</a>
<a id='n3951' href='#n3951'>3951</a>
<a id='n3952' href='#n3952'>3952</a>
<a id='n3953' href='#n3953'>3953</a>
<a id='n3954' href='#n3954'>3954</a>
<a id='n3955' href='#n3955'>3955</a>
<a id='n3956' href='#n3956'>3956</a>
<a id='n3957' href='#n3957'>3957</a>
<a id='n3958' href='#n3958'>3958</a>
<a id='n3959' href='#n3959'>3959</a>
<a id='n3960' href='#n3960'>3960</a>
<a id='n3961' href='#n3961'>3961</a>
<a id='n3962' href='#n3962'>3962</a>
<a id='n3963' href='#n3963'>3963</a>
<a id='n3964' href='#n3964'>3964</a>
<a id='n3965' href='#n3965'>3965</a>
<a id='n3966' href='#n3966'>3966</a>
<a id='n3967' href='#n3967'>3967</a>
<a id='n3968' href='#n3968'>3968</a>
<a id='n3969' href='#n3969'>3969</a>
<a id='n3970' href='#n3970'>3970</a>
<a id='n3971' href='#n3971'>3971</a>
<a id='n3972' href='#n3972'>3972</a>
<a id='n3973' href='#n3973'>3973</a>
<a id='n3974' href='#n3974'>3974</a>
<a id='n3975' href='#n3975'>3975</a>
<a id='n3976' href='#n3976'>3976</a>
<a id='n3977' href='#n3977'>3977</a>
<a id='n3978' href='#n3978'>3978</a>
<a id='n3979' href='#n3979'>3979</a>
<a id='n3980' href='#n3980'>3980</a>
<a id='n3981' href='#n3981'>3981</a>
<a id='n3982' href='#n3982'>3982</a>
<a id='n3983' href='#n3983'>3983</a>
<a id='n3984' href='#n3984'>3984</a>
<a id='n3985' href='#n3985'>3985</a>
<a id='n3986' href='#n3986'>3986</a>
<a id='n3987' href='#n3987'>3987</a>
<a id='n3988' href='#n3988'>3988</a>
<a id='n3989' href='#n3989'>3989</a>
<a id='n3990' href='#n3990'>3990</a>
<a id='n3991' href='#n3991'>3991</a>
<a id='n3992' href='#n3992'>3992</a>
<a id='n3993' href='#n3993'>3993</a>
<a id='n3994' href='#n3994'>3994</a>
<a id='n3995' href='#n3995'>3995</a>
<a id='n3996' href='#n3996'>3996</a>
<a id='n3997' href='#n3997'>3997</a>
<a id='n3998' href='#n3998'>3998</a>
<a id='n3999' href='#n3999'>3999</a>
<a id='n4000' href='#n4000'>4000</a>
<a id='n4001' href='#n4001'>4001</a>
<a id='n4002' href='#n4002'>4002</a>
<a id='n4003' href='#n4003'>4003</a>
<a id='n4004' href='#n4004'>4004</a>
<a id='n4005' href='#n4005'>4005</a>
<a id='n4006' href='#n4006'>4006</a>
<a id='n4007' href='#n4007'>4007</a>
<a id='n4008' href='#n4008'>4008</a>
<a id='n4009' href='#n4009'>4009</a>
<a id='n4010' href='#n4010'>4010</a>
<a id='n4011' href='#n4011'>4011</a>
<a id='n4012' href='#n4012'>4012</a>
<a id='n4013' href='#n4013'>4013</a>
<a id='n4014' href='#n4014'>4014</a>
<a id='n4015' href='#n4015'>4015</a>
<a id='n4016' href='#n4016'>4016</a>
<a id='n4017' href='#n4017'>4017</a>
<a id='n4018' href='#n4018'>4018</a>
<a id='n4019' href='#n4019'>4019</a>
<a id='n4020' href='#n4020'>4020</a>
<a id='n4021' href='#n4021'>4021</a>
<a id='n4022' href='#n4022'>4022</a>
<a id='n4023' href='#n4023'>4023</a>
<a id='n4024' href='#n4024'>4024</a>
<a id='n4025' href='#n4025'>4025</a>
<a id='n4026' href='#n4026'>4026</a>
<a id='n4027' href='#n4027'>4027</a>
<a id='n4028' href='#n4028'>4028</a>
<a id='n4029' href='#n4029'>4029</a>
<a id='n4030' href='#n4030'>4030</a>
<a id='n4031' href='#n4031'>4031</a>
<a id='n4032' href='#n4032'>4032</a>
<a id='n4033' href='#n4033'>4033</a>
<a id='n4034' href='#n4034'>4034</a>
<a id='n4035' href='#n4035'>4035</a>
<a id='n4036' href='#n4036'>4036</a>
<a id='n4037' href='#n4037'>4037</a>
<a id='n4038' href='#n4038'>4038</a>
<a id='n4039' href='#n4039'>4039</a>
<a id='n4040' href='#n4040'>4040</a>
<a id='n4041' href='#n4041'>4041</a>
<a id='n4042' href='#n4042'>4042</a>
<a id='n4043' href='#n4043'>4043</a>
<a id='n4044' href='#n4044'>4044</a>
<a id='n4045' href='#n4045'>4045</a>
<a id='n4046' href='#n4046'>4046</a>
<a id='n4047' href='#n4047'>4047</a>
<a id='n4048' href='#n4048'>4048</a>
<a id='n4049' href='#n4049'>4049</a>
<a id='n4050' href='#n4050'>4050</a>
<a id='n4051' href='#n4051'>4051</a>
<a id='n4052' href='#n4052'>4052</a>
<a id='n4053' href='#n4053'>4053</a>
<a id='n4054' href='#n4054'>4054</a>
<a id='n4055' href='#n4055'>4055</a>
<a id='n4056' href='#n4056'>4056</a>
<a id='n4057' href='#n4057'>4057</a>
<a id='n4058' href='#n4058'>4058</a>
<a id='n4059' href='#n4059'>4059</a>
<a id='n4060' href='#n4060'>4060</a>
<a id='n4061' href='#n4061'>4061</a>
<a id='n4062' href='#n4062'>4062</a>
<a id='n4063' href='#n4063'>4063</a>
<a id='n4064' href='#n4064'>4064</a>
<a id='n4065' href='#n4065'>4065</a>
<a id='n4066' href='#n4066'>4066</a>
<a id='n4067' href='#n4067'>4067</a>
<a id='n4068' href='#n4068'>4068</a>
<a id='n4069' href='#n4069'>4069</a>
<a id='n4070' href='#n4070'>4070</a>
<a id='n4071' href='#n4071'>4071</a>
<a id='n4072' href='#n4072'>4072</a>
<a id='n4073' href='#n4073'>4073</a>
<a id='n4074' href='#n4074'>4074</a>
<a id='n4075' href='#n4075'>4075</a>
<a id='n4076' href='#n4076'>4076</a>
<a id='n4077' href='#n4077'>4077</a>
<a id='n4078' href='#n4078'>4078</a>
<a id='n4079' href='#n4079'>4079</a>
<a id='n4080' href='#n4080'>4080</a>
<a id='n4081' href='#n4081'>4081</a>
<a id='n4082' href='#n4082'>4082</a>
<a id='n4083' href='#n4083'>4083</a>
<a id='n4084' href='#n4084'>4084</a>
<a id='n4085' href='#n4085'>4085</a>
<a id='n4086' href='#n4086'>4086</a>
<a id='n4087' href='#n4087'>4087</a>
<a id='n4088' href='#n4088'>4088</a>
<a id='n4089' href='#n4089'>4089</a>
<a id='n4090' href='#n4090'>4090</a>
<a id='n4091' href='#n4091'>4091</a>
<a id='n4092' href='#n4092'>4092</a>
<a id='n4093' href='#n4093'>4093</a>
<a id='n4094' href='#n4094'>4094</a>
<a id='n4095' href='#n4095'>4095</a>
<a id='n4096' href='#n4096'>4096</a>
<a id='n4097' href='#n4097'>4097</a>
<a id='n4098' href='#n4098'>4098</a>
<a id='n4099' href='#n4099'>4099</a>
<a id='n4100' href='#n4100'>4100</a>
<a id='n4101' href='#n4101'>4101</a>
<a id='n4102' href='#n4102'>4102</a>
<a id='n4103' href='#n4103'>4103</a>
<a id='n4104' href='#n4104'>4104</a>
<a id='n4105' href='#n4105'>4105</a>
<a id='n4106' href='#n4106'>4106</a>
<a id='n4107' href='#n4107'>4107</a>
<a id='n4108' href='#n4108'>4108</a>
<a id='n4109' href='#n4109'>4109</a>
<a id='n4110' href='#n4110'>4110</a>
<a id='n4111' href='#n4111'>4111</a>
<a id='n4112' href='#n4112'>4112</a>
<a id='n4113' href='#n4113'>4113</a>
<a id='n4114' href='#n4114'>4114</a>
<a id='n4115' href='#n4115'>4115</a>
<a id='n4116' href='#n4116'>4116</a>
<a id='n4117' href='#n4117'>4117</a>
<a id='n4118' href='#n4118'>4118</a>
<a id='n4119' href='#n4119'>4119</a>
<a id='n4120' href='#n4120'>4120</a>
<a id='n4121' href='#n4121'>4121</a>
<a id='n4122' href='#n4122'>4122</a>
<a id='n4123' href='#n4123'>4123</a>
<a id='n4124' href='#n4124'>4124</a>
<a id='n4125' href='#n4125'>4125</a>
<a id='n4126' href='#n4126'>4126</a>
<a id='n4127' href='#n4127'>4127</a>
<a id='n4128' href='#n4128'>4128</a>
<a id='n4129' href='#n4129'>4129</a>
<a id='n4130' href='#n4130'>4130</a>
<a id='n4131' href='#n4131'>4131</a>
<a id='n4132' href='#n4132'>4132</a>
<a id='n4133' href='#n4133'>4133</a>
<a id='n4134' href='#n4134'>4134</a>
<a id='n4135' href='#n4135'>4135</a>
<a id='n4136' href='#n4136'>4136</a>
<a id='n4137' href='#n4137'>4137</a>
<a id='n4138' href='#n4138'>4138</a>
<a id='n4139' href='#n4139'>4139</a>
<a id='n4140' href='#n4140'>4140</a>
<a id='n4141' href='#n4141'>4141</a>
<a id='n4142' href='#n4142'>4142</a>
<a id='n4143' href='#n4143'>4143</a>
<a id='n4144' href='#n4144'>4144</a>
<a id='n4145' href='#n4145'>4145</a>
<a id='n4146' href='#n4146'>4146</a>
<a id='n4147' href='#n4147'>4147</a>
<a id='n4148' href='#n4148'>4148</a>
<a id='n4149' href='#n4149'>4149</a>
<a id='n4150' href='#n4150'>4150</a>
<a id='n4151' href='#n4151'>4151</a>
<a id='n4152' href='#n4152'>4152</a>
<a id='n4153' href='#n4153'>4153</a>
<a id='n4154' href='#n4154'>4154</a>
<a id='n4155' href='#n4155'>4155</a>
<a id='n4156' href='#n4156'>4156</a>
<a id='n4157' href='#n4157'>4157</a>
<a id='n4158' href='#n4158'>4158</a>
<a id='n4159' href='#n4159'>4159</a>
<a id='n4160' href='#n4160'>4160</a>
<a id='n4161' href='#n4161'>4161</a>
<a id='n4162' href='#n4162'>4162</a>
<a id='n4163' href='#n4163'>4163</a>
<a id='n4164' href='#n4164'>4164</a>
<a id='n4165' href='#n4165'>4165</a>
<a id='n4166' href='#n4166'>4166</a>
<a id='n4167' href='#n4167'>4167</a>
<a id='n4168' href='#n4168'>4168</a>
<a id='n4169' href='#n4169'>4169</a>
<a id='n4170' href='#n4170'>4170</a>
<a id='n4171' href='#n4171'>4171</a>
<a id='n4172' href='#n4172'>4172</a>
<a id='n4173' href='#n4173'>4173</a>
<a id='n4174' href='#n4174'>4174</a>
<a id='n4175' href='#n4175'>4175</a>
<a id='n4176' href='#n4176'>4176</a>
<a id='n4177' href='#n4177'>4177</a>
<a id='n4178' href='#n4178'>4178</a>
<a id='n4179' href='#n4179'>4179</a>
<a id='n4180' href='#n4180'>4180</a>
<a id='n4181' href='#n4181'>4181</a>
<a id='n4182' href='#n4182'>4182</a>
<a id='n4183' href='#n4183'>4183</a>
<a id='n4184' href='#n4184'>4184</a>
<a id='n4185' href='#n4185'>4185</a>
<a id='n4186' href='#n4186'>4186</a>
<a id='n4187' href='#n4187'>4187</a>
<a id='n4188' href='#n4188'>4188</a>
<a id='n4189' href='#n4189'>4189</a>
<a id='n4190' href='#n4190'>4190</a>
<a id='n4191' href='#n4191'>4191</a>
<a id='n4192' href='#n4192'>4192</a>
<a id='n4193' href='#n4193'>4193</a>
<a id='n4194' href='#n4194'>4194</a>
<a id='n4195' href='#n4195'>4195</a>
<a id='n4196' href='#n4196'>4196</a>
<a id='n4197' href='#n4197'>4197</a>
<a id='n4198' href='#n4198'>4198</a>
<a id='n4199' href='#n4199'>4199</a>
<a id='n4200' href='#n4200'>4200</a>
<a id='n4201' href='#n4201'>4201</a>
<a id='n4202' href='#n4202'>4202</a>
<a id='n4203' href='#n4203'>4203</a>
<a id='n4204' href='#n4204'>4204</a>
<a id='n4205' href='#n4205'>4205</a>
<a id='n4206' href='#n4206'>4206</a>
<a id='n4207' href='#n4207'>4207</a>
<a id='n4208' href='#n4208'>4208</a>
<a id='n4209' href='#n4209'>4209</a>
<a id='n4210' href='#n4210'>4210</a>
<a id='n4211' href='#n4211'>4211</a>
<a id='n4212' href='#n4212'>4212</a>
<a id='n4213' href='#n4213'>4213</a>
<a id='n4214' href='#n4214'>4214</a>
<a id='n4215' href='#n4215'>4215</a>
<a id='n4216' href='#n4216'>4216</a>
<a id='n4217' href='#n4217'>4217</a>
<a id='n4218' href='#n4218'>4218</a>
<a id='n4219' href='#n4219'>4219</a>
<a id='n4220' href='#n4220'>4220</a>
<a id='n4221' href='#n4221'>4221</a>
<a id='n4222' href='#n4222'>4222</a>
<a id='n4223' href='#n4223'>4223</a>
<a id='n4224' href='#n4224'>4224</a>
<a id='n4225' href='#n4225'>4225</a>
<a id='n4226' href='#n4226'>4226</a>
<a id='n4227' href='#n4227'>4227</a>
<a id='n4228' href='#n4228'>4228</a>
<a id='n4229' href='#n4229'>4229</a>
<a id='n4230' href='#n4230'>4230</a>
<a id='n4231' href='#n4231'>4231</a>
<a id='n4232' href='#n4232'>4232</a>
<a id='n4233' href='#n4233'>4233</a>
<a id='n4234' href='#n4234'>4234</a>
<a id='n4235' href='#n4235'>4235</a>
<a id='n4236' href='#n4236'>4236</a>
<a id='n4237' href='#n4237'>4237</a>
<a id='n4238' href='#n4238'>4238</a>
<a id='n4239' href='#n4239'>4239</a>
<a id='n4240' href='#n4240'>4240</a>
<a id='n4241' href='#n4241'>4241</a>
<a id='n4242' href='#n4242'>4242</a>
<a id='n4243' href='#n4243'>4243</a>
<a id='n4244' href='#n4244'>4244</a>
<a id='n4245' href='#n4245'>4245</a>
<a id='n4246' href='#n4246'>4246</a>
<a id='n4247' href='#n4247'>4247</a>
<a id='n4248' href='#n4248'>4248</a>
<a id='n4249' href='#n4249'>4249</a>
<a id='n4250' href='#n4250'>4250</a>
<a id='n4251' href='#n4251'>4251</a>
<a id='n4252' href='#n4252'>4252</a>
<a id='n4253' href='#n4253'>4253</a>
<a id='n4254' href='#n4254'>4254</a>
<a id='n4255' href='#n4255'>4255</a>
<a id='n4256' href='#n4256'>4256</a>
<a id='n4257' href='#n4257'>4257</a>
<a id='n4258' href='#n4258'>4258</a>
<a id='n4259' href='#n4259'>4259</a>
<a id='n4260' href='#n4260'>4260</a>
<a id='n4261' href='#n4261'>4261</a>
<a id='n4262' href='#n4262'>4262</a>
<a id='n4263' href='#n4263'>4263</a>
<a id='n4264' href='#n4264'>4264</a>
<a id='n4265' href='#n4265'>4265</a>
<a id='n4266' href='#n4266'>4266</a>
<a id='n4267' href='#n4267'>4267</a>
<a id='n4268' href='#n4268'>4268</a>
<a id='n4269' href='#n4269'>4269</a>
<a id='n4270' href='#n4270'>4270</a>
<a id='n4271' href='#n4271'>4271</a>
<a id='n4272' href='#n4272'>4272</a>
<a id='n4273' href='#n4273'>4273</a>
<a id='n4274' href='#n4274'>4274</a>
<a id='n4275' href='#n4275'>4275</a>
<a id='n4276' href='#n4276'>4276</a>
<a id='n4277' href='#n4277'>4277</a>
<a id='n4278' href='#n4278'>4278</a>
<a id='n4279' href='#n4279'>4279</a>
<a id='n4280' href='#n4280'>4280</a>
<a id='n4281' href='#n4281'>4281</a>
<a id='n4282' href='#n4282'>4282</a>
<a id='n4283' href='#n4283'>4283</a>
<a id='n4284' href='#n4284'>4284</a>
<a id='n4285' href='#n4285'>4285</a>
<a id='n4286' href='#n4286'>4286</a>
<a id='n4287' href='#n4287'>4287</a>
<a id='n4288' href='#n4288'>4288</a>
<a id='n4289' href='#n4289'>4289</a>
<a id='n4290' href='#n4290'>4290</a>
<a id='n4291' href='#n4291'>4291</a>
<a id='n4292' href='#n4292'>4292</a>
<a id='n4293' href='#n4293'>4293</a>
<a id='n4294' href='#n4294'>4294</a>
<a id='n4295' href='#n4295'>4295</a>
<a id='n4296' href='#n4296'>4296</a>
<a id='n4297' href='#n4297'>4297</a>
<a id='n4298' href='#n4298'>4298</a>
<a id='n4299' href='#n4299'>4299</a>
<a id='n4300' href='#n4300'>4300</a>
<a id='n4301' href='#n4301'>4301</a>
<a id='n4302' href='#n4302'>4302</a>
<a id='n4303' href='#n4303'>4303</a>
<a id='n4304' href='#n4304'>4304</a>
<a id='n4305' href='#n4305'>4305</a>
<a id='n4306' href='#n4306'>4306</a>
<a id='n4307' href='#n4307'>4307</a>
<a id='n4308' href='#n4308'>4308</a>
<a id='n4309' href='#n4309'>4309</a>
<a id='n4310' href='#n4310'>4310</a>
<a id='n4311' href='#n4311'>4311</a>
<a id='n4312' href='#n4312'>4312</a>
<a id='n4313' href='#n4313'>4313</a>
<a id='n4314' href='#n4314'>4314</a>
<a id='n4315' href='#n4315'>4315</a>
<a id='n4316' href='#n4316'>4316</a>
<a id='n4317' href='#n4317'>4317</a>
<a id='n4318' href='#n4318'>4318</a>
<a id='n4319' href='#n4319'>4319</a>
<a id='n4320' href='#n4320'>4320</a>
<a id='n4321' href='#n4321'>4321</a>
<a id='n4322' href='#n4322'>4322</a>
<a id='n4323' href='#n4323'>4323</a>
<a id='n4324' href='#n4324'>4324</a>
<a id='n4325' href='#n4325'>4325</a>
<a id='n4326' href='#n4326'>4326</a>
<a id='n4327' href='#n4327'>4327</a>
<a id='n4328' href='#n4328'>4328</a>
<a id='n4329' href='#n4329'>4329</a>
<a id='n4330' href='#n4330'>4330</a>
<a id='n4331' href='#n4331'>4331</a>
<a id='n4332' href='#n4332'>4332</a>
<a id='n4333' href='#n4333'>4333</a>
<a id='n4334' href='#n4334'>4334</a>
<a id='n4335' href='#n4335'>4335</a>
<a id='n4336' href='#n4336'>4336</a>
<a id='n4337' href='#n4337'>4337</a>
<a id='n4338' href='#n4338'>4338</a>
<a id='n4339' href='#n4339'>4339</a>
<a id='n4340' href='#n4340'>4340</a>
<a id='n4341' href='#n4341'>4341</a>
<a id='n4342' href='#n4342'>4342</a>
<a id='n4343' href='#n4343'>4343</a>
<a id='n4344' href='#n4344'>4344</a>
<a id='n4345' href='#n4345'>4345</a>
<a id='n4346' href='#n4346'>4346</a>
<a id='n4347' href='#n4347'>4347</a>
<a id='n4348' href='#n4348'>4348</a>
<a id='n4349' href='#n4349'>4349</a>
<a id='n4350' href='#n4350'>4350</a>
<a id='n4351' href='#n4351'>4351</a>
<a id='n4352' href='#n4352'>4352</a>
<a id='n4353' href='#n4353'>4353</a>
<a id='n4354' href='#n4354'>4354</a>
<a id='n4355' href='#n4355'>4355</a>
<a id='n4356' href='#n4356'>4356</a>
<a id='n4357' href='#n4357'>4357</a>
<a id='n4358' href='#n4358'>4358</a>
<a id='n4359' href='#n4359'>4359</a>
<a id='n4360' href='#n4360'>4360</a>
<a id='n4361' href='#n4361'>4361</a>
<a id='n4362' href='#n4362'>4362</a>
<a id='n4363' href='#n4363'>4363</a>
<a id='n4364' href='#n4364'>4364</a>
<a id='n4365' href='#n4365'>4365</a>
<a id='n4366' href='#n4366'>4366</a>
<a id='n4367' href='#n4367'>4367</a>
<a id='n4368' href='#n4368'>4368</a>
<a id='n4369' href='#n4369'>4369</a>
<a id='n4370' href='#n4370'>4370</a>
<a id='n4371' href='#n4371'>4371</a>
<a id='n4372' href='#n4372'>4372</a>
<a id='n4373' href='#n4373'>4373</a>
<a id='n4374' href='#n4374'>4374</a>
<a id='n4375' href='#n4375'>4375</a>
<a id='n4376' href='#n4376'>4376</a>
<a id='n4377' href='#n4377'>4377</a>
<a id='n4378' href='#n4378'>4378</a>
<a id='n4379' href='#n4379'>4379</a>
<a id='n4380' href='#n4380'>4380</a>
<a id='n4381' href='#n4381'>4381</a>
<a id='n4382' href='#n4382'>4382</a>
<a id='n4383' href='#n4383'>4383</a>
<a id='n4384' href='#n4384'>4384</a>
<a id='n4385' href='#n4385'>4385</a>
<a id='n4386' href='#n4386'>4386</a>
<a id='n4387' href='#n4387'>4387</a>
<a id='n4388' href='#n4388'>4388</a>
<a id='n4389' href='#n4389'>4389</a>
<a id='n4390' href='#n4390'>4390</a>
<a id='n4391' href='#n4391'>4391</a>
<a id='n4392' href='#n4392'>4392</a>
<a id='n4393' href='#n4393'>4393</a>
<a id='n4394' href='#n4394'>4394</a>
<a id='n4395' href='#n4395'>4395</a>
<a id='n4396' href='#n4396'>4396</a>
<a id='n4397' href='#n4397'>4397</a>
<a id='n4398' href='#n4398'>4398</a>
<a id='n4399' href='#n4399'>4399</a>
<a id='n4400' href='#n4400'>4400</a>
<a id='n4401' href='#n4401'>4401</a>
<a id='n4402' href='#n4402'>4402</a>
<a id='n4403' href='#n4403'>4403</a>
<a id='n4404' href='#n4404'>4404</a>
<a id='n4405' href='#n4405'>4405</a>
<a id='n4406' href='#n4406'>4406</a>
<a id='n4407' href='#n4407'>4407</a>
<a id='n4408' href='#n4408'>4408</a>
<a id='n4409' href='#n4409'>4409</a>
<a id='n4410' href='#n4410'>4410</a>
<a id='n4411' href='#n4411'>4411</a>
<a id='n4412' href='#n4412'>4412</a>
<a id='n4413' href='#n4413'>4413</a>
<a id='n4414' href='#n4414'>4414</a>
<a id='n4415' href='#n4415'>4415</a>
<a id='n4416' href='#n4416'>4416</a>
<a id='n4417' href='#n4417'>4417</a>
<a id='n4418' href='#n4418'>4418</a>
<a id='n4419' href='#n4419'>4419</a>
<a id='n4420' href='#n4420'>4420</a>
<a id='n4421' href='#n4421'>4421</a>
<a id='n4422' href='#n4422'>4422</a>
<a id='n4423' href='#n4423'>4423</a>
<a id='n4424' href='#n4424'>4424</a>
<a id='n4425' href='#n4425'>4425</a>
<a id='n4426' href='#n4426'>4426</a>
<a id='n4427' href='#n4427'>4427</a>
<a id='n4428' href='#n4428'>4428</a>
<a id='n4429' href='#n4429'>4429</a>
<a id='n4430' href='#n4430'>4430</a>
<a id='n4431' href='#n4431'>4431</a>
<a id='n4432' href='#n4432'>4432</a>
<a id='n4433' href='#n4433'>4433</a>
<a id='n4434' href='#n4434'>4434</a>
<a id='n4435' href='#n4435'>4435</a>
<a id='n4436' href='#n4436'>4436</a>
<a id='n4437' href='#n4437'>4437</a>
<a id='n4438' href='#n4438'>4438</a>
<a id='n4439' href='#n4439'>4439</a>
<a id='n4440' href='#n4440'>4440</a>
<a id='n4441' href='#n4441'>4441</a>
<a id='n4442' href='#n4442'>4442</a>
<a id='n4443' href='#n4443'>4443</a>
<a id='n4444' href='#n4444'>4444</a>
<a id='n4445' href='#n4445'>4445</a>
<a id='n4446' href='#n4446'>4446</a>
<a id='n4447' href='#n4447'>4447</a>
<a id='n4448' href='#n4448'>4448</a>
<a id='n4449' href='#n4449'>4449</a>
<a id='n4450' href='#n4450'>4450</a>
<a id='n4451' href='#n4451'>4451</a>
<a id='n4452' href='#n4452'>4452</a>
<a id='n4453' href='#n4453'>4453</a>
<a id='n4454' href='#n4454'>4454</a>
<a id='n4455' href='#n4455'>4455</a>
<a id='n4456' href='#n4456'>4456</a>
<a id='n4457' href='#n4457'>4457</a>
<a id='n4458' href='#n4458'>4458</a>
<a id='n4459' href='#n4459'>4459</a>
<a id='n4460' href='#n4460'>4460</a>
<a id='n4461' href='#n4461'>4461</a>
<a id='n4462' href='#n4462'>4462</a>
<a id='n4463' href='#n4463'>4463</a>
<a id='n4464' href='#n4464'>4464</a>
<a id='n4465' href='#n4465'>4465</a>
<a id='n4466' href='#n4466'>4466</a>
<a id='n4467' href='#n4467'>4467</a>
<a id='n4468' href='#n4468'>4468</a>
<a id='n4469' href='#n4469'>4469</a>
<a id='n4470' href='#n4470'>4470</a>
<a id='n4471' href='#n4471'>4471</a>
<a id='n4472' href='#n4472'>4472</a>
<a id='n4473' href='#n4473'>4473</a>
<a id='n4474' href='#n4474'>4474</a>
<a id='n4475' href='#n4475'>4475</a>
<a id='n4476' href='#n4476'>4476</a>
<a id='n4477' href='#n4477'>4477</a>
<a id='n4478' href='#n4478'>4478</a>
<a id='n4479' href='#n4479'>4479</a>
<a id='n4480' href='#n4480'>4480</a>
<a id='n4481' href='#n4481'>4481</a>
<a id='n4482' href='#n4482'>4482</a>
<a id='n4483' href='#n4483'>4483</a>
<a id='n4484' href='#n4484'>4484</a>
<a id='n4485' href='#n4485'>4485</a>
<a id='n4486' href='#n4486'>4486</a>
<a id='n4487' href='#n4487'>4487</a>
<a id='n4488' href='#n4488'>4488</a>
<a id='n4489' href='#n4489'>4489</a>
<a id='n4490' href='#n4490'>4490</a>
<a id='n4491' href='#n4491'>4491</a>
<a id='n4492' href='#n4492'>4492</a>
<a id='n4493' href='#n4493'>4493</a>
<a id='n4494' href='#n4494'>4494</a>
<a id='n4495' href='#n4495'>4495</a>
<a id='n4496' href='#n4496'>4496</a>
<a id='n4497' href='#n4497'>4497</a>
<a id='n4498' href='#n4498'>4498</a>
<a id='n4499' href='#n4499'>4499</a>
<a id='n4500' href='#n4500'>4500</a>
<a id='n4501' href='#n4501'>4501</a>
<a id='n4502' href='#n4502'>4502</a>
<a id='n4503' href='#n4503'>4503</a>
<a id='n4504' href='#n4504'>4504</a>
<a id='n4505' href='#n4505'>4505</a>
<a id='n4506' href='#n4506'>4506</a>
<a id='n4507' href='#n4507'>4507</a>
<a id='n4508' href='#n4508'>4508</a>
<a id='n4509' href='#n4509'>4509</a>
<a id='n4510' href='#n4510'>4510</a>
<a id='n4511' href='#n4511'>4511</a>
<a id='n4512' href='#n4512'>4512</a>
<a id='n4513' href='#n4513'>4513</a>
<a id='n4514' href='#n4514'>4514</a>
<a id='n4515' href='#n4515'>4515</a>
<a id='n4516' href='#n4516'>4516</a>
<a id='n4517' href='#n4517'>4517</a>
<a id='n4518' href='#n4518'>4518</a>
<a id='n4519' href='#n4519'>4519</a>
<a id='n4520' href='#n4520'>4520</a>
<a id='n4521' href='#n4521'>4521</a>
<a id='n4522' href='#n4522'>4522</a>
<a id='n4523' href='#n4523'>4523</a>
<a id='n4524' href='#n4524'>4524</a>
<a id='n4525' href='#n4525'>4525</a>
<a id='n4526' href='#n4526'>4526</a>
<a id='n4527' href='#n4527'>4527</a>
<a id='n4528' href='#n4528'>4528</a>
<a id='n4529' href='#n4529'>4529</a>
<a id='n4530' href='#n4530'>4530</a>
<a id='n4531' href='#n4531'>4531</a>
<a id='n4532' href='#n4532'>4532</a>
<a id='n4533' href='#n4533'>4533</a>
<a id='n4534' href='#n4534'>4534</a>
<a id='n4535' href='#n4535'>4535</a>
<a id='n4536' href='#n4536'>4536</a>
<a id='n4537' href='#n4537'>4537</a>
<a id='n4538' href='#n4538'>4538</a>
<a id='n4539' href='#n4539'>4539</a>
<a id='n4540' href='#n4540'>4540</a>
<a id='n4541' href='#n4541'>4541</a>
<a id='n4542' href='#n4542'>4542</a>
<a id='n4543' href='#n4543'>4543</a>
<a id='n4544' href='#n4544'>4544</a>
<a id='n4545' href='#n4545'>4545</a>
<a id='n4546' href='#n4546'>4546</a>
<a id='n4547' href='#n4547'>4547</a>
<a id='n4548' href='#n4548'>4548</a>
<a id='n4549' href='#n4549'>4549</a>
<a id='n4550' href='#n4550'>4550</a>
<a id='n4551' href='#n4551'>4551</a>
<a id='n4552' href='#n4552'>4552</a>
<a id='n4553' href='#n4553'>4553</a>
<a id='n4554' href='#n4554'>4554</a>
<a id='n4555' href='#n4555'>4555</a>
<a id='n4556' href='#n4556'>4556</a>
<a id='n4557' href='#n4557'>4557</a>
<a id='n4558' href='#n4558'>4558</a>
<a id='n4559' href='#n4559'>4559</a>
<a id='n4560' href='#n4560'>4560</a>
<a id='n4561' href='#n4561'>4561</a>
<a id='n4562' href='#n4562'>4562</a>
<a id='n4563' href='#n4563'>4563</a>
<a id='n4564' href='#n4564'>4564</a>
<a id='n4565' href='#n4565'>4565</a>
<a id='n4566' href='#n4566'>4566</a>
<a id='n4567' href='#n4567'>4567</a>
<a id='n4568' href='#n4568'>4568</a>
<a id='n4569' href='#n4569'>4569</a>
<a id='n4570' href='#n4570'>4570</a>
<a id='n4571' href='#n4571'>4571</a>
<a id='n4572' href='#n4572'>4572</a>
<a id='n4573' href='#n4573'>4573</a>
<a id='n4574' href='#n4574'>4574</a>
<a id='n4575' href='#n4575'>4575</a>
<a id='n4576' href='#n4576'>4576</a>
<a id='n4577' href='#n4577'>4577</a>
<a id='n4578' href='#n4578'>4578</a>
<a id='n4579' href='#n4579'>4579</a>
<a id='n4580' href='#n4580'>4580</a>
<a id='n4581' href='#n4581'>4581</a>
<a id='n4582' href='#n4582'>4582</a>
<a id='n4583' href='#n4583'>4583</a>
<a id='n4584' href='#n4584'>4584</a>
<a id='n4585' href='#n4585'>4585</a>
<a id='n4586' href='#n4586'>4586</a>
<a id='n4587' href='#n4587'>4587</a>
<a id='n4588' href='#n4588'>4588</a>
<a id='n4589' href='#n4589'>4589</a>
<a id='n4590' href='#n4590'>4590</a>
<a id='n4591' href='#n4591'>4591</a>
<a id='n4592' href='#n4592'>4592</a>
<a id='n4593' href='#n4593'>4593</a>
<a id='n4594' href='#n4594'>4594</a>
<a id='n4595' href='#n4595'>4595</a>
<a id='n4596' href='#n4596'>4596</a>
<a id='n4597' href='#n4597'>4597</a>
<a id='n4598' href='#n4598'>4598</a>
<a id='n4599' href='#n4599'>4599</a>
<a id='n4600' href='#n4600'>4600</a>
<a id='n4601' href='#n4601'>4601</a>
<a id='n4602' href='#n4602'>4602</a>
<a id='n4603' href='#n4603'>4603</a>
<a id='n4604' href='#n4604'>4604</a>
<a id='n4605' href='#n4605'>4605</a>
<a id='n4606' href='#n4606'>4606</a>
<a id='n4607' href='#n4607'>4607</a>
<a id='n4608' href='#n4608'>4608</a>
<a id='n4609' href='#n4609'>4609</a>
<a id='n4610' href='#n4610'>4610</a>
<a id='n4611' href='#n4611'>4611</a>
<a id='n4612' href='#n4612'>4612</a>
<a id='n4613' href='#n4613'>4613</a>
<a id='n4614' href='#n4614'>4614</a>
<a id='n4615' href='#n4615'>4615</a>
<a id='n4616' href='#n4616'>4616</a>
<a id='n4617' href='#n4617'>4617</a>
<a id='n4618' href='#n4618'>4618</a>
<a id='n4619' href='#n4619'>4619</a>
<a id='n4620' href='#n4620'>4620</a>
<a id='n4621' href='#n4621'>4621</a>
<a id='n4622' href='#n4622'>4622</a>
<a id='n4623' href='#n4623'>4623</a>
<a id='n4624' href='#n4624'>4624</a>
<a id='n4625' href='#n4625'>4625</a>
<a id='n4626' href='#n4626'>4626</a>
<a id='n4627' href='#n4627'>4627</a>
<a id='n4628' href='#n4628'>4628</a>
<a id='n4629' href='#n4629'>4629</a>
<a id='n4630' href='#n4630'>4630</a>
<a id='n4631' href='#n4631'>4631</a>
<a id='n4632' href='#n4632'>4632</a>
<a id='n4633' href='#n4633'>4633</a>
<a id='n4634' href='#n4634'>4634</a>
<a id='n4635' href='#n4635'>4635</a>
<a id='n4636' href='#n4636'>4636</a>
<a id='n4637' href='#n4637'>4637</a>
<a id='n4638' href='#n4638'>4638</a>
<a id='n4639' href='#n4639'>4639</a>
<a id='n4640' href='#n4640'>4640</a>
<a id='n4641' href='#n4641'>4641</a>
<a id='n4642' href='#n4642'>4642</a>
<a id='n4643' href='#n4643'>4643</a>
<a id='n4644' href='#n4644'>4644</a>
<a id='n4645' href='#n4645'>4645</a>
<a id='n4646' href='#n4646'>4646</a>
<a id='n4647' href='#n4647'>4647</a>
<a id='n4648' href='#n4648'>4648</a>
<a id='n4649' href='#n4649'>4649</a>
<a id='n4650' href='#n4650'>4650</a>
<a id='n4651' href='#n4651'>4651</a>
<a id='n4652' href='#n4652'>4652</a>
<a id='n4653' href='#n4653'>4653</a>
<a id='n4654' href='#n4654'>4654</a>
<a id='n4655' href='#n4655'>4655</a>
<a id='n4656' href='#n4656'>4656</a>
<a id='n4657' href='#n4657'>4657</a>
<a id='n4658' href='#n4658'>4658</a>
<a id='n4659' href='#n4659'>4659</a>
<a id='n4660' href='#n4660'>4660</a>
<a id='n4661' href='#n4661'>4661</a>
<a id='n4662' href='#n4662'>4662</a>
<a id='n4663' href='#n4663'>4663</a>
<a id='n4664' href='#n4664'>4664</a>
<a id='n4665' href='#n4665'>4665</a>
<a id='n4666' href='#n4666'>4666</a>
<a id='n4667' href='#n4667'>4667</a>
<a id='n4668' href='#n4668'>4668</a>
<a id='n4669' href='#n4669'>4669</a>
<a id='n4670' href='#n4670'>4670</a>
<a id='n4671' href='#n4671'>4671</a>
<a id='n4672' href='#n4672'>4672</a>
<a id='n4673' href='#n4673'>4673</a>
<a id='n4674' href='#n4674'>4674</a>
<a id='n4675' href='#n4675'>4675</a>
<a id='n4676' href='#n4676'>4676</a>
<a id='n4677' href='#n4677'>4677</a>
<a id='n4678' href='#n4678'>4678</a>
<a id='n4679' href='#n4679'>4679</a>
<a id='n4680' href='#n4680'>4680</a>
<a id='n4681' href='#n4681'>4681</a>
<a id='n4682' href='#n4682'>4682</a>
<a id='n4683' href='#n4683'>4683</a>
<a id='n4684' href='#n4684'>4684</a>
<a id='n4685' href='#n4685'>4685</a>
<a id='n4686' href='#n4686'>4686</a>
<a id='n4687' href='#n4687'>4687</a>
<a id='n4688' href='#n4688'>4688</a>
<a id='n4689' href='#n4689'>4689</a>
<a id='n4690' href='#n4690'>4690</a>
<a id='n4691' href='#n4691'>4691</a>
<a id='n4692' href='#n4692'>4692</a>
<a id='n4693' href='#n4693'>4693</a>
<a id='n4694' href='#n4694'>4694</a>
<a id='n4695' href='#n4695'>4695</a>
<a id='n4696' href='#n4696'>4696</a>
<a id='n4697' href='#n4697'>4697</a>
<a id='n4698' href='#n4698'>4698</a>
<a id='n4699' href='#n4699'>4699</a>
<a id='n4700' href='#n4700'>4700</a>
<a id='n4701' href='#n4701'>4701</a>
<a id='n4702' href='#n4702'>4702</a>
<a id='n4703' href='#n4703'>4703</a>
<a id='n4704' href='#n4704'>4704</a>
<a id='n4705' href='#n4705'>4705</a>
<a id='n4706' href='#n4706'>4706</a>
<a id='n4707' href='#n4707'>4707</a>
<a id='n4708' href='#n4708'>4708</a>
<a id='n4709' href='#n4709'>4709</a>
<a id='n4710' href='#n4710'>4710</a>
<a id='n4711' href='#n4711'>4711</a>
<a id='n4712' href='#n4712'>4712</a>
<a id='n4713' href='#n4713'>4713</a>
<a id='n4714' href='#n4714'>4714</a>
<a id='n4715' href='#n4715'>4715</a>
<a id='n4716' href='#n4716'>4716</a>
<a id='n4717' href='#n4717'>4717</a>
<a id='n4718' href='#n4718'>4718</a>
<a id='n4719' href='#n4719'>4719</a>
<a id='n4720' href='#n4720'>4720</a>
<a id='n4721' href='#n4721'>4721</a>
<a id='n4722' href='#n4722'>4722</a>
<a id='n4723' href='#n4723'>4723</a>
<a id='n4724' href='#n4724'>4724</a>
<a id='n4725' href='#n4725'>4725</a>
<a id='n4726' href='#n4726'>4726</a>
<a id='n4727' href='#n4727'>4727</a>
<a id='n4728' href='#n4728'>4728</a>
<a id='n4729' href='#n4729'>4729</a>
<a id='n4730' href='#n4730'>4730</a>
<a id='n4731' href='#n4731'>4731</a>
<a id='n4732' href='#n4732'>4732</a>
<a id='n4733' href='#n4733'>4733</a>
<a id='n4734' href='#n4734'>4734</a>
<a id='n4735' href='#n4735'>4735</a>
<a id='n4736' href='#n4736'>4736</a>
<a id='n4737' href='#n4737'>4737</a>
<a id='n4738' href='#n4738'>4738</a>
<a id='n4739' href='#n4739'>4739</a>
<a id='n4740' href='#n4740'>4740</a>
<a id='n4741' href='#n4741'>4741</a>
<a id='n4742' href='#n4742'>4742</a>
<a id='n4743' href='#n4743'>4743</a>
<a id='n4744' href='#n4744'>4744</a>
<a id='n4745' href='#n4745'>4745</a>
<a id='n4746' href='#n4746'>4746</a>
<a id='n4747' href='#n4747'>4747</a>
<a id='n4748' href='#n4748'>4748</a>
<a id='n4749' href='#n4749'>4749</a>
<a id='n4750' href='#n4750'>4750</a>
<a id='n4751' href='#n4751'>4751</a>
<a id='n4752' href='#n4752'>4752</a>
<a id='n4753' href='#n4753'>4753</a>
<a id='n4754' href='#n4754'>4754</a>
<a id='n4755' href='#n4755'>4755</a>
<a id='n4756' href='#n4756'>4756</a>
<a id='n4757' href='#n4757'>4757</a>
<a id='n4758' href='#n4758'>4758</a>
<a id='n4759' href='#n4759'>4759</a>
<a id='n4760' href='#n4760'>4760</a>
<a id='n4761' href='#n4761'>4761</a>
<a id='n4762' href='#n4762'>4762</a>
<a id='n4763' href='#n4763'>4763</a>
<a id='n4764' href='#n4764'>4764</a>
<a id='n4765' href='#n4765'>4765</a>
<a id='n4766' href='#n4766'>4766</a>
<a id='n4767' href='#n4767'>4767</a>
<a id='n4768' href='#n4768'>4768</a>
<a id='n4769' href='#n4769'>4769</a>
<a id='n4770' href='#n4770'>4770</a>
<a id='n4771' href='#n4771'>4771</a>
<a id='n4772' href='#n4772'>4772</a>
<a id='n4773' href='#n4773'>4773</a>
<a id='n4774' href='#n4774'>4774</a>
<a id='n4775' href='#n4775'>4775</a>
<a id='n4776' href='#n4776'>4776</a>
<a id='n4777' href='#n4777'>4777</a>
<a id='n4778' href='#n4778'>4778</a>
<a id='n4779' href='#n4779'>4779</a>
<a id='n4780' href='#n4780'>4780</a>
<a id='n4781' href='#n4781'>4781</a>
<a id='n4782' href='#n4782'>4782</a>
<a id='n4783' href='#n4783'>4783</a>
<a id='n4784' href='#n4784'>4784</a>
<a id='n4785' href='#n4785'>4785</a>
<a id='n4786' href='#n4786'>4786</a>
<a id='n4787' href='#n4787'>4787</a>
<a id='n4788' href='#n4788'>4788</a>
<a id='n4789' href='#n4789'>4789</a>
<a id='n4790' href='#n4790'>4790</a>
<a id='n4791' href='#n4791'>4791</a>
<a id='n4792' href='#n4792'>4792</a>
<a id='n4793' href='#n4793'>4793</a>
<a id='n4794' href='#n4794'>4794</a>
<a id='n4795' href='#n4795'>4795</a>
<a id='n4796' href='#n4796'>4796</a>
<a id='n4797' href='#n4797'>4797</a>
<a id='n4798' href='#n4798'>4798</a>
<a id='n4799' href='#n4799'>4799</a>
<a id='n4800' href='#n4800'>4800</a>
<a id='n4801' href='#n4801'>4801</a>
<a id='n4802' href='#n4802'>4802</a>
<a id='n4803' href='#n4803'>4803</a>
<a id='n4804' href='#n4804'>4804</a>
<a id='n4805' href='#n4805'>4805</a>
<a id='n4806' href='#n4806'>4806</a>
<a id='n4807' href='#n4807'>4807</a>
<a id='n4808' href='#n4808'>4808</a>
<a id='n4809' href='#n4809'>4809</a>
<a id='n4810' href='#n4810'>4810</a>
<a id='n4811' href='#n4811'>4811</a>
<a id='n4812' href='#n4812'>4812</a>
<a id='n4813' href='#n4813'>4813</a>
<a id='n4814' href='#n4814'>4814</a>
<a id='n4815' href='#n4815'>4815</a>
<a id='n4816' href='#n4816'>4816</a>
<a id='n4817' href='#n4817'>4817</a>
<a id='n4818' href='#n4818'>4818</a>
<a id='n4819' href='#n4819'>4819</a>
<a id='n4820' href='#n4820'>4820</a>
<a id='n4821' href='#n4821'>4821</a>
<a id='n4822' href='#n4822'>4822</a>
<a id='n4823' href='#n4823'>4823</a>
<a id='n4824' href='#n4824'>4824</a>
<a id='n4825' href='#n4825'>4825</a>
<a id='n4826' href='#n4826'>4826</a>
<a id='n4827' href='#n4827'>4827</a>
<a id='n4828' href='#n4828'>4828</a>
<a id='n4829' href='#n4829'>4829</a>
<a id='n4830' href='#n4830'>4830</a>
<a id='n4831' href='#n4831'>4831</a>
<a id='n4832' href='#n4832'>4832</a>
<a id='n4833' href='#n4833'>4833</a>
<a id='n4834' href='#n4834'>4834</a>
<a id='n4835' href='#n4835'>4835</a>
<a id='n4836' href='#n4836'>4836</a>
<a id='n4837' href='#n4837'>4837</a>
<a id='n4838' href='#n4838'>4838</a>
<a id='n4839' href='#n4839'>4839</a>
<a id='n4840' href='#n4840'>4840</a>
<a id='n4841' href='#n4841'>4841</a>
<a id='n4842' href='#n4842'>4842</a>
<a id='n4843' href='#n4843'>4843</a>
<a id='n4844' href='#n4844'>4844</a>
<a id='n4845' href='#n4845'>4845</a>
<a id='n4846' href='#n4846'>4846</a>
<a id='n4847' href='#n4847'>4847</a>
<a id='n4848' href='#n4848'>4848</a>
<a id='n4849' href='#n4849'>4849</a>
<a id='n4850' href='#n4850'>4850</a>
<a id='n4851' href='#n4851'>4851</a>
<a id='n4852' href='#n4852'>4852</a>
<a id='n4853' href='#n4853'>4853</a>
<a id='n4854' href='#n4854'>4854</a>
<a id='n4855' href='#n4855'>4855</a>
<a id='n4856' href='#n4856'>4856</a>
<a id='n4857' href='#n4857'>4857</a>
<a id='n4858' href='#n4858'>4858</a>
<a id='n4859' href='#n4859'>4859</a>
<a id='n4860' href='#n4860'>4860</a>
<a id='n4861' href='#n4861'>4861</a>
<a id='n4862' href='#n4862'>4862</a>
<a id='n4863' href='#n4863'>4863</a>
<a id='n4864' href='#n4864'>4864</a>
<a id='n4865' href='#n4865'>4865</a>
<a id='n4866' href='#n4866'>4866</a>
<a id='n4867' href='#n4867'>4867</a>
<a id='n4868' href='#n4868'>4868</a>
<a id='n4869' href='#n4869'>4869</a>
<a id='n4870' href='#n4870'>4870</a>
<a id='n4871' href='#n4871'>4871</a>
<a id='n4872' href='#n4872'>4872</a>
<a id='n4873' href='#n4873'>4873</a>
<a id='n4874' href='#n4874'>4874</a>
<a id='n4875' href='#n4875'>4875</a>
<a id='n4876' href='#n4876'>4876</a>
<a id='n4877' href='#n4877'>4877</a>
<a id='n4878' href='#n4878'>4878</a>
<a id='n4879' href='#n4879'>4879</a>
<a id='n4880' href='#n4880'>4880</a>
<a id='n4881' href='#n4881'>4881</a>
<a id='n4882' href='#n4882'>4882</a>
<a id='n4883' href='#n4883'>4883</a>
<a id='n4884' href='#n4884'>4884</a>
<a id='n4885' href='#n4885'>4885</a>
<a id='n4886' href='#n4886'>4886</a>
<a id='n4887' href='#n4887'>4887</a>
<a id='n4888' href='#n4888'>4888</a>
<a id='n4889' href='#n4889'>4889</a>
<a id='n4890' href='#n4890'>4890</a>
<a id='n4891' href='#n4891'>4891</a>
<a id='n4892' href='#n4892'>4892</a>
<a id='n4893' href='#n4893'>4893</a>
<a id='n4894' href='#n4894'>4894</a>
<a id='n4895' href='#n4895'>4895</a>
<a id='n4896' href='#n4896'>4896</a>
<a id='n4897' href='#n4897'>4897</a>
<a id='n4898' href='#n4898'>4898</a>
<a id='n4899' href='#n4899'>4899</a>
<a id='n4900' href='#n4900'>4900</a>
<a id='n4901' href='#n4901'>4901</a>
<a id='n4902' href='#n4902'>4902</a>
<a id='n4903' href='#n4903'>4903</a>
<a id='n4904' href='#n4904'>4904</a>
<a id='n4905' href='#n4905'>4905</a>
<a id='n4906' href='#n4906'>4906</a>
<a id='n4907' href='#n4907'>4907</a>
<a id='n4908' href='#n4908'>4908</a>
<a id='n4909' href='#n4909'>4909</a>
<a id='n4910' href='#n4910'>4910</a>
<a id='n4911' href='#n4911'>4911</a>
<a id='n4912' href='#n4912'>4912</a>
<a id='n4913' href='#n4913'>4913</a>
<a id='n4914' href='#n4914'>4914</a>
<a id='n4915' href='#n4915'>4915</a>
<a id='n4916' href='#n4916'>4916</a>
<a id='n4917' href='#n4917'>4917</a>
<a id='n4918' href='#n4918'>4918</a>
<a id='n4919' href='#n4919'>4919</a>
<a id='n4920' href='#n4920'>4920</a>
<a id='n4921' href='#n4921'>4921</a>
<a id='n4922' href='#n4922'>4922</a>
<a id='n4923' href='#n4923'>4923</a>
<a id='n4924' href='#n4924'>4924</a>
<a id='n4925' href='#n4925'>4925</a>
<a id='n4926' href='#n4926'>4926</a>
<a id='n4927' href='#n4927'>4927</a>
<a id='n4928' href='#n4928'>4928</a>
<a id='n4929' href='#n4929'>4929</a>
<a id='n4930' href='#n4930'>4930</a>
<a id='n4931' href='#n4931'>4931</a>
<a id='n4932' href='#n4932'>4932</a>
<a id='n4933' href='#n4933'>4933</a>
<a id='n4934' href='#n4934'>4934</a>
<a id='n4935' href='#n4935'>4935</a>
<a id='n4936' href='#n4936'>4936</a>
<a id='n4937' href='#n4937'>4937</a>
<a id='n4938' href='#n4938'>4938</a>
<a id='n4939' href='#n4939'>4939</a>
<a id='n4940' href='#n4940'>4940</a>
<a id='n4941' href='#n4941'>4941</a>
<a id='n4942' href='#n4942'>4942</a>
<a id='n4943' href='#n4943'>4943</a>
<a id='n4944' href='#n4944'>4944</a>
<a id='n4945' href='#n4945'>4945</a>
<a id='n4946' href='#n4946'>4946</a>
<a id='n4947' href='#n4947'>4947</a>
<a id='n4948' href='#n4948'>4948</a>
<a id='n4949' href='#n4949'>4949</a>
<a id='n4950' href='#n4950'>4950</a>
<a id='n4951' href='#n4951'>4951</a>
<a id='n4952' href='#n4952'>4952</a>
<a id='n4953' href='#n4953'>4953</a>
<a id='n4954' href='#n4954'>4954</a>
<a id='n4955' href='#n4955'>4955</a>
<a id='n4956' href='#n4956'>4956</a>
<a id='n4957' href='#n4957'>4957</a>
<a id='n4958' href='#n4958'>4958</a>
<a id='n4959' href='#n4959'>4959</a>
<a id='n4960' href='#n4960'>4960</a>
<a id='n4961' href='#n4961'>4961</a>
<a id='n4962' href='#n4962'>4962</a>
<a id='n4963' href='#n4963'>4963</a>
<a id='n4964' href='#n4964'>4964</a>
<a id='n4965' href='#n4965'>4965</a>
<a id='n4966' href='#n4966'>4966</a>
<a id='n4967' href='#n4967'>4967</a>
<a id='n4968' href='#n4968'>4968</a>
<a id='n4969' href='#n4969'>4969</a>
<a id='n4970' href='#n4970'>4970</a>
<a id='n4971' href='#n4971'>4971</a>
<a id='n4972' href='#n4972'>4972</a>
<a id='n4973' href='#n4973'>4973</a>
<a id='n4974' href='#n4974'>4974</a>
<a id='n4975' href='#n4975'>4975</a>
<a id='n4976' href='#n4976'>4976</a>
<a id='n4977' href='#n4977'>4977</a>
<a id='n4978' href='#n4978'>4978</a>
<a id='n4979' href='#n4979'>4979</a>
<a id='n4980' href='#n4980'>4980</a>
<a id='n4981' href='#n4981'>4981</a>
<a id='n4982' href='#n4982'>4982</a>
<a id='n4983' href='#n4983'>4983</a>
<a id='n4984' href='#n4984'>4984</a>
<a id='n4985' href='#n4985'>4985</a>
<a id='n4986' href='#n4986'>4986</a>
<a id='n4987' href='#n4987'>4987</a>
<a id='n4988' href='#n4988'>4988</a>
<a id='n4989' href='#n4989'>4989</a>
<a id='n4990' href='#n4990'>4990</a>
<a id='n4991' href='#n4991'>4991</a>
<a id='n4992' href='#n4992'>4992</a>
<a id='n4993' href='#n4993'>4993</a>
<a id='n4994' href='#n4994'>4994</a>
<a id='n4995' href='#n4995'>4995</a>
<a id='n4996' href='#n4996'>4996</a>
<a id='n4997' href='#n4997'>4997</a>
<a id='n4998' href='#n4998'>4998</a>
<a id='n4999' href='#n4999'>4999</a>
<a id='n5000' href='#n5000'>5000</a>
<a id='n5001' href='#n5001'>5001</a>
<a id='n5002' href='#n5002'>5002</a>
<a id='n5003' href='#n5003'>5003</a>
<a id='n5004' href='#n5004'>5004</a>
<a id='n5005' href='#n5005'>5005</a>
<a id='n5006' href='#n5006'>5006</a>
<a id='n5007' href='#n5007'>5007</a>
<a id='n5008' href='#n5008'>5008</a>
<a id='n5009' href='#n5009'>5009</a>
<a id='n5010' href='#n5010'>5010</a>
<a id='n5011' href='#n5011'>5011</a>
<a id='n5012' href='#n5012'>5012</a>
<a id='n5013' href='#n5013'>5013</a>
<a id='n5014' href='#n5014'>5014</a>
<a id='n5015' href='#n5015'>5015</a>
<a id='n5016' href='#n5016'>5016</a>
<a id='n5017' href='#n5017'>5017</a>
<a id='n5018' href='#n5018'>5018</a>
<a id='n5019' href='#n5019'>5019</a>
<a id='n5020' href='#n5020'>5020</a>
<a id='n5021' href='#n5021'>5021</a>
<a id='n5022' href='#n5022'>5022</a>
<a id='n5023' href='#n5023'>5023</a>
<a id='n5024' href='#n5024'>5024</a>
<a id='n5025' href='#n5025'>5025</a>
<a id='n5026' href='#n5026'>5026</a>
<a id='n5027' href='#n5027'>5027</a>
<a id='n5028' href='#n5028'>5028</a>
<a id='n5029' href='#n5029'>5029</a>
<a id='n5030' href='#n5030'>5030</a>
<a id='n5031' href='#n5031'>5031</a>
<a id='n5032' href='#n5032'>5032</a>
<a id='n5033' href='#n5033'>5033</a>
<a id='n5034' href='#n5034'>5034</a>
<a id='n5035' href='#n5035'>5035</a>
<a id='n5036' href='#n5036'>5036</a>
<a id='n5037' href='#n5037'>5037</a>
<a id='n5038' href='#n5038'>5038</a>
<a id='n5039' href='#n5039'>5039</a>
<a id='n5040' href='#n5040'>5040</a>
<a id='n5041' href='#n5041'>5041</a>
<a id='n5042' href='#n5042'>5042</a>
<a id='n5043' href='#n5043'>5043</a>
<a id='n5044' href='#n5044'>5044</a>
<a id='n5045' href='#n5045'>5045</a>
<a id='n5046' href='#n5046'>5046</a>
<a id='n5047' href='#n5047'>5047</a>
<a id='n5048' href='#n5048'>5048</a>
<a id='n5049' href='#n5049'>5049</a>
<a id='n5050' href='#n5050'>5050</a>
<a id='n5051' href='#n5051'>5051</a>
<a id='n5052' href='#n5052'>5052</a>
<a id='n5053' href='#n5053'>5053</a>
<a id='n5054' href='#n5054'>5054</a>
<a id='n5055' href='#n5055'>5055</a>
<a id='n5056' href='#n5056'>5056</a>
<a id='n5057' href='#n5057'>5057</a>
<a id='n5058' href='#n5058'>5058</a>
<a id='n5059' href='#n5059'>5059</a>
<a id='n5060' href='#n5060'>5060</a>
<a id='n5061' href='#n5061'>5061</a>
<a id='n5062' href='#n5062'>5062</a>
<a id='n5063' href='#n5063'>5063</a>
<a id='n5064' href='#n5064'>5064</a>
<a id='n5065' href='#n5065'>5065</a>
<a id='n5066' href='#n5066'>5066</a>
<a id='n5067' href='#n5067'>5067</a>
<a id='n5068' href='#n5068'>5068</a>
<a id='n5069' href='#n5069'>5069</a>
<a id='n5070' href='#n5070'>5070</a>
<a id='n5071' href='#n5071'>5071</a>
<a id='n5072' href='#n5072'>5072</a>
<a id='n5073' href='#n5073'>5073</a>
<a id='n5074' href='#n5074'>5074</a>
<a id='n5075' href='#n5075'>5075</a>
<a id='n5076' href='#n5076'>5076</a>
<a id='n5077' href='#n5077'>5077</a>
<a id='n5078' href='#n5078'>5078</a>
<a id='n5079' href='#n5079'>5079</a>
<a id='n5080' href='#n5080'>5080</a>
<a id='n5081' href='#n5081'>5081</a>
<a id='n5082' href='#n5082'>5082</a>
<a id='n5083' href='#n5083'>5083</a>
<a id='n5084' href='#n5084'>5084</a>
<a id='n5085' href='#n5085'>5085</a>
<a id='n5086' href='#n5086'>5086</a>
<a id='n5087' href='#n5087'>5087</a>
<a id='n5088' href='#n5088'>5088</a>
<a id='n5089' href='#n5089'>5089</a>
<a id='n5090' href='#n5090'>5090</a>
<a id='n5091' href='#n5091'>5091</a>
<a id='n5092' href='#n5092'>5092</a>
<a id='n5093' href='#n5093'>5093</a>
<a id='n5094' href='#n5094'>5094</a>
<a id='n5095' href='#n5095'>5095</a>
<a id='n5096' href='#n5096'>5096</a>
<a id='n5097' href='#n5097'>5097</a>
<a id='n5098' href='#n5098'>5098</a>
<a id='n5099' href='#n5099'>5099</a>
<a id='n5100' href='#n5100'>5100</a>
<a id='n5101' href='#n5101'>5101</a>
<a id='n5102' href='#n5102'>5102</a>
<a id='n5103' href='#n5103'>5103</a>
<a id='n5104' href='#n5104'>5104</a>
<a id='n5105' href='#n5105'>5105</a>
<a id='n5106' href='#n5106'>5106</a>
<a id='n5107' href='#n5107'>5107</a>
<a id='n5108' href='#n5108'>5108</a>
<a id='n5109' href='#n5109'>5109</a>
<a id='n5110' href='#n5110'>5110</a>
<a id='n5111' href='#n5111'>5111</a>
<a id='n5112' href='#n5112'>5112</a>
<a id='n5113' href='#n5113'>5113</a>
<a id='n5114' href='#n5114'>5114</a>
<a id='n5115' href='#n5115'>5115</a>
<a id='n5116' href='#n5116'>5116</a>
<a id='n5117' href='#n5117'>5117</a>
<a id='n5118' href='#n5118'>5118</a>
<a id='n5119' href='#n5119'>5119</a>
<a id='n5120' href='#n5120'>5120</a>
<a id='n5121' href='#n5121'>5121</a>
<a id='n5122' href='#n5122'>5122</a>
<a id='n5123' href='#n5123'>5123</a>
<a id='n5124' href='#n5124'>5124</a>
<a id='n5125' href='#n5125'>5125</a>
<a id='n5126' href='#n5126'>5126</a>
<a id='n5127' href='#n5127'>5127</a>
<a id='n5128' href='#n5128'>5128</a>
<a id='n5129' href='#n5129'>5129</a>
<a id='n5130' href='#n5130'>5130</a>
<a id='n5131' href='#n5131'>5131</a>
<a id='n5132' href='#n5132'>5132</a>
<a id='n5133' href='#n5133'>5133</a>
<a id='n5134' href='#n5134'>5134</a>
<a id='n5135' href='#n5135'>5135</a>
<a id='n5136' href='#n5136'>5136</a>
<a id='n5137' href='#n5137'>5137</a>
<a id='n5138' href='#n5138'>5138</a>
<a id='n5139' href='#n5139'>5139</a>
<a id='n5140' href='#n5140'>5140</a>
<a id='n5141' href='#n5141'>5141</a>
<a id='n5142' href='#n5142'>5142</a>
<a id='n5143' href='#n5143'>5143</a>
<a id='n5144' href='#n5144'>5144</a>
<a id='n5145' href='#n5145'>5145</a>
<a id='n5146' href='#n5146'>5146</a>
<a id='n5147' href='#n5147'>5147</a>
<a id='n5148' href='#n5148'>5148</a>
<a id='n5149' href='#n5149'>5149</a>
<a id='n5150' href='#n5150'>5150</a>
<a id='n5151' href='#n5151'>5151</a>
<a id='n5152' href='#n5152'>5152</a>
<a id='n5153' href='#n5153'>5153</a>
<a id='n5154' href='#n5154'>5154</a>
<a id='n5155' href='#n5155'>5155</a>
<a id='n5156' href='#n5156'>5156</a>
<a id='n5157' href='#n5157'>5157</a>
<a id='n5158' href='#n5158'>5158</a>
<a id='n5159' href='#n5159'>5159</a>
<a id='n5160' href='#n5160'>5160</a>
<a id='n5161' href='#n5161'>5161</a>
<a id='n5162' href='#n5162'>5162</a>
<a id='n5163' href='#n5163'>5163</a>
<a id='n5164' href='#n5164'>5164</a>
<a id='n5165' href='#n5165'>5165</a>
<a id='n5166' href='#n5166'>5166</a>
<a id='n5167' href='#n5167'>5167</a>
<a id='n5168' href='#n5168'>5168</a>
<a id='n5169' href='#n5169'>5169</a>
<a id='n5170' href='#n5170'>5170</a>
<a id='n5171' href='#n5171'>5171</a>
<a id='n5172' href='#n5172'>5172</a>
<a id='n5173' href='#n5173'>5173</a>
<a id='n5174' href='#n5174'>5174</a>
<a id='n5175' href='#n5175'>5175</a>
<a id='n5176' href='#n5176'>5176</a>
<a id='n5177' href='#n5177'>5177</a>
<a id='n5178' href='#n5178'>5178</a>
<a id='n5179' href='#n5179'>5179</a>
<a id='n5180' href='#n5180'>5180</a>
<a id='n5181' href='#n5181'>5181</a>
<a id='n5182' href='#n5182'>5182</a>
<a id='n5183' href='#n5183'>5183</a>
<a id='n5184' href='#n5184'>5184</a>
<a id='n5185' href='#n5185'>5185</a>
<a id='n5186' href='#n5186'>5186</a>
<a id='n5187' href='#n5187'>5187</a>
<a id='n5188' href='#n5188'>5188</a>
<a id='n5189' href='#n5189'>5189</a>
<a id='n5190' href='#n5190'>5190</a>
<a id='n5191' href='#n5191'>5191</a>
<a id='n5192' href='#n5192'>5192</a>
<a id='n5193' href='#n5193'>5193</a>
<a id='n5194' href='#n5194'>5194</a>
<a id='n5195' href='#n5195'>5195</a>
<a id='n5196' href='#n5196'>5196</a>
<a id='n5197' href='#n5197'>5197</a>
<a id='n5198' href='#n5198'>5198</a>
<a id='n5199' href='#n5199'>5199</a>
<a id='n5200' href='#n5200'>5200</a>
<a id='n5201' href='#n5201'>5201</a>
<a id='n5202' href='#n5202'>5202</a>
<a id='n5203' href='#n5203'>5203</a>
<a id='n5204' href='#n5204'>5204</a>
<a id='n5205' href='#n5205'>5205</a>
<a id='n5206' href='#n5206'>5206</a>
<a id='n5207' href='#n5207'>5207</a>
<a id='n5208' href='#n5208'>5208</a>
<a id='n5209' href='#n5209'>5209</a>
<a id='n5210' href='#n5210'>5210</a>
<a id='n5211' href='#n5211'>5211</a>
<a id='n5212' href='#n5212'>5212</a>
<a id='n5213' href='#n5213'>5213</a>
<a id='n5214' href='#n5214'>5214</a>
<a id='n5215' href='#n5215'>5215</a>
<a id='n5216' href='#n5216'>5216</a>
<a id='n5217' href='#n5217'>5217</a>
<a id='n5218' href='#n5218'>5218</a>
<a id='n5219' href='#n5219'>5219</a>
<a id='n5220' href='#n5220'>5220</a>
<a id='n5221' href='#n5221'>5221</a>
<a id='n5222' href='#n5222'>5222</a>
<a id='n5223' href='#n5223'>5223</a>
<a id='n5224' href='#n5224'>5224</a>
<a id='n5225' href='#n5225'>5225</a>
<a id='n5226' href='#n5226'>5226</a>
<a id='n5227' href='#n5227'>5227</a>
<a id='n5228' href='#n5228'>5228</a>
<a id='n5229' href='#n5229'>5229</a>
<a id='n5230' href='#n5230'>5230</a>
<a id='n5231' href='#n5231'>5231</a>
<a id='n5232' href='#n5232'>5232</a>
<a id='n5233' href='#n5233'>5233</a>
<a id='n5234' href='#n5234'>5234</a>
<a id='n5235' href='#n5235'>5235</a>
<a id='n5236' href='#n5236'>5236</a>
<a id='n5237' href='#n5237'>5237</a>
<a id='n5238' href='#n5238'>5238</a>
<a id='n5239' href='#n5239'>5239</a>
<a id='n5240' href='#n5240'>5240</a>
<a id='n5241' href='#n5241'>5241</a>
<a id='n5242' href='#n5242'>5242</a>
<a id='n5243' href='#n5243'>5243</a>
<a id='n5244' href='#n5244'>5244</a>
<a id='n5245' href='#n5245'>5245</a>
<a id='n5246' href='#n5246'>5246</a>
<a id='n5247' href='#n5247'>5247</a>
<a id='n5248' href='#n5248'>5248</a>
<a id='n5249' href='#n5249'>5249</a>
<a id='n5250' href='#n5250'>5250</a>
<a id='n5251' href='#n5251'>5251</a>
<a id='n5252' href='#n5252'>5252</a>
<a id='n5253' href='#n5253'>5253</a>
<a id='n5254' href='#n5254'>5254</a>
<a id='n5255' href='#n5255'>5255</a>
<a id='n5256' href='#n5256'>5256</a>
<a id='n5257' href='#n5257'>5257</a>
<a id='n5258' href='#n5258'>5258</a>
<a id='n5259' href='#n5259'>5259</a>
<a id='n5260' href='#n5260'>5260</a>
<a id='n5261' href='#n5261'>5261</a>
<a id='n5262' href='#n5262'>5262</a>
<a id='n5263' href='#n5263'>5263</a>
<a id='n5264' href='#n5264'>5264</a>
<a id='n5265' href='#n5265'>5265</a>
<a id='n5266' href='#n5266'>5266</a>
<a id='n5267' href='#n5267'>5267</a>
<a id='n5268' href='#n5268'>5268</a>
<a id='n5269' href='#n5269'>5269</a>
<a id='n5270' href='#n5270'>5270</a>
<a id='n5271' href='#n5271'>5271</a>
<a id='n5272' href='#n5272'>5272</a>
<a id='n5273' href='#n5273'>5273</a>
<a id='n5274' href='#n5274'>5274</a>
<a id='n5275' href='#n5275'>5275</a>
<a id='n5276' href='#n5276'>5276</a>
<a id='n5277' href='#n5277'>5277</a>
<a id='n5278' href='#n5278'>5278</a>
<a id='n5279' href='#n5279'>5279</a>
<a id='n5280' href='#n5280'>5280</a>
<a id='n5281' href='#n5281'>5281</a>
<a id='n5282' href='#n5282'>5282</a>
<a id='n5283' href='#n5283'>5283</a>
<a id='n5284' href='#n5284'>5284</a>
<a id='n5285' href='#n5285'>5285</a>
<a id='n5286' href='#n5286'>5286</a>
<a id='n5287' href='#n5287'>5287</a>
<a id='n5288' href='#n5288'>5288</a>
<a id='n5289' href='#n5289'>5289</a>
<a id='n5290' href='#n5290'>5290</a>
<a id='n5291' href='#n5291'>5291</a>
<a id='n5292' href='#n5292'>5292</a>
<a id='n5293' href='#n5293'>5293</a>
<a id='n5294' href='#n5294'>5294</a>
<a id='n5295' href='#n5295'>5295</a>
<a id='n5296' href='#n5296'>5296</a>
<a id='n5297' href='#n5297'>5297</a>
<a id='n5298' href='#n5298'>5298</a>
<a id='n5299' href='#n5299'>5299</a>
<a id='n5300' href='#n5300'>5300</a>
<a id='n5301' href='#n5301'>5301</a>
<a id='n5302' href='#n5302'>5302</a>
<a id='n5303' href='#n5303'>5303</a>
<a id='n5304' href='#n5304'>5304</a>
<a id='n5305' href='#n5305'>5305</a>
<a id='n5306' href='#n5306'>5306</a>
<a id='n5307' href='#n5307'>5307</a>
<a id='n5308' href='#n5308'>5308</a>
<a id='n5309' href='#n5309'>5309</a>
<a id='n5310' href='#n5310'>5310</a>
<a id='n5311' href='#n5311'>5311</a>
<a id='n5312' href='#n5312'>5312</a>
<a id='n5313' href='#n5313'>5313</a>
<a id='n5314' href='#n5314'>5314</a>
<a id='n5315' href='#n5315'>5315</a>
<a id='n5316' href='#n5316'>5316</a>
<a id='n5317' href='#n5317'>5317</a>
<a id='n5318' href='#n5318'>5318</a>
<a id='n5319' href='#n5319'>5319</a>
<a id='n5320' href='#n5320'>5320</a>
<a id='n5321' href='#n5321'>5321</a>
<a id='n5322' href='#n5322'>5322</a>
<a id='n5323' href='#n5323'>5323</a>
<a id='n5324' href='#n5324'>5324</a>
<a id='n5325' href='#n5325'>5325</a>
<a id='n5326' href='#n5326'>5326</a>
<a id='n5327' href='#n5327'>5327</a>
<a id='n5328' href='#n5328'>5328</a>
<a id='n5329' href='#n5329'>5329</a>
<a id='n5330' href='#n5330'>5330</a>
<a id='n5331' href='#n5331'>5331</a>
<a id='n5332' href='#n5332'>5332</a>
<a id='n5333' href='#n5333'>5333</a>
<a id='n5334' href='#n5334'>5334</a>
<a id='n5335' href='#n5335'>5335</a>
<a id='n5336' href='#n5336'>5336</a>
<a id='n5337' href='#n5337'>5337</a>
<a id='n5338' href='#n5338'>5338</a>
<a id='n5339' href='#n5339'>5339</a>
<a id='n5340' href='#n5340'>5340</a>
<a id='n5341' href='#n5341'>5341</a>
<a id='n5342' href='#n5342'>5342</a>
<a id='n5343' href='#n5343'>5343</a>
<a id='n5344' href='#n5344'>5344</a>
<a id='n5345' href='#n5345'>5345</a>
<a id='n5346' href='#n5346'>5346</a>
<a id='n5347' href='#n5347'>5347</a>
<a id='n5348' href='#n5348'>5348</a>
<a id='n5349' href='#n5349'>5349</a>
<a id='n5350' href='#n5350'>5350</a>
<a id='n5351' href='#n5351'>5351</a>
<a id='n5352' href='#n5352'>5352</a>
<a id='n5353' href='#n5353'>5353</a>
<a id='n5354' href='#n5354'>5354</a>
<a id='n5355' href='#n5355'>5355</a>
<a id='n5356' href='#n5356'>5356</a>
<a id='n5357' href='#n5357'>5357</a>
<a id='n5358' href='#n5358'>5358</a>
<a id='n5359' href='#n5359'>5359</a>
<a id='n5360' href='#n5360'>5360</a>
<a id='n5361' href='#n5361'>5361</a>
<a id='n5362' href='#n5362'>5362</a>
<a id='n5363' href='#n5363'>5363</a>
<a id='n5364' href='#n5364'>5364</a>
<a id='n5365' href='#n5365'>5365</a>
<a id='n5366' href='#n5366'>5366</a>
<a id='n5367' href='#n5367'>5367</a>
<a id='n5368' href='#n5368'>5368</a>
<a id='n5369' href='#n5369'>5369</a>
<a id='n5370' href='#n5370'>5370</a>
<a id='n5371' href='#n5371'>5371</a>
<a id='n5372' href='#n5372'>5372</a>
<a id='n5373' href='#n5373'>5373</a>
<a id='n5374' href='#n5374'>5374</a>
<a id='n5375' href='#n5375'>5375</a>
<a id='n5376' href='#n5376'>5376</a>
<a id='n5377' href='#n5377'>5377</a>
<a id='n5378' href='#n5378'>5378</a>
<a id='n5379' href='#n5379'>5379</a>
<a id='n5380' href='#n5380'>5380</a>
<a id='n5381' href='#n5381'>5381</a>
<a id='n5382' href='#n5382'>5382</a>
<a id='n5383' href='#n5383'>5383</a>
<a id='n5384' href='#n5384'>5384</a>
<a id='n5385' href='#n5385'>5385</a>
<a id='n5386' href='#n5386'>5386</a>
<a id='n5387' href='#n5387'>5387</a>
<a id='n5388' href='#n5388'>5388</a>
<a id='n5389' href='#n5389'>5389</a>
<a id='n5390' href='#n5390'>5390</a>
<a id='n5391' href='#n5391'>5391</a>
<a id='n5392' href='#n5392'>5392</a>
<a id='n5393' href='#n5393'>5393</a>
<a id='n5394' href='#n5394'>5394</a>
<a id='n5395' href='#n5395'>5395</a>
<a id='n5396' href='#n5396'>5396</a>
<a id='n5397' href='#n5397'>5397</a>
<a id='n5398' href='#n5398'>5398</a>
<a id='n5399' href='#n5399'>5399</a>
<a id='n5400' href='#n5400'>5400</a>
<a id='n5401' href='#n5401'>5401</a>
<a id='n5402' href='#n5402'>5402</a>
<a id='n5403' href='#n5403'>5403</a>
<a id='n5404' href='#n5404'>5404</a>
<a id='n5405' href='#n5405'>5405</a>
<a id='n5406' href='#n5406'>5406</a>
<a id='n5407' href='#n5407'>5407</a>
<a id='n5408' href='#n5408'>5408</a>
<a id='n5409' href='#n5409'>5409</a>
<a id='n5410' href='#n5410'>5410</a>
<a id='n5411' href='#n5411'>5411</a>
<a id='n5412' href='#n5412'>5412</a>
<a id='n5413' href='#n5413'>5413</a>
<a id='n5414' href='#n5414'>5414</a>
<a id='n5415' href='#n5415'>5415</a>
<a id='n5416' href='#n5416'>5416</a>
<a id='n5417' href='#n5417'>5417</a>
<a id='n5418' href='#n5418'>5418</a>
<a id='n5419' href='#n5419'>5419</a>
<a id='n5420' href='#n5420'>5420</a>
<a id='n5421' href='#n5421'>5421</a>
<a id='n5422' href='#n5422'>5422</a>
<a id='n5423' href='#n5423'>5423</a>
<a id='n5424' href='#n5424'>5424</a>
<a id='n5425' href='#n5425'>5425</a>
<a id='n5426' href='#n5426'>5426</a>
<a id='n5427' href='#n5427'>5427</a>
<a id='n5428' href='#n5428'>5428</a>
<a id='n5429' href='#n5429'>5429</a>
<a id='n5430' href='#n5430'>5430</a>
<a id='n5431' href='#n5431'>5431</a>
<a id='n5432' href='#n5432'>5432</a>
<a id='n5433' href='#n5433'>5433</a>
<a id='n5434' href='#n5434'>5434</a>
<a id='n5435' href='#n5435'>5435</a>
<a id='n5436' href='#n5436'>5436</a>
<a id='n5437' href='#n5437'>5437</a>
<a id='n5438' href='#n5438'>5438</a>
<a id='n5439' href='#n5439'>5439</a>
<a id='n5440' href='#n5440'>5440</a>
<a id='n5441' href='#n5441'>5441</a>
<a id='n5442' href='#n5442'>5442</a>
<a id='n5443' href='#n5443'>5443</a>
<a id='n5444' href='#n5444'>5444</a>
<a id='n5445' href='#n5445'>5445</a>
<a id='n5446' href='#n5446'>5446</a>
<a id='n5447' href='#n5447'>5447</a>
<a id='n5448' href='#n5448'>5448</a>
<a id='n5449' href='#n5449'>5449</a>
<a id='n5450' href='#n5450'>5450</a>
<a id='n5451' href='#n5451'>5451</a>
<a id='n5452' href='#n5452'>5452</a>
<a id='n5453' href='#n5453'>5453</a>
<a id='n5454' href='#n5454'>5454</a>
<a id='n5455' href='#n5455'>5455</a>
<a id='n5456' href='#n5456'>5456</a>
<a id='n5457' href='#n5457'>5457</a>
<a id='n5458' href='#n5458'>5458</a>
<a id='n5459' href='#n5459'>5459</a>
<a id='n5460' href='#n5460'>5460</a>
<a id='n5461' href='#n5461'>5461</a>
<a id='n5462' href='#n5462'>5462</a>
<a id='n5463' href='#n5463'>5463</a>
<a id='n5464' href='#n5464'>5464</a>
<a id='n5465' href='#n5465'>5465</a>
<a id='n5466' href='#n5466'>5466</a>
<a id='n5467' href='#n5467'>5467</a>
<a id='n5468' href='#n5468'>5468</a>
<a id='n5469' href='#n5469'>5469</a>
<a id='n5470' href='#n5470'>5470</a>
<a id='n5471' href='#n5471'>5471</a>
<a id='n5472' href='#n5472'>5472</a>
<a id='n5473' href='#n5473'>5473</a>
<a id='n5474' href='#n5474'>5474</a>
<a id='n5475' href='#n5475'>5475</a>
<a id='n5476' href='#n5476'>5476</a>
<a id='n5477' href='#n5477'>5477</a>
<a id='n5478' href='#n5478'>5478</a>
<a id='n5479' href='#n5479'>5479</a>
<a id='n5480' href='#n5480'>5480</a>
<a id='n5481' href='#n5481'>5481</a>
<a id='n5482' href='#n5482'>5482</a>
<a id='n5483' href='#n5483'>5483</a>
<a id='n5484' href='#n5484'>5484</a>
<a id='n5485' href='#n5485'>5485</a>
<a id='n5486' href='#n5486'>5486</a>
<a id='n5487' href='#n5487'>5487</a>
<a id='n5488' href='#n5488'>5488</a>
<a id='n5489' href='#n5489'>5489</a>
<a id='n5490' href='#n5490'>5490</a>
<a id='n5491' href='#n5491'>5491</a>
<a id='n5492' href='#n5492'>5492</a>
<a id='n5493' href='#n5493'>5493</a>
<a id='n5494' href='#n5494'>5494</a>
<a id='n5495' href='#n5495'>5495</a>
<a id='n5496' href='#n5496'>5496</a>
<a id='n5497' href='#n5497'>5497</a>
<a id='n5498' href='#n5498'>5498</a>
<a id='n5499' href='#n5499'>5499</a>
<a id='n5500' href='#n5500'>5500</a>
<a id='n5501' href='#n5501'>5501</a>
<a id='n5502' href='#n5502'>5502</a>
<a id='n5503' href='#n5503'>5503</a>
<a id='n5504' href='#n5504'>5504</a>
<a id='n5505' href='#n5505'>5505</a>
<a id='n5506' href='#n5506'>5506</a>
<a id='n5507' href='#n5507'>5507</a>
<a id='n5508' href='#n5508'>5508</a>
<a id='n5509' href='#n5509'>5509</a>
<a id='n5510' href='#n5510'>5510</a>
<a id='n5511' href='#n5511'>5511</a>
<a id='n5512' href='#n5512'>5512</a>
<a id='n5513' href='#n5513'>5513</a>
<a id='n5514' href='#n5514'>5514</a>
<a id='n5515' href='#n5515'>5515</a>
<a id='n5516' href='#n5516'>5516</a>
<a id='n5517' href='#n5517'>5517</a>
<a id='n5518' href='#n5518'>5518</a>
<a id='n5519' href='#n5519'>5519</a>
<a id='n5520' href='#n5520'>5520</a>
<a id='n5521' href='#n5521'>5521</a>
<a id='n5522' href='#n5522'>5522</a>
<a id='n5523' href='#n5523'>5523</a>
<a id='n5524' href='#n5524'>5524</a>
<a id='n5525' href='#n5525'>5525</a>
<a id='n5526' href='#n5526'>5526</a>
<a id='n5527' href='#n5527'>5527</a>
<a id='n5528' href='#n5528'>5528</a>
<a id='n5529' href='#n5529'>5529</a>
<a id='n5530' href='#n5530'>5530</a>
<a id='n5531' href='#n5531'>5531</a>
<a id='n5532' href='#n5532'>5532</a>
<a id='n5533' href='#n5533'>5533</a>
<a id='n5534' href='#n5534'>5534</a>
<a id='n5535' href='#n5535'>5535</a>
<a id='n5536' href='#n5536'>5536</a>
<a id='n5537' href='#n5537'>5537</a>
<a id='n5538' href='#n5538'>5538</a>
<a id='n5539' href='#n5539'>5539</a>
<a id='n5540' href='#n5540'>5540</a>
<a id='n5541' href='#n5541'>5541</a>
<a id='n5542' href='#n5542'>5542</a>
<a id='n5543' href='#n5543'>5543</a>
<a id='n5544' href='#n5544'>5544</a>
<a id='n5545' href='#n5545'>5545</a>
<a id='n5546' href='#n5546'>5546</a>
<a id='n5547' href='#n5547'>5547</a>
<a id='n5548' href='#n5548'>5548</a>
<a id='n5549' href='#n5549'>5549</a>
<a id='n5550' href='#n5550'>5550</a>
<a id='n5551' href='#n5551'>5551</a>
<a id='n5552' href='#n5552'>5552</a>
<a id='n5553' href='#n5553'>5553</a>
<a id='n5554' href='#n5554'>5554</a>
<a id='n5555' href='#n5555'>5555</a>
<a id='n5556' href='#n5556'>5556</a>
<a id='n5557' href='#n5557'>5557</a>
<a id='n5558' href='#n5558'>5558</a>
<a id='n5559' href='#n5559'>5559</a>
<a id='n5560' href='#n5560'>5560</a>
<a id='n5561' href='#n5561'>5561</a>
<a id='n5562' href='#n5562'>5562</a>
<a id='n5563' href='#n5563'>5563</a>
<a id='n5564' href='#n5564'>5564</a>
<a id='n5565' href='#n5565'>5565</a>
<a id='n5566' href='#n5566'>5566</a>
<a id='n5567' href='#n5567'>5567</a>
<a id='n5568' href='#n5568'>5568</a>
<a id='n5569' href='#n5569'>5569</a>
<a id='n5570' href='#n5570'>5570</a>
<a id='n5571' href='#n5571'>5571</a>
<a id='n5572' href='#n5572'>5572</a>
<a id='n5573' href='#n5573'>5573</a>
<a id='n5574' href='#n5574'>5574</a>
<a id='n5575' href='#n5575'>5575</a>
<a id='n5576' href='#n5576'>5576</a>
<a id='n5577' href='#n5577'>5577</a>
<a id='n5578' href='#n5578'>5578</a>
<a id='n5579' href='#n5579'>5579</a>
<a id='n5580' href='#n5580'>5580</a>
<a id='n5581' href='#n5581'>5581</a>
<a id='n5582' href='#n5582'>5582</a>
<a id='n5583' href='#n5583'>5583</a>
<a id='n5584' href='#n5584'>5584</a>
<a id='n5585' href='#n5585'>5585</a>
<a id='n5586' href='#n5586'>5586</a>
<a id='n5587' href='#n5587'>5587</a>
<a id='n5588' href='#n5588'>5588</a>
<a id='n5589' href='#n5589'>5589</a>
<a id='n5590' href='#n5590'>5590</a>
<a id='n5591' href='#n5591'>5591</a>
<a id='n5592' href='#n5592'>5592</a>
<a id='n5593' href='#n5593'>5593</a>
<a id='n5594' href='#n5594'>5594</a>
<a id='n5595' href='#n5595'>5595</a>
<a id='n5596' href='#n5596'>5596</a>
<a id='n5597' href='#n5597'>5597</a>
<a id='n5598' href='#n5598'>5598</a>
<a id='n5599' href='#n5599'>5599</a>
<a id='n5600' href='#n5600'>5600</a>
<a id='n5601' href='#n5601'>5601</a>
<a id='n5602' href='#n5602'>5602</a>
<a id='n5603' href='#n5603'>5603</a>
<a id='n5604' href='#n5604'>5604</a>
<a id='n5605' href='#n5605'>5605</a>
<a id='n5606' href='#n5606'>5606</a>
<a id='n5607' href='#n5607'>5607</a>
<a id='n5608' href='#n5608'>5608</a>
<a id='n5609' href='#n5609'>5609</a>
<a id='n5610' href='#n5610'>5610</a>
<a id='n5611' href='#n5611'>5611</a>
<a id='n5612' href='#n5612'>5612</a>
<a id='n5613' href='#n5613'>5613</a>
<a id='n5614' href='#n5614'>5614</a>
<a id='n5615' href='#n5615'>5615</a>
<a id='n5616' href='#n5616'>5616</a>
<a id='n5617' href='#n5617'>5617</a>
<a id='n5618' href='#n5618'>5618</a>
<a id='n5619' href='#n5619'>5619</a>
<a id='n5620' href='#n5620'>5620</a>
<a id='n5621' href='#n5621'>5621</a>
<a id='n5622' href='#n5622'>5622</a>
<a id='n5623' href='#n5623'>5623</a>
<a id='n5624' href='#n5624'>5624</a>
<a id='n5625' href='#n5625'>5625</a>
<a id='n5626' href='#n5626'>5626</a>
<a id='n5627' href='#n5627'>5627</a>
<a id='n5628' href='#n5628'>5628</a>
<a id='n5629' href='#n5629'>5629</a>
<a id='n5630' href='#n5630'>5630</a>
<a id='n5631' href='#n5631'>5631</a>
<a id='n5632' href='#n5632'>5632</a>
<a id='n5633' href='#n5633'>5633</a>
<a id='n5634' href='#n5634'>5634</a>
<a id='n5635' href='#n5635'>5635</a>
<a id='n5636' href='#n5636'>5636</a>
<a id='n5637' href='#n5637'>5637</a>
<a id='n5638' href='#n5638'>5638</a>
<a id='n5639' href='#n5639'>5639</a>
<a id='n5640' href='#n5640'>5640</a>
<a id='n5641' href='#n5641'>5641</a>
<a id='n5642' href='#n5642'>5642</a>
<a id='n5643' href='#n5643'>5643</a>
<a id='n5644' href='#n5644'>5644</a>
<a id='n5645' href='#n5645'>5645</a>
<a id='n5646' href='#n5646'>5646</a>
<a id='n5647' href='#n5647'>5647</a>
<a id='n5648' href='#n5648'>5648</a>
<a id='n5649' href='#n5649'>5649</a>
<a id='n5650' href='#n5650'>5650</a>
<a id='n5651' href='#n5651'>5651</a>
<a id='n5652' href='#n5652'>5652</a>
<a id='n5653' href='#n5653'>5653</a>
<a id='n5654' href='#n5654'>5654</a>
<a id='n5655' href='#n5655'>5655</a>
<a id='n5656' href='#n5656'>5656</a>
<a id='n5657' href='#n5657'>5657</a>
<a id='n5658' href='#n5658'>5658</a>
<a id='n5659' href='#n5659'>5659</a>
<a id='n5660' href='#n5660'>5660</a>
<a id='n5661' href='#n5661'>5661</a>
<a id='n5662' href='#n5662'>5662</a>
<a id='n5663' href='#n5663'>5663</a>
<a id='n5664' href='#n5664'>5664</a>
<a id='n5665' href='#n5665'>5665</a>
<a id='n5666' href='#n5666'>5666</a>
<a id='n5667' href='#n5667'>5667</a>
<a id='n5668' href='#n5668'>5668</a>
<a id='n5669' href='#n5669'>5669</a>
<a id='n5670' href='#n5670'>5670</a>
<a id='n5671' href='#n5671'>5671</a>
<a id='n5672' href='#n5672'>5672</a>
<a id='n5673' href='#n5673'>5673</a>
<a id='n5674' href='#n5674'>5674</a>
<a id='n5675' href='#n5675'>5675</a>
<a id='n5676' href='#n5676'>5676</a>
<a id='n5677' href='#n5677'>5677</a>
<a id='n5678' href='#n5678'>5678</a>
<a id='n5679' href='#n5679'>5679</a>
<a id='n5680' href='#n5680'>5680</a>
<a id='n5681' href='#n5681'>5681</a>
<a id='n5682' href='#n5682'>5682</a>
<a id='n5683' href='#n5683'>5683</a>
<a id='n5684' href='#n5684'>5684</a>
<a id='n5685' href='#n5685'>5685</a>
<a id='n5686' href='#n5686'>5686</a>
<a id='n5687' href='#n5687'>5687</a>
<a id='n5688' href='#n5688'>5688</a>
<a id='n5689' href='#n5689'>5689</a>
<a id='n5690' href='#n5690'>5690</a>
<a id='n5691' href='#n5691'>5691</a>
<a id='n5692' href='#n5692'>5692</a>
<a id='n5693' href='#n5693'>5693</a>
<a id='n5694' href='#n5694'>5694</a>
<a id='n5695' href='#n5695'>5695</a>
<a id='n5696' href='#n5696'>5696</a>
<a id='n5697' href='#n5697'>5697</a>
<a id='n5698' href='#n5698'>5698</a>
<a id='n5699' href='#n5699'>5699</a>
<a id='n5700' href='#n5700'>5700</a>
<a id='n5701' href='#n5701'>5701</a>
<a id='n5702' href='#n5702'>5702</a>
<a id='n5703' href='#n5703'>5703</a>
<a id='n5704' href='#n5704'>5704</a>
<a id='n5705' href='#n5705'>5705</a>
<a id='n5706' href='#n5706'>5706</a>
<a id='n5707' href='#n5707'>5707</a>
<a id='n5708' href='#n5708'>5708</a>
<a id='n5709' href='#n5709'>5709</a>
<a id='n5710' href='#n5710'>5710</a>
<a id='n5711' href='#n5711'>5711</a>
<a id='n5712' href='#n5712'>5712</a>
<a id='n5713' href='#n5713'>5713</a>
<a id='n5714' href='#n5714'>5714</a>
<a id='n5715' href='#n5715'>5715</a>
<a id='n5716' href='#n5716'>5716</a>
<a id='n5717' href='#n5717'>5717</a>
<a id='n5718' href='#n5718'>5718</a>
<a id='n5719' href='#n5719'>5719</a>
<a id='n5720' href='#n5720'>5720</a>
<a id='n5721' href='#n5721'>5721</a>
<a id='n5722' href='#n5722'>5722</a>
<a id='n5723' href='#n5723'>5723</a>
<a id='n5724' href='#n5724'>5724</a>
<a id='n5725' href='#n5725'>5725</a>
<a id='n5726' href='#n5726'>5726</a>
<a id='n5727' href='#n5727'>5727</a>
<a id='n5728' href='#n5728'>5728</a>
<a id='n5729' href='#n5729'>5729</a>
<a id='n5730' href='#n5730'>5730</a>
<a id='n5731' href='#n5731'>5731</a>
<a id='n5732' href='#n5732'>5732</a>
<a id='n5733' href='#n5733'>5733</a>
<a id='n5734' href='#n5734'>5734</a>
<a id='n5735' href='#n5735'>5735</a>
<a id='n5736' href='#n5736'>5736</a>
<a id='n5737' href='#n5737'>5737</a>
<a id='n5738' href='#n5738'>5738</a>
<a id='n5739' href='#n5739'>5739</a>
<a id='n5740' href='#n5740'>5740</a>
<a id='n5741' href='#n5741'>5741</a>
<a id='n5742' href='#n5742'>5742</a>
<a id='n5743' href='#n5743'>5743</a>
<a id='n5744' href='#n5744'>5744</a>
<a id='n5745' href='#n5745'>5745</a>
<a id='n5746' href='#n5746'>5746</a>
<a id='n5747' href='#n5747'>5747</a>
<a id='n5748' href='#n5748'>5748</a>
<a id='n5749' href='#n5749'>5749</a>
<a id='n5750' href='#n5750'>5750</a>
<a id='n5751' href='#n5751'>5751</a>
<a id='n5752' href='#n5752'>5752</a>
<a id='n5753' href='#n5753'>5753</a>
<a id='n5754' href='#n5754'>5754</a>
<a id='n5755' href='#n5755'>5755</a>
<a id='n5756' href='#n5756'>5756</a>
<a id='n5757' href='#n5757'>5757</a>
<a id='n5758' href='#n5758'>5758</a>
<a id='n5759' href='#n5759'>5759</a>
<a id='n5760' href='#n5760'>5760</a>
<a id='n5761' href='#n5761'>5761</a>
<a id='n5762' href='#n5762'>5762</a>
<a id='n5763' href='#n5763'>5763</a>
<a id='n5764' href='#n5764'>5764</a>
<a id='n5765' href='#n5765'>5765</a>
<a id='n5766' href='#n5766'>5766</a>
<a id='n5767' href='#n5767'>5767</a>
<a id='n5768' href='#n5768'>5768</a>
<a id='n5769' href='#n5769'>5769</a>
<a id='n5770' href='#n5770'>5770</a>
<a id='n5771' href='#n5771'>5771</a>
<a id='n5772' href='#n5772'>5772</a>
<a id='n5773' href='#n5773'>5773</a>
<a id='n5774' href='#n5774'>5774</a>
<a id='n5775' href='#n5775'>5775</a>
<a id='n5776' href='#n5776'>5776</a>
<a id='n5777' href='#n5777'>5777</a>
<a id='n5778' href='#n5778'>5778</a>
<a id='n5779' href='#n5779'>5779</a>
<a id='n5780' href='#n5780'>5780</a>
<a id='n5781' href='#n5781'>5781</a>
<a id='n5782' href='#n5782'>5782</a>
<a id='n5783' href='#n5783'>5783</a>
<a id='n5784' href='#n5784'>5784</a>
<a id='n5785' href='#n5785'>5785</a>
<a id='n5786' href='#n5786'>5786</a>
<a id='n5787' href='#n5787'>5787</a>
<a id='n5788' href='#n5788'>5788</a>
<a id='n5789' href='#n5789'>5789</a>
<a id='n5790' href='#n5790'>5790</a>
<a id='n5791' href='#n5791'>5791</a>
<a id='n5792' href='#n5792'>5792</a>
<a id='n5793' href='#n5793'>5793</a>
<a id='n5794' href='#n5794'>5794</a>
<a id='n5795' href='#n5795'>5795</a>
<a id='n5796' href='#n5796'>5796</a>
<a id='n5797' href='#n5797'>5797</a>
<a id='n5798' href='#n5798'>5798</a>
<a id='n5799' href='#n5799'>5799</a>
<a id='n5800' href='#n5800'>5800</a>
<a id='n5801' href='#n5801'>5801</a>
<a id='n5802' href='#n5802'>5802</a>
<a id='n5803' href='#n5803'>5803</a>
<a id='n5804' href='#n5804'>5804</a>
<a id='n5805' href='#n5805'>5805</a>
<a id='n5806' href='#n5806'>5806</a>
<a id='n5807' href='#n5807'>5807</a>
<a id='n5808' href='#n5808'>5808</a>
<a id='n5809' href='#n5809'>5809</a>
<a id='n5810' href='#n5810'>5810</a>
<a id='n5811' href='#n5811'>5811</a>
<a id='n5812' href='#n5812'>5812</a>
<a id='n5813' href='#n5813'>5813</a>
<a id='n5814' href='#n5814'>5814</a>
<a id='n5815' href='#n5815'>5815</a>
<a id='n5816' href='#n5816'>5816</a>
<a id='n5817' href='#n5817'>5817</a>
<a id='n5818' href='#n5818'>5818</a>
<a id='n5819' href='#n5819'>5819</a>
<a id='n5820' href='#n5820'>5820</a>
<a id='n5821' href='#n5821'>5821</a>
<a id='n5822' href='#n5822'>5822</a>
<a id='n5823' href='#n5823'>5823</a>
<a id='n5824' href='#n5824'>5824</a>
<a id='n5825' href='#n5825'>5825</a>
<a id='n5826' href='#n5826'>5826</a>
<a id='n5827' href='#n5827'>5827</a>
<a id='n5828' href='#n5828'>5828</a>
<a id='n5829' href='#n5829'>5829</a>
<a id='n5830' href='#n5830'>5830</a>
<a id='n5831' href='#n5831'>5831</a>
<a id='n5832' href='#n5832'>5832</a>
<a id='n5833' href='#n5833'>5833</a>
<a id='n5834' href='#n5834'>5834</a>
<a id='n5835' href='#n5835'>5835</a>
<a id='n5836' href='#n5836'>5836</a>
<a id='n5837' href='#n5837'>5837</a>
<a id='n5838' href='#n5838'>5838</a>
<a id='n5839' href='#n5839'>5839</a>
<a id='n5840' href='#n5840'>5840</a>
<a id='n5841' href='#n5841'>5841</a>
<a id='n5842' href='#n5842'>5842</a>
<a id='n5843' href='#n5843'>5843</a>
<a id='n5844' href='#n5844'>5844</a>
<a id='n5845' href='#n5845'>5845</a>
<a id='n5846' href='#n5846'>5846</a>
<a id='n5847' href='#n5847'>5847</a>
<a id='n5848' href='#n5848'>5848</a>
<a id='n5849' href='#n5849'>5849</a>
<a id='n5850' href='#n5850'>5850</a>
<a id='n5851' href='#n5851'>5851</a>
<a id='n5852' href='#n5852'>5852</a>
<a id='n5853' href='#n5853'>5853</a>
<a id='n5854' href='#n5854'>5854</a>
<a id='n5855' href='#n5855'>5855</a>
<a id='n5856' href='#n5856'>5856</a>
<a id='n5857' href='#n5857'>5857</a>
<a id='n5858' href='#n5858'>5858</a>
<a id='n5859' href='#n5859'>5859</a>
<a id='n5860' href='#n5860'>5860</a>
<a id='n5861' href='#n5861'>5861</a>
<a id='n5862' href='#n5862'>5862</a>
<a id='n5863' href='#n5863'>5863</a>
<a id='n5864' href='#n5864'>5864</a>
<a id='n5865' href='#n5865'>5865</a>
<a id='n5866' href='#n5866'>5866</a>
<a id='n5867' href='#n5867'>5867</a>
<a id='n5868' href='#n5868'>5868</a>
<a id='n5869' href='#n5869'>5869</a>
<a id='n5870' href='#n5870'>5870</a>
<a id='n5871' href='#n5871'>5871</a>
<a id='n5872' href='#n5872'>5872</a>
<a id='n5873' href='#n5873'>5873</a>
<a id='n5874' href='#n5874'>5874</a>
<a id='n5875' href='#n5875'>5875</a>
<a id='n5876' href='#n5876'>5876</a>
<a id='n5877' href='#n5877'>5877</a>
<a id='n5878' href='#n5878'>5878</a>
<a id='n5879' href='#n5879'>5879</a>
<a id='n5880' href='#n5880'>5880</a>
<a id='n5881' href='#n5881'>5881</a>
<a id='n5882' href='#n5882'>5882</a>
<a id='n5883' href='#n5883'>5883</a>
<a id='n5884' href='#n5884'>5884</a>
<a id='n5885' href='#n5885'>5885</a>
<a id='n5886' href='#n5886'>5886</a>
<a id='n5887' href='#n5887'>5887</a>
<a id='n5888' href='#n5888'>5888</a>
<a id='n5889' href='#n5889'>5889</a>
<a id='n5890' href='#n5890'>5890</a>
<a id='n5891' href='#n5891'>5891</a>
<a id='n5892' href='#n5892'>5892</a>
<a id='n5893' href='#n5893'>5893</a>
<a id='n5894' href='#n5894'>5894</a>
<a id='n5895' href='#n5895'>5895</a>
<a id='n5896' href='#n5896'>5896</a>
<a id='n5897' href='#n5897'>5897</a>
<a id='n5898' href='#n5898'>5898</a>
<a id='n5899' href='#n5899'>5899</a>
<a id='n5900' href='#n5900'>5900</a>
<a id='n5901' href='#n5901'>5901</a>
<a id='n5902' href='#n5902'>5902</a>
<a id='n5903' href='#n5903'>5903</a>
<a id='n5904' href='#n5904'>5904</a>
<a id='n5905' href='#n5905'>5905</a>
<a id='n5906' href='#n5906'>5906</a>
<a id='n5907' href='#n5907'>5907</a>
<a id='n5908' href='#n5908'>5908</a>
<a id='n5909' href='#n5909'>5909</a>
<a id='n5910' href='#n5910'>5910</a>
<a id='n5911' href='#n5911'>5911</a>
<a id='n5912' href='#n5912'>5912</a>
<a id='n5913' href='#n5913'>5913</a>
<a id='n5914' href='#n5914'>5914</a>
<a id='n5915' href='#n5915'>5915</a>
<a id='n5916' href='#n5916'>5916</a>
<a id='n5917' href='#n5917'>5917</a>
<a id='n5918' href='#n5918'>5918</a>
<a id='n5919' href='#n5919'>5919</a>
<a id='n5920' href='#n5920'>5920</a>
<a id='n5921' href='#n5921'>5921</a>
<a id='n5922' href='#n5922'>5922</a>
<a id='n5923' href='#n5923'>5923</a>
<a id='n5924' href='#n5924'>5924</a>
<a id='n5925' href='#n5925'>5925</a>
<a id='n5926' href='#n5926'>5926</a>
<a id='n5927' href='#n5927'>5927</a>
<a id='n5928' href='#n5928'>5928</a>
<a id='n5929' href='#n5929'>5929</a>
<a id='n5930' href='#n5930'>5930</a>
<a id='n5931' href='#n5931'>5931</a>
<a id='n5932' href='#n5932'>5932</a>
<a id='n5933' href='#n5933'>5933</a>
<a id='n5934' href='#n5934'>5934</a>
<a id='n5935' href='#n5935'>5935</a>
<a id='n5936' href='#n5936'>5936</a>
<a id='n5937' href='#n5937'>5937</a>
<a id='n5938' href='#n5938'>5938</a>
<a id='n5939' href='#n5939'>5939</a>
<a id='n5940' href='#n5940'>5940</a>
<a id='n5941' href='#n5941'>5941</a>
<a id='n5942' href='#n5942'>5942</a>
<a id='n5943' href='#n5943'>5943</a>
<a id='n5944' href='#n5944'>5944</a>
<a id='n5945' href='#n5945'>5945</a>
<a id='n5946' href='#n5946'>5946</a>
<a id='n5947' href='#n5947'>5947</a>
<a id='n5948' href='#n5948'>5948</a>
<a id='n5949' href='#n5949'>5949</a>
<a id='n5950' href='#n5950'>5950</a>
<a id='n5951' href='#n5951'>5951</a>
<a id='n5952' href='#n5952'>5952</a>
<a id='n5953' href='#n5953'>5953</a>
<a id='n5954' href='#n5954'>5954</a>
<a id='n5955' href='#n5955'>5955</a>
<a id='n5956' href='#n5956'>5956</a>
<a id='n5957' href='#n5957'>5957</a>
<a id='n5958' href='#n5958'>5958</a>
<a id='n5959' href='#n5959'>5959</a>
<a id='n5960' href='#n5960'>5960</a>
<a id='n5961' href='#n5961'>5961</a>
<a id='n5962' href='#n5962'>5962</a>
<a id='n5963' href='#n5963'>5963</a>
<a id='n5964' href='#n5964'>5964</a>
<a id='n5965' href='#n5965'>5965</a>
<a id='n5966' href='#n5966'>5966</a>
<a id='n5967' href='#n5967'>5967</a>
<a id='n5968' href='#n5968'>5968</a>
<a id='n5969' href='#n5969'>5969</a>
<a id='n5970' href='#n5970'>5970</a>
<a id='n5971' href='#n5971'>5971</a>
<a id='n5972' href='#n5972'>5972</a>
<a id='n5973' href='#n5973'>5973</a>
<a id='n5974' href='#n5974'>5974</a>
<a id='n5975' href='#n5975'>5975</a>
<a id='n5976' href='#n5976'>5976</a>
<a id='n5977' href='#n5977'>5977</a>
<a id='n5978' href='#n5978'>5978</a>
<a id='n5979' href='#n5979'>5979</a>
<a id='n5980' href='#n5980'>5980</a>
<a id='n5981' href='#n5981'>5981</a>
<a id='n5982' href='#n5982'>5982</a>
<a id='n5983' href='#n5983'>5983</a>
<a id='n5984' href='#n5984'>5984</a>
<a id='n5985' href='#n5985'>5985</a>
<a id='n5986' href='#n5986'>5986</a>
<a id='n5987' href='#n5987'>5987</a>
<a id='n5988' href='#n5988'>5988</a>
<a id='n5989' href='#n5989'>5989</a>
<a id='n5990' href='#n5990'>5990</a>
<a id='n5991' href='#n5991'>5991</a>
<a id='n5992' href='#n5992'>5992</a>
<a id='n5993' href='#n5993'>5993</a>
<a id='n5994' href='#n5994'>5994</a>
<a id='n5995' href='#n5995'>5995</a>
<a id='n5996' href='#n5996'>5996</a>
<a id='n5997' href='#n5997'>5997</a>
<a id='n5998' href='#n5998'>5998</a>
<a id='n5999' href='#n5999'>5999</a>
<a id='n6000' href='#n6000'>6000</a>
<a id='n6001' href='#n6001'>6001</a>
<a id='n6002' href='#n6002'>6002</a>
<a id='n6003' href='#n6003'>6003</a>
<a id='n6004' href='#n6004'>6004</a>
<a id='n6005' href='#n6005'>6005</a>
<a id='n6006' href='#n6006'>6006</a>
<a id='n6007' href='#n6007'>6007</a>
<a id='n6008' href='#n6008'>6008</a>
<a id='n6009' href='#n6009'>6009</a>
<a id='n6010' href='#n6010'>6010</a>
<a id='n6011' href='#n6011'>6011</a>
<a id='n6012' href='#n6012'>6012</a>
<a id='n6013' href='#n6013'>6013</a>
<a id='n6014' href='#n6014'>6014</a>
<a id='n6015' href='#n6015'>6015</a>
<a id='n6016' href='#n6016'>6016</a>
<a id='n6017' href='#n6017'>6017</a>
<a id='n6018' href='#n6018'>6018</a>
<a id='n6019' href='#n6019'>6019</a>
<a id='n6020' href='#n6020'>6020</a>
<a id='n6021' href='#n6021'>6021</a>
<a id='n6022' href='#n6022'>6022</a>
<a id='n6023' href='#n6023'>6023</a>
<a id='n6024' href='#n6024'>6024</a>
<a id='n6025' href='#n6025'>6025</a>
<a id='n6026' href='#n6026'>6026</a>
<a id='n6027' href='#n6027'>6027</a>
<a id='n6028' href='#n6028'>6028</a>
<a id='n6029' href='#n6029'>6029</a>
<a id='n6030' href='#n6030'>6030</a>
<a id='n6031' href='#n6031'>6031</a>
<a id='n6032' href='#n6032'>6032</a>
<a id='n6033' href='#n6033'>6033</a>
<a id='n6034' href='#n6034'>6034</a>
<a id='n6035' href='#n6035'>6035</a>
<a id='n6036' href='#n6036'>6036</a>
<a id='n6037' href='#n6037'>6037</a>
<a id='n6038' href='#n6038'>6038</a>
<a id='n6039' href='#n6039'>6039</a>
<a id='n6040' href='#n6040'>6040</a>
<a id='n6041' href='#n6041'>6041</a>
<a id='n6042' href='#n6042'>6042</a>
<a id='n6043' href='#n6043'>6043</a>
<a id='n6044' href='#n6044'>6044</a>
<a id='n6045' href='#n6045'>6045</a>
<a id='n6046' href='#n6046'>6046</a>
<a id='n6047' href='#n6047'>6047</a>
<a id='n6048' href='#n6048'>6048</a>
<a id='n6049' href='#n6049'>6049</a>
<a id='n6050' href='#n6050'>6050</a>
<a id='n6051' href='#n6051'>6051</a>
<a id='n6052' href='#n6052'>6052</a>
<a id='n6053' href='#n6053'>6053</a>
<a id='n6054' href='#n6054'>6054</a>
<a id='n6055' href='#n6055'>6055</a>
<a id='n6056' href='#n6056'>6056</a>
<a id='n6057' href='#n6057'>6057</a>
<a id='n6058' href='#n6058'>6058</a>
<a id='n6059' href='#n6059'>6059</a>
<a id='n6060' href='#n6060'>6060</a>
<a id='n6061' href='#n6061'>6061</a>
<a id='n6062' href='#n6062'>6062</a>
<a id='n6063' href='#n6063'>6063</a>
<a id='n6064' href='#n6064'>6064</a>
<a id='n6065' href='#n6065'>6065</a>
<a id='n6066' href='#n6066'>6066</a>
<a id='n6067' href='#n6067'>6067</a>
<a id='n6068' href='#n6068'>6068</a>
<a id='n6069' href='#n6069'>6069</a>
<a id='n6070' href='#n6070'>6070</a>
<a id='n6071' href='#n6071'>6071</a>
<a id='n6072' href='#n6072'>6072</a>
<a id='n6073' href='#n6073'>6073</a>
<a id='n6074' href='#n6074'>6074</a>
<a id='n6075' href='#n6075'>6075</a>
<a id='n6076' href='#n6076'>6076</a>
<a id='n6077' href='#n6077'>6077</a>
<a id='n6078' href='#n6078'>6078</a>
<a id='n6079' href='#n6079'>6079</a>
<a id='n6080' href='#n6080'>6080</a>
<a id='n6081' href='#n6081'>6081</a>
<a id='n6082' href='#n6082'>6082</a>
<a id='n6083' href='#n6083'>6083</a>
<a id='n6084' href='#n6084'>6084</a>
<a id='n6085' href='#n6085'>6085</a>
<a id='n6086' href='#n6086'>6086</a>
<a id='n6087' href='#n6087'>6087</a>
<a id='n6088' href='#n6088'>6088</a>
<a id='n6089' href='#n6089'>6089</a>
<a id='n6090' href='#n6090'>6090</a>
<a id='n6091' href='#n6091'>6091</a>
<a id='n6092' href='#n6092'>6092</a>
<a id='n6093' href='#n6093'>6093</a>
<a id='n6094' href='#n6094'>6094</a>
<a id='n6095' href='#n6095'>6095</a>
<a id='n6096' href='#n6096'>6096</a>
<a id='n6097' href='#n6097'>6097</a>
<a id='n6098' href='#n6098'>6098</a>
<a id='n6099' href='#n6099'>6099</a>
<a id='n6100' href='#n6100'>6100</a>
<a id='n6101' href='#n6101'>6101</a>
<a id='n6102' href='#n6102'>6102</a>
<a id='n6103' href='#n6103'>6103</a>
<a id='n6104' href='#n6104'>6104</a>
<a id='n6105' href='#n6105'>6105</a>
<a id='n6106' href='#n6106'>6106</a>
<a id='n6107' href='#n6107'>6107</a>
<a id='n6108' href='#n6108'>6108</a>
<a id='n6109' href='#n6109'>6109</a>
<a id='n6110' href='#n6110'>6110</a>
<a id='n6111' href='#n6111'>6111</a>
<a id='n6112' href='#n6112'>6112</a>
<a id='n6113' href='#n6113'>6113</a>
<a id='n6114' href='#n6114'>6114</a>
<a id='n6115' href='#n6115'>6115</a>
<a id='n6116' href='#n6116'>6116</a>
<a id='n6117' href='#n6117'>6117</a>
<a id='n6118' href='#n6118'>6118</a>
<a id='n6119' href='#n6119'>6119</a>
<a id='n6120' href='#n6120'>6120</a>
<a id='n6121' href='#n6121'>6121</a>
<a id='n6122' href='#n6122'>6122</a>
<a id='n6123' href='#n6123'>6123</a>
<a id='n6124' href='#n6124'>6124</a>
<a id='n6125' href='#n6125'>6125</a>
<a id='n6126' href='#n6126'>6126</a>
<a id='n6127' href='#n6127'>6127</a>
<a id='n6128' href='#n6128'>6128</a>
<a id='n6129' href='#n6129'>6129</a>
<a id='n6130' href='#n6130'>6130</a>
<a id='n6131' href='#n6131'>6131</a>
<a id='n6132' href='#n6132'>6132</a>
<a id='n6133' href='#n6133'>6133</a>
<a id='n6134' href='#n6134'>6134</a>
<a id='n6135' href='#n6135'>6135</a>
<a id='n6136' href='#n6136'>6136</a>
<a id='n6137' href='#n6137'>6137</a>
<a id='n6138' href='#n6138'>6138</a>
<a id='n6139' href='#n6139'>6139</a>
<a id='n6140' href='#n6140'>6140</a>
<a id='n6141' href='#n6141'>6141</a>
<a id='n6142' href='#n6142'>6142</a>
<a id='n6143' href='#n6143'>6143</a>
<a id='n6144' href='#n6144'>6144</a>
<a id='n6145' href='#n6145'>6145</a>
<a id='n6146' href='#n6146'>6146</a>
<a id='n6147' href='#n6147'>6147</a>
<a id='n6148' href='#n6148'>6148</a>
<a id='n6149' href='#n6149'>6149</a>
<a id='n6150' href='#n6150'>6150</a>
<a id='n6151' href='#n6151'>6151</a>
<a id='n6152' href='#n6152'>6152</a>
<a id='n6153' href='#n6153'>6153</a>
<a id='n6154' href='#n6154'>6154</a>
<a id='n6155' href='#n6155'>6155</a>
<a id='n6156' href='#n6156'>6156</a>
<a id='n6157' href='#n6157'>6157</a>
<a id='n6158' href='#n6158'>6158</a>
<a id='n6159' href='#n6159'>6159</a>
<a id='n6160' href='#n6160'>6160</a>
<a id='n6161' href='#n6161'>6161</a>
<a id='n6162' href='#n6162'>6162</a>
<a id='n6163' href='#n6163'>6163</a>
<a id='n6164' href='#n6164'>6164</a>
<a id='n6165' href='#n6165'>6165</a>
<a id='n6166' href='#n6166'>6166</a>
<a id='n6167' href='#n6167'>6167</a>
<a id='n6168' href='#n6168'>6168</a>
<a id='n6169' href='#n6169'>6169</a>
<a id='n6170' href='#n6170'>6170</a>
<a id='n6171' href='#n6171'>6171</a>
<a id='n6172' href='#n6172'>6172</a>
<a id='n6173' href='#n6173'>6173</a>
<a id='n6174' href='#n6174'>6174</a>
<a id='n6175' href='#n6175'>6175</a>
<a id='n6176' href='#n6176'>6176</a>
<a id='n6177' href='#n6177'>6177</a>
<a id='n6178' href='#n6178'>6178</a>
<a id='n6179' href='#n6179'>6179</a>
<a id='n6180' href='#n6180'>6180</a>
<a id='n6181' href='#n6181'>6181</a>
<a id='n6182' href='#n6182'>6182</a>
<a id='n6183' href='#n6183'>6183</a>
<a id='n6184' href='#n6184'>6184</a>
<a id='n6185' href='#n6185'>6185</a>
<a id='n6186' href='#n6186'>6186</a>
<a id='n6187' href='#n6187'>6187</a>
<a id='n6188' href='#n6188'>6188</a>
<a id='n6189' href='#n6189'>6189</a>
<a id='n6190' href='#n6190'>6190</a>
<a id='n6191' href='#n6191'>6191</a>
<a id='n6192' href='#n6192'>6192</a>
<a id='n6193' href='#n6193'>6193</a>
<a id='n6194' href='#n6194'>6194</a>
<a id='n6195' href='#n6195'>6195</a>
<a id='n6196' href='#n6196'>6196</a>
<a id='n6197' href='#n6197'>6197</a>
<a id='n6198' href='#n6198'>6198</a>
<a id='n6199' href='#n6199'>6199</a>
<a id='n6200' href='#n6200'>6200</a>
<a id='n6201' href='#n6201'>6201</a>
<a id='n6202' href='#n6202'>6202</a>
<a id='n6203' href='#n6203'>6203</a>
<a id='n6204' href='#n6204'>6204</a>
<a id='n6205' href='#n6205'>6205</a>
<a id='n6206' href='#n6206'>6206</a>
<a id='n6207' href='#n6207'>6207</a>
<a id='n6208' href='#n6208'>6208</a>
<a id='n6209' href='#n6209'>6209</a>
<a id='n6210' href='#n6210'>6210</a>
<a id='n6211' href='#n6211'>6211</a>
<a id='n6212' href='#n6212'>6212</a>
<a id='n6213' href='#n6213'>6213</a>
<a id='n6214' href='#n6214'>6214</a>
<a id='n6215' href='#n6215'>6215</a>
<a id='n6216' href='#n6216'>6216</a>
<a id='n6217' href='#n6217'>6217</a>
<a id='n6218' href='#n6218'>6218</a>
<a id='n6219' href='#n6219'>6219</a>
<a id='n6220' href='#n6220'>6220</a>
<a id='n6221' href='#n6221'>6221</a>
<a id='n6222' href='#n6222'>6222</a>
<a id='n6223' href='#n6223'>6223</a>
<a id='n6224' href='#n6224'>6224</a>
<a id='n6225' href='#n6225'>6225</a>
<a id='n6226' href='#n6226'>6226</a>
<a id='n6227' href='#n6227'>6227</a>
<a id='n6228' href='#n6228'>6228</a>
<a id='n6229' href='#n6229'>6229</a>
<a id='n6230' href='#n6230'>6230</a>
<a id='n6231' href='#n6231'>6231</a>
<a id='n6232' href='#n6232'>6232</a>
<a id='n6233' href='#n6233'>6233</a>
<a id='n6234' href='#n6234'>6234</a>
<a id='n6235' href='#n6235'>6235</a>
<a id='n6236' href='#n6236'>6236</a>
<a id='n6237' href='#n6237'>6237</a>
<a id='n6238' href='#n6238'>6238</a>
<a id='n6239' href='#n6239'>6239</a>
<a id='n6240' href='#n6240'>6240</a>
<a id='n6241' href='#n6241'>6241</a>
<a id='n6242' href='#n6242'>6242</a>
<a id='n6243' href='#n6243'>6243</a>
<a id='n6244' href='#n6244'>6244</a>
<a id='n6245' href='#n6245'>6245</a>
<a id='n6246' href='#n6246'>6246</a>
<a id='n6247' href='#n6247'>6247</a>
<a id='n6248' href='#n6248'>6248</a>
<a id='n6249' href='#n6249'>6249</a>
<a id='n6250' href='#n6250'>6250</a>
<a id='n6251' href='#n6251'>6251</a>
<a id='n6252' href='#n6252'>6252</a>
<a id='n6253' href='#n6253'>6253</a>
<a id='n6254' href='#n6254'>6254</a>
<a id='n6255' href='#n6255'>6255</a>
<a id='n6256' href='#n6256'>6256</a>
<a id='n6257' href='#n6257'>6257</a>
<a id='n6258' href='#n6258'>6258</a>
<a id='n6259' href='#n6259'>6259</a>
<a id='n6260' href='#n6260'>6260</a>
<a id='n6261' href='#n6261'>6261</a>
<a id='n6262' href='#n6262'>6262</a>
<a id='n6263' href='#n6263'>6263</a>
<a id='n6264' href='#n6264'>6264</a>
<a id='n6265' href='#n6265'>6265</a>
<a id='n6266' href='#n6266'>6266</a>
<a id='n6267' href='#n6267'>6267</a>
<a id='n6268' href='#n6268'>6268</a>
<a id='n6269' href='#n6269'>6269</a>
<a id='n6270' href='#n6270'>6270</a>
<a id='n6271' href='#n6271'>6271</a>
<a id='n6272' href='#n6272'>6272</a>
<a id='n6273' href='#n6273'>6273</a>
<a id='n6274' href='#n6274'>6274</a>
<a id='n6275' href='#n6275'>6275</a>
<a id='n6276' href='#n6276'>6276</a>
<a id='n6277' href='#n6277'>6277</a>
<a id='n6278' href='#n6278'>6278</a>
<a id='n6279' href='#n6279'>6279</a>
<a id='n6280' href='#n6280'>6280</a>
<a id='n6281' href='#n6281'>6281</a>
<a id='n6282' href='#n6282'>6282</a>
<a id='n6283' href='#n6283'>6283</a>
<a id='n6284' href='#n6284'>6284</a>
<a id='n6285' href='#n6285'>6285</a>
<a id='n6286' href='#n6286'>6286</a>
<a id='n6287' href='#n6287'>6287</a>
<a id='n6288' href='#n6288'>6288</a>
<a id='n6289' href='#n6289'>6289</a>
<a id='n6290' href='#n6290'>6290</a>
<a id='n6291' href='#n6291'>6291</a>
<a id='n6292' href='#n6292'>6292</a>
<a id='n6293' href='#n6293'>6293</a>
<a id='n6294' href='#n6294'>6294</a>
<a id='n6295' href='#n6295'>6295</a>
<a id='n6296' href='#n6296'>6296</a>
<a id='n6297' href='#n6297'>6297</a>
<a id='n6298' href='#n6298'>6298</a>
<a id='n6299' href='#n6299'>6299</a>
<a id='n6300' href='#n6300'>6300</a>
<a id='n6301' href='#n6301'>6301</a>
<a id='n6302' href='#n6302'>6302</a>
<a id='n6303' href='#n6303'>6303</a>
<a id='n6304' href='#n6304'>6304</a>
<a id='n6305' href='#n6305'>6305</a>
<a id='n6306' href='#n6306'>6306</a>
<a id='n6307' href='#n6307'>6307</a>
<a id='n6308' href='#n6308'>6308</a>
<a id='n6309' href='#n6309'>6309</a>
<a id='n6310' href='#n6310'>6310</a>
<a id='n6311' href='#n6311'>6311</a>
<a id='n6312' href='#n6312'>6312</a>
<a id='n6313' href='#n6313'>6313</a>
<a id='n6314' href='#n6314'>6314</a>
<a id='n6315' href='#n6315'>6315</a>
<a id='n6316' href='#n6316'>6316</a>
<a id='n6317' href='#n6317'>6317</a>
<a id='n6318' href='#n6318'>6318</a>
<a id='n6319' href='#n6319'>6319</a>
<a id='n6320' href='#n6320'>6320</a>
<a id='n6321' href='#n6321'>6321</a>
<a id='n6322' href='#n6322'>6322</a>
<a id='n6323' href='#n6323'>6323</a>
<a id='n6324' href='#n6324'>6324</a>
<a id='n6325' href='#n6325'>6325</a>
<a id='n6326' href='#n6326'>6326</a>
<a id='n6327' href='#n6327'>6327</a>
<a id='n6328' href='#n6328'>6328</a>
<a id='n6329' href='#n6329'>6329</a>
<a id='n6330' href='#n6330'>6330</a>
<a id='n6331' href='#n6331'>6331</a>
<a id='n6332' href='#n6332'>6332</a>
<a id='n6333' href='#n6333'>6333</a>
<a id='n6334' href='#n6334'>6334</a>
<a id='n6335' href='#n6335'>6335</a>
<a id='n6336' href='#n6336'>6336</a>
<a id='n6337' href='#n6337'>6337</a>
<a id='n6338' href='#n6338'>6338</a>
<a id='n6339' href='#n6339'>6339</a>
<a id='n6340' href='#n6340'>6340</a>
<a id='n6341' href='#n6341'>6341</a>
<a id='n6342' href='#n6342'>6342</a>
<a id='n6343' href='#n6343'>6343</a>
<a id='n6344' href='#n6344'>6344</a>
<a id='n6345' href='#n6345'>6345</a>
<a id='n6346' href='#n6346'>6346</a>
<a id='n6347' href='#n6347'>6347</a>
<a id='n6348' href='#n6348'>6348</a>
<a id='n6349' href='#n6349'>6349</a>
<a id='n6350' href='#n6350'>6350</a>
<a id='n6351' href='#n6351'>6351</a>
<a id='n6352' href='#n6352'>6352</a>
<a id='n6353' href='#n6353'>6353</a>
<a id='n6354' href='#n6354'>6354</a>
<a id='n6355' href='#n6355'>6355</a>
<a id='n6356' href='#n6356'>6356</a>
<a id='n6357' href='#n6357'>6357</a>
<a id='n6358' href='#n6358'>6358</a>
<a id='n6359' href='#n6359'>6359</a>
<a id='n6360' href='#n6360'>6360</a>
<a id='n6361' href='#n6361'>6361</a>
<a id='n6362' href='#n6362'>6362</a>
<a id='n6363' href='#n6363'>6363</a>
<a id='n6364' href='#n6364'>6364</a>
<a id='n6365' href='#n6365'>6365</a>
<a id='n6366' href='#n6366'>6366</a>
<a id='n6367' href='#n6367'>6367</a>
<a id='n6368' href='#n6368'>6368</a>
<a id='n6369' href='#n6369'>6369</a>
<a id='n6370' href='#n6370'>6370</a>
<a id='n6371' href='#n6371'>6371</a>
<a id='n6372' href='#n6372'>6372</a>
<a id='n6373' href='#n6373'>6373</a>
<a id='n6374' href='#n6374'>6374</a>
<a id='n6375' href='#n6375'>6375</a>
<a id='n6376' href='#n6376'>6376</a>
<a id='n6377' href='#n6377'>6377</a>
<a id='n6378' href='#n6378'>6378</a>
<a id='n6379' href='#n6379'>6379</a>
<a id='n6380' href='#n6380'>6380</a>
<a id='n6381' href='#n6381'>6381</a>
<a id='n6382' href='#n6382'>6382</a>
<a id='n6383' href='#n6383'>6383</a>
<a id='n6384' href='#n6384'>6384</a>
<a id='n6385' href='#n6385'>6385</a>
<a id='n6386' href='#n6386'>6386</a>
<a id='n6387' href='#n6387'>6387</a>
<a id='n6388' href='#n6388'>6388</a>
<a id='n6389' href='#n6389'>6389</a>
<a id='n6390' href='#n6390'>6390</a>
<a id='n6391' href='#n6391'>6391</a>
<a id='n6392' href='#n6392'>6392</a>
<a id='n6393' href='#n6393'>6393</a>
<a id='n6394' href='#n6394'>6394</a>
<a id='n6395' href='#n6395'>6395</a>
<a id='n6396' href='#n6396'>6396</a>
<a id='n6397' href='#n6397'>6397</a>
<a id='n6398' href='#n6398'>6398</a>
<a id='n6399' href='#n6399'>6399</a>
<a id='n6400' href='#n6400'>6400</a>
<a id='n6401' href='#n6401'>6401</a>
<a id='n6402' href='#n6402'>6402</a>
<a id='n6403' href='#n6403'>6403</a>
<a id='n6404' href='#n6404'>6404</a>
<a id='n6405' href='#n6405'>6405</a>
<a id='n6406' href='#n6406'>6406</a>
<a id='n6407' href='#n6407'>6407</a>
<a id='n6408' href='#n6408'>6408</a>
<a id='n6409' href='#n6409'>6409</a>
<a id='n6410' href='#n6410'>6410</a>
<a id='n6411' href='#n6411'>6411</a>
<a id='n6412' href='#n6412'>6412</a>
<a id='n6413' href='#n6413'>6413</a>
<a id='n6414' href='#n6414'>6414</a>
<a id='n6415' href='#n6415'>6415</a>
<a id='n6416' href='#n6416'>6416</a>
<a id='n6417' href='#n6417'>6417</a>
<a id='n6418' href='#n6418'>6418</a>
<a id='n6419' href='#n6419'>6419</a>
<a id='n6420' href='#n6420'>6420</a>
<a id='n6421' href='#n6421'>6421</a>
<a id='n6422' href='#n6422'>6422</a>
<a id='n6423' href='#n6423'>6423</a>
<a id='n6424' href='#n6424'>6424</a>
<a id='n6425' href='#n6425'>6425</a>
<a id='n6426' href='#n6426'>6426</a>
<a id='n6427' href='#n6427'>6427</a>
<a id='n6428' href='#n6428'>6428</a>
<a id='n6429' href='#n6429'>6429</a>
<a id='n6430' href='#n6430'>6430</a>
<a id='n6431' href='#n6431'>6431</a>
<a id='n6432' href='#n6432'>6432</a>
<a id='n6433' href='#n6433'>6433</a>
<a id='n6434' href='#n6434'>6434</a>
<a id='n6435' href='#n6435'>6435</a>
<a id='n6436' href='#n6436'>6436</a>
<a id='n6437' href='#n6437'>6437</a>
<a id='n6438' href='#n6438'>6438</a>
<a id='n6439' href='#n6439'>6439</a>
<a id='n6440' href='#n6440'>6440</a>
<a id='n6441' href='#n6441'>6441</a>
<a id='n6442' href='#n6442'>6442</a>
<a id='n6443' href='#n6443'>6443</a>
<a id='n6444' href='#n6444'>6444</a>
<a id='n6445' href='#n6445'>6445</a>
<a id='n6446' href='#n6446'>6446</a>
<a id='n6447' href='#n6447'>6447</a>
<a id='n6448' href='#n6448'>6448</a>
<a id='n6449' href='#n6449'>6449</a>
<a id='n6450' href='#n6450'>6450</a>
<a id='n6451' href='#n6451'>6451</a>
<a id='n6452' href='#n6452'>6452</a>
<a id='n6453' href='#n6453'>6453</a>
<a id='n6454' href='#n6454'>6454</a>
<a id='n6455' href='#n6455'>6455</a>
<a id='n6456' href='#n6456'>6456</a>
<a id='n6457' href='#n6457'>6457</a>
<a id='n6458' href='#n6458'>6458</a>
<a id='n6459' href='#n6459'>6459</a>
<a id='n6460' href='#n6460'>6460</a>
<a id='n6461' href='#n6461'>6461</a>
<a id='n6462' href='#n6462'>6462</a>
<a id='n6463' href='#n6463'>6463</a>
<a id='n6464' href='#n6464'>6464</a>
<a id='n6465' href='#n6465'>6465</a>
<a id='n6466' href='#n6466'>6466</a>
<a id='n6467' href='#n6467'>6467</a>
<a id='n6468' href='#n6468'>6468</a>
<a id='n6469' href='#n6469'>6469</a>
<a id='n6470' href='#n6470'>6470</a>
<a id='n6471' href='#n6471'>6471</a>
<a id='n6472' href='#n6472'>6472</a>
<a id='n6473' href='#n6473'>6473</a>
<a id='n6474' href='#n6474'>6474</a>
<a id='n6475' href='#n6475'>6475</a>
<a id='n6476' href='#n6476'>6476</a>
<a id='n6477' href='#n6477'>6477</a>
<a id='n6478' href='#n6478'>6478</a>
<a id='n6479' href='#n6479'>6479</a>
<a id='n6480' href='#n6480'>6480</a>
<a id='n6481' href='#n6481'>6481</a>
<a id='n6482' href='#n6482'>6482</a>
<a id='n6483' href='#n6483'>6483</a>
<a id='n6484' href='#n6484'>6484</a>
<a id='n6485' href='#n6485'>6485</a>
<a id='n6486' href='#n6486'>6486</a>
<a id='n6487' href='#n6487'>6487</a>
<a id='n6488' href='#n6488'>6488</a>
<a id='n6489' href='#n6489'>6489</a>
<a id='n6490' href='#n6490'>6490</a>
<a id='n6491' href='#n6491'>6491</a>
<a id='n6492' href='#n6492'>6492</a>
<a id='n6493' href='#n6493'>6493</a>
<a id='n6494' href='#n6494'>6494</a>
<a id='n6495' href='#n6495'>6495</a>
<a id='n6496' href='#n6496'>6496</a>
<a id='n6497' href='#n6497'>6497</a>
<a id='n6498' href='#n6498'>6498</a>
<a id='n6499' href='#n6499'>6499</a>
<a id='n6500' href='#n6500'>6500</a>
<a id='n6501' href='#n6501'>6501</a>
<a id='n6502' href='#n6502'>6502</a>
<a id='n6503' href='#n6503'>6503</a>
<a id='n6504' href='#n6504'>6504</a>
<a id='n6505' href='#n6505'>6505</a>
<a id='n6506' href='#n6506'>6506</a>
<a id='n6507' href='#n6507'>6507</a>
<a id='n6508' href='#n6508'>6508</a>
<a id='n6509' href='#n6509'>6509</a>
<a id='n6510' href='#n6510'>6510</a>
<a id='n6511' href='#n6511'>6511</a>
<a id='n6512' href='#n6512'>6512</a>
<a id='n6513' href='#n6513'>6513</a>
<a id='n6514' href='#n6514'>6514</a>
<a id='n6515' href='#n6515'>6515</a>
<a id='n6516' href='#n6516'>6516</a>
<a id='n6517' href='#n6517'>6517</a>
<a id='n6518' href='#n6518'>6518</a>
<a id='n6519' href='#n6519'>6519</a>
<a id='n6520' href='#n6520'>6520</a>
<a id='n6521' href='#n6521'>6521</a>
<a id='n6522' href='#n6522'>6522</a>
<a id='n6523' href='#n6523'>6523</a>
<a id='n6524' href='#n6524'>6524</a>
<a id='n6525' href='#n6525'>6525</a>
<a id='n6526' href='#n6526'>6526</a>
<a id='n6527' href='#n6527'>6527</a>
<a id='n6528' href='#n6528'>6528</a>
<a id='n6529' href='#n6529'>6529</a>
<a id='n6530' href='#n6530'>6530</a>
<a id='n6531' href='#n6531'>6531</a>
<a id='n6532' href='#n6532'>6532</a>
<a id='n6533' href='#n6533'>6533</a>
<a id='n6534' href='#n6534'>6534</a>
<a id='n6535' href='#n6535'>6535</a>
<a id='n6536' href='#n6536'>6536</a>
<a id='n6537' href='#n6537'>6537</a>
<a id='n6538' href='#n6538'>6538</a>
<a id='n6539' href='#n6539'>6539</a>
<a id='n6540' href='#n6540'>6540</a>
<a id='n6541' href='#n6541'>6541</a>
<a id='n6542' href='#n6542'>6542</a>
<a id='n6543' href='#n6543'>6543</a>
<a id='n6544' href='#n6544'>6544</a>
<a id='n6545' href='#n6545'>6545</a>
<a id='n6546' href='#n6546'>6546</a>
<a id='n6547' href='#n6547'>6547</a>
<a id='n6548' href='#n6548'>6548</a>
<a id='n6549' href='#n6549'>6549</a>
<a id='n6550' href='#n6550'>6550</a>
<a id='n6551' href='#n6551'>6551</a>
<a id='n6552' href='#n6552'>6552</a>
<a id='n6553' href='#n6553'>6553</a>
<a id='n6554' href='#n6554'>6554</a>
<a id='n6555' href='#n6555'>6555</a>
<a id='n6556' href='#n6556'>6556</a>
<a id='n6557' href='#n6557'>6557</a>
<a id='n6558' href='#n6558'>6558</a>
<a id='n6559' href='#n6559'>6559</a>
<a id='n6560' href='#n6560'>6560</a>
<a id='n6561' href='#n6561'>6561</a>
<a id='n6562' href='#n6562'>6562</a>
<a id='n6563' href='#n6563'>6563</a>
<a id='n6564' href='#n6564'>6564</a>
<a id='n6565' href='#n6565'>6565</a>
<a id='n6566' href='#n6566'>6566</a>
<a id='n6567' href='#n6567'>6567</a>
<a id='n6568' href='#n6568'>6568</a>
<a id='n6569' href='#n6569'>6569</a>
<a id='n6570' href='#n6570'>6570</a>
<a id='n6571' href='#n6571'>6571</a>
<a id='n6572' href='#n6572'>6572</a>
<a id='n6573' href='#n6573'>6573</a>
<a id='n6574' href='#n6574'>6574</a>
<a id='n6575' href='#n6575'>6575</a>
<a id='n6576' href='#n6576'>6576</a>
<a id='n6577' href='#n6577'>6577</a>
<a id='n6578' href='#n6578'>6578</a>
<a id='n6579' href='#n6579'>6579</a>
<a id='n6580' href='#n6580'>6580</a>
<a id='n6581' href='#n6581'>6581</a>
<a id='n6582' href='#n6582'>6582</a>
<a id='n6583' href='#n6583'>6583</a>
<a id='n6584' href='#n6584'>6584</a>
<a id='n6585' href='#n6585'>6585</a>
<a id='n6586' href='#n6586'>6586</a>
<a id='n6587' href='#n6587'>6587</a>
<a id='n6588' href='#n6588'>6588</a>
<a id='n6589' href='#n6589'>6589</a>
<a id='n6590' href='#n6590'>6590</a>
<a id='n6591' href='#n6591'>6591</a>
<a id='n6592' href='#n6592'>6592</a>
<a id='n6593' href='#n6593'>6593</a>
<a id='n6594' href='#n6594'>6594</a>
<a id='n6595' href='#n6595'>6595</a>
<a id='n6596' href='#n6596'>6596</a>
<a id='n6597' href='#n6597'>6597</a>
<a id='n6598' href='#n6598'>6598</a>
<a id='n6599' href='#n6599'>6599</a>
<a id='n6600' href='#n6600'>6600</a>
<a id='n6601' href='#n6601'>6601</a>
<a id='n6602' href='#n6602'>6602</a>
<a id='n6603' href='#n6603'>6603</a>
<a id='n6604' href='#n6604'>6604</a>
<a id='n6605' href='#n6605'>6605</a>
<a id='n6606' href='#n6606'>6606</a>
<a id='n6607' href='#n6607'>6607</a>
<a id='n6608' href='#n6608'>6608</a>
<a id='n6609' href='#n6609'>6609</a>
<a id='n6610' href='#n6610'>6610</a>
<a id='n6611' href='#n6611'>6611</a>
<a id='n6612' href='#n6612'>6612</a>
<a id='n6613' href='#n6613'>6613</a>
<a id='n6614' href='#n6614'>6614</a>
<a id='n6615' href='#n6615'>6615</a>
<a id='n6616' href='#n6616'>6616</a>
<a id='n6617' href='#n6617'>6617</a>
<a id='n6618' href='#n6618'>6618</a>
<a id='n6619' href='#n6619'>6619</a>
<a id='n6620' href='#n6620'>6620</a>
<a id='n6621' href='#n6621'>6621</a>
<a id='n6622' href='#n6622'>6622</a>
<a id='n6623' href='#n6623'>6623</a>
<a id='n6624' href='#n6624'>6624</a>
<a id='n6625' href='#n6625'>6625</a>
<a id='n6626' href='#n6626'>6626</a>
<a id='n6627' href='#n6627'>6627</a>
<a id='n6628' href='#n6628'>6628</a>
<a id='n6629' href='#n6629'>6629</a>
<a id='n6630' href='#n6630'>6630</a>
<a id='n6631' href='#n6631'>6631</a>
<a id='n6632' href='#n6632'>6632</a>
<a id='n6633' href='#n6633'>6633</a>
<a id='n6634' href='#n6634'>6634</a>
<a id='n6635' href='#n6635'>6635</a>
<a id='n6636' href='#n6636'>6636</a>
<a id='n6637' href='#n6637'>6637</a>
<a id='n6638' href='#n6638'>6638</a>
<a id='n6639' href='#n6639'>6639</a>
<a id='n6640' href='#n6640'>6640</a>
<a id='n6641' href='#n6641'>6641</a>
<a id='n6642' href='#n6642'>6642</a>
<a id='n6643' href='#n6643'>6643</a>
<a id='n6644' href='#n6644'>6644</a>
<a id='n6645' href='#n6645'>6645</a>
<a id='n6646' href='#n6646'>6646</a>
<a id='n6647' href='#n6647'>6647</a>
<a id='n6648' href='#n6648'>6648</a>
<a id='n6649' href='#n6649'>6649</a>
<a id='n6650' href='#n6650'>6650</a>
<a id='n6651' href='#n6651'>6651</a>
<a id='n6652' href='#n6652'>6652</a>
<a id='n6653' href='#n6653'>6653</a>
<a id='n6654' href='#n6654'>6654</a>
<a id='n6655' href='#n6655'>6655</a>
<a id='n6656' href='#n6656'>6656</a>
<a id='n6657' href='#n6657'>6657</a>
<a id='n6658' href='#n6658'>6658</a>
<a id='n6659' href='#n6659'>6659</a>
<a id='n6660' href='#n6660'>6660</a>
<a id='n6661' href='#n6661'>6661</a>
<a id='n6662' href='#n6662'>6662</a>
<a id='n6663' href='#n6663'>6663</a>
<a id='n6664' href='#n6664'>6664</a>
<a id='n6665' href='#n6665'>6665</a>
<a id='n6666' href='#n6666'>6666</a>
<a id='n6667' href='#n6667'>6667</a>
<a id='n6668' href='#n6668'>6668</a>
<a id='n6669' href='#n6669'>6669</a>
<a id='n6670' href='#n6670'>6670</a>
<a id='n6671' href='#n6671'>6671</a>
<a id='n6672' href='#n6672'>6672</a>
<a id='n6673' href='#n6673'>6673</a>
<a id='n6674' href='#n6674'>6674</a>
<a id='n6675' href='#n6675'>6675</a>
<a id='n6676' href='#n6676'>6676</a>
<a id='n6677' href='#n6677'>6677</a>
<a id='n6678' href='#n6678'>6678</a>
<a id='n6679' href='#n6679'>6679</a>
<a id='n6680' href='#n6680'>6680</a>
<a id='n6681' href='#n6681'>6681</a>
<a id='n6682' href='#n6682'>6682</a>
<a id='n6683' href='#n6683'>6683</a>
<a id='n6684' href='#n6684'>6684</a>
<a id='n6685' href='#n6685'>6685</a>
<a id='n6686' href='#n6686'>6686</a>
<a id='n6687' href='#n6687'>6687</a>
<a id='n6688' href='#n6688'>6688</a>
<a id='n6689' href='#n6689'>6689</a>
<a id='n6690' href='#n6690'>6690</a>
<a id='n6691' href='#n6691'>6691</a>
<a id='n6692' href='#n6692'>6692</a>
<a id='n6693' href='#n6693'>6693</a>
<a id='n6694' href='#n6694'>6694</a>
<a id='n6695' href='#n6695'>6695</a>
<a id='n6696' href='#n6696'>6696</a>
<a id='n6697' href='#n6697'>6697</a>
<a id='n6698' href='#n6698'>6698</a>
<a id='n6699' href='#n6699'>6699</a>
<a id='n6700' href='#n6700'>6700</a>
<a id='n6701' href='#n6701'>6701</a>
<a id='n6702' href='#n6702'>6702</a>
<a id='n6703' href='#n6703'>6703</a>
<a id='n6704' href='#n6704'>6704</a>
<a id='n6705' href='#n6705'>6705</a>
<a id='n6706' href='#n6706'>6706</a>
<a id='n6707' href='#n6707'>6707</a>
<a id='n6708' href='#n6708'>6708</a>
<a id='n6709' href='#n6709'>6709</a>
<a id='n6710' href='#n6710'>6710</a>
<a id='n6711' href='#n6711'>6711</a>
<a id='n6712' href='#n6712'>6712</a>
<a id='n6713' href='#n6713'>6713</a>
<a id='n6714' href='#n6714'>6714</a>
<a id='n6715' href='#n6715'>6715</a>
<a id='n6716' href='#n6716'>6716</a>
<a id='n6717' href='#n6717'>6717</a>
<a id='n6718' href='#n6718'>6718</a>
<a id='n6719' href='#n6719'>6719</a>
<a id='n6720' href='#n6720'>6720</a>
<a id='n6721' href='#n6721'>6721</a>
<a id='n6722' href='#n6722'>6722</a>
<a id='n6723' href='#n6723'>6723</a>
<a id='n6724' href='#n6724'>6724</a>
<a id='n6725' href='#n6725'>6725</a>
<a id='n6726' href='#n6726'>6726</a>
<a id='n6727' href='#n6727'>6727</a>
<a id='n6728' href='#n6728'>6728</a>
<a id='n6729' href='#n6729'>6729</a>
<a id='n6730' href='#n6730'>6730</a>
<a id='n6731' href='#n6731'>6731</a>
<a id='n6732' href='#n6732'>6732</a>
<a id='n6733' href='#n6733'>6733</a>
<a id='n6734' href='#n6734'>6734</a>
<a id='n6735' href='#n6735'>6735</a>
<a id='n6736' href='#n6736'>6736</a>
<a id='n6737' href='#n6737'>6737</a>
<a id='n6738' href='#n6738'>6738</a>
<a id='n6739' href='#n6739'>6739</a>
<a id='n6740' href='#n6740'>6740</a>
<a id='n6741' href='#n6741'>6741</a>
<a id='n6742' href='#n6742'>6742</a>
<a id='n6743' href='#n6743'>6743</a>
<a id='n6744' href='#n6744'>6744</a>
<a id='n6745' href='#n6745'>6745</a>
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<a id='n6747' href='#n6747'>6747</a>
<a id='n6748' href='#n6748'>6748</a>
<a id='n6749' href='#n6749'>6749</a>
<a id='n6750' href='#n6750'>6750</a>
<a id='n6751' href='#n6751'>6751</a>
<a id='n6752' href='#n6752'>6752</a>
<a id='n6753' href='#n6753'>6753</a>
<a id='n6754' href='#n6754'>6754</a>
<a id='n6755' href='#n6755'>6755</a>
<a id='n6756' href='#n6756'>6756</a>
<a id='n6757' href='#n6757'>6757</a>
<a id='n6758' href='#n6758'>6758</a>
<a id='n6759' href='#n6759'>6759</a>
<a id='n6760' href='#n6760'>6760</a>
<a id='n6761' href='#n6761'>6761</a>
<a id='n6762' href='#n6762'>6762</a>
<a id='n6763' href='#n6763'>6763</a>
<a id='n6764' href='#n6764'>6764</a>
<a id='n6765' href='#n6765'>6765</a>
<a id='n6766' href='#n6766'>6766</a>
<a id='n6767' href='#n6767'>6767</a>
<a id='n6768' href='#n6768'>6768</a>
<a id='n6769' href='#n6769'>6769</a>
<a id='n6770' href='#n6770'>6770</a>
<a id='n6771' href='#n6771'>6771</a>
<a id='n6772' href='#n6772'>6772</a>
<a id='n6773' href='#n6773'>6773</a>
<a id='n6774' href='#n6774'>6774</a>
<a id='n6775' href='#n6775'>6775</a>
<a id='n6776' href='#n6776'>6776</a>
<a id='n6777' href='#n6777'>6777</a>
<a id='n6778' href='#n6778'>6778</a>
<a id='n6779' href='#n6779'>6779</a>
<a id='n6780' href='#n6780'>6780</a>
<a id='n6781' href='#n6781'>6781</a>
<a id='n6782' href='#n6782'>6782</a>
<a id='n6783' href='#n6783'>6783</a>
<a id='n6784' href='#n6784'>6784</a>
<a id='n6785' href='#n6785'>6785</a>
<a id='n6786' href='#n6786'>6786</a>
<a id='n6787' href='#n6787'>6787</a>
<a id='n6788' href='#n6788'>6788</a>
<a id='n6789' href='#n6789'>6789</a>
<a id='n6790' href='#n6790'>6790</a>
<a id='n6791' href='#n6791'>6791</a>
<a id='n6792' href='#n6792'>6792</a>
<a id='n6793' href='#n6793'>6793</a>
<a id='n6794' href='#n6794'>6794</a>
<a id='n6795' href='#n6795'>6795</a>
<a id='n6796' href='#n6796'>6796</a>
<a id='n6797' href='#n6797'>6797</a>
<a id='n6798' href='#n6798'>6798</a>
<a id='n6799' href='#n6799'>6799</a>
<a id='n6800' href='#n6800'>6800</a>
<a id='n6801' href='#n6801'>6801</a>
<a id='n6802' href='#n6802'>6802</a>
<a id='n6803' href='#n6803'>6803</a>
<a id='n6804' href='#n6804'>6804</a>
<a id='n6805' href='#n6805'>6805</a>
<a id='n6806' href='#n6806'>6806</a>
<a id='n6807' href='#n6807'>6807</a>
<a id='n6808' href='#n6808'>6808</a>
<a id='n6809' href='#n6809'>6809</a>
<a id='n6810' href='#n6810'>6810</a>
<a id='n6811' href='#n6811'>6811</a>
<a id='n6812' href='#n6812'>6812</a>
<a id='n6813' href='#n6813'>6813</a>
<a id='n6814' href='#n6814'>6814</a>
<a id='n6815' href='#n6815'>6815</a>
<a id='n6816' href='#n6816'>6816</a>
<a id='n6817' href='#n6817'>6817</a>
<a id='n6818' href='#n6818'>6818</a>
<a id='n6819' href='#n6819'>6819</a>
<a id='n6820' href='#n6820'>6820</a>
<a id='n6821' href='#n6821'>6821</a>
<a id='n6822' href='#n6822'>6822</a>
<a id='n6823' href='#n6823'>6823</a>
<a id='n6824' href='#n6824'>6824</a>
<a id='n6825' href='#n6825'>6825</a>
<a id='n6826' href='#n6826'>6826</a>
<a id='n6827' href='#n6827'>6827</a>
<a id='n6828' href='#n6828'>6828</a>
<a id='n6829' href='#n6829'>6829</a>
<a id='n6830' href='#n6830'>6830</a>
<a id='n6831' href='#n6831'>6831</a>
<a id='n6832' href='#n6832'>6832</a>
<a id='n6833' href='#n6833'>6833</a>
<a id='n6834' href='#n6834'>6834</a>
<a id='n6835' href='#n6835'>6835</a>
<a id='n6836' href='#n6836'>6836</a>
<a id='n6837' href='#n6837'>6837</a>
<a id='n6838' href='#n6838'>6838</a>
<a id='n6839' href='#n6839'>6839</a>
<a id='n6840' href='#n6840'>6840</a>
<a id='n6841' href='#n6841'>6841</a>
<a id='n6842' href='#n6842'>6842</a>
<a id='n6843' href='#n6843'>6843</a>
<a id='n6844' href='#n6844'>6844</a>
<a id='n6845' href='#n6845'>6845</a>
<a id='n6846' href='#n6846'>6846</a>
<a id='n6847' href='#n6847'>6847</a>
<a id='n6848' href='#n6848'>6848</a>
<a id='n6849' href='#n6849'>6849</a>
<a id='n6850' href='#n6850'>6850</a>
<a id='n6851' href='#n6851'>6851</a>
<a id='n6852' href='#n6852'>6852</a>
<a id='n6853' href='#n6853'>6853</a>
<a id='n6854' href='#n6854'>6854</a>
<a id='n6855' href='#n6855'>6855</a>
<a id='n6856' href='#n6856'>6856</a>
<a id='n6857' href='#n6857'>6857</a>
<a id='n6858' href='#n6858'>6858</a>
<a id='n6859' href='#n6859'>6859</a>
<a id='n6860' href='#n6860'>6860</a>
<a id='n6861' href='#n6861'>6861</a>
<a id='n6862' href='#n6862'>6862</a>
<a id='n6863' href='#n6863'>6863</a>
<a id='n6864' href='#n6864'>6864</a>
<a id='n6865' href='#n6865'>6865</a>
<a id='n6866' href='#n6866'>6866</a>
<a id='n6867' href='#n6867'>6867</a>
<a id='n6868' href='#n6868'>6868</a>
<a id='n6869' href='#n6869'>6869</a>
<a id='n6870' href='#n6870'>6870</a>
<a id='n6871' href='#n6871'>6871</a>
<a id='n6872' href='#n6872'>6872</a>
<a id='n6873' href='#n6873'>6873</a>
<a id='n6874' href='#n6874'>6874</a>
<a id='n6875' href='#n6875'>6875</a>
<a id='n6876' href='#n6876'>6876</a>
<a id='n6877' href='#n6877'>6877</a>
<a id='n6878' href='#n6878'>6878</a>
<a id='n6879' href='#n6879'>6879</a>
<a id='n6880' href='#n6880'>6880</a>
<a id='n6881' href='#n6881'>6881</a>
<a id='n6882' href='#n6882'>6882</a>
<a id='n6883' href='#n6883'>6883</a>
<a id='n6884' href='#n6884'>6884</a>
<a id='n6885' href='#n6885'>6885</a>
<a id='n6886' href='#n6886'>6886</a>
<a id='n6887' href='#n6887'>6887</a>
<a id='n6888' href='#n6888'>6888</a>
<a id='n6889' href='#n6889'>6889</a>
<a id='n6890' href='#n6890'>6890</a>
<a id='n6891' href='#n6891'>6891</a>
<a id='n6892' href='#n6892'>6892</a>
<a id='n6893' href='#n6893'>6893</a>
<a id='n6894' href='#n6894'>6894</a>
<a id='n6895' href='#n6895'>6895</a>
<a id='n6896' href='#n6896'>6896</a>
<a id='n6897' href='#n6897'>6897</a>
<a id='n6898' href='#n6898'>6898</a>
<a id='n6899' href='#n6899'>6899</a>
<a id='n6900' href='#n6900'>6900</a>
<a id='n6901' href='#n6901'>6901</a>
<a id='n6902' href='#n6902'>6902</a>
<a id='n6903' href='#n6903'>6903</a>
<a id='n6904' href='#n6904'>6904</a>
<a id='n6905' href='#n6905'>6905</a>
<a id='n6906' href='#n6906'>6906</a>
<a id='n6907' href='#n6907'>6907</a>
<a id='n6908' href='#n6908'>6908</a>
<a id='n6909' href='#n6909'>6909</a>
<a id='n6910' href='#n6910'>6910</a>
<a id='n6911' href='#n6911'>6911</a>
<a id='n6912' href='#n6912'>6912</a>
<a id='n6913' href='#n6913'>6913</a>
<a id='n6914' href='#n6914'>6914</a>
<a id='n6915' href='#n6915'>6915</a>
<a id='n6916' href='#n6916'>6916</a>
<a id='n6917' href='#n6917'>6917</a>
<a id='n6918' href='#n6918'>6918</a>
<a id='n6919' href='#n6919'>6919</a>
<a id='n6920' href='#n6920'>6920</a>
<a id='n6921' href='#n6921'>6921</a>
<a id='n6922' href='#n6922'>6922</a>
<a id='n6923' href='#n6923'>6923</a>
<a id='n6924' href='#n6924'>6924</a>
<a id='n6925' href='#n6925'>6925</a>
<a id='n6926' href='#n6926'>6926</a>
<a id='n6927' href='#n6927'>6927</a>
<a id='n6928' href='#n6928'>6928</a>
<a id='n6929' href='#n6929'>6929</a>
<a id='n6930' href='#n6930'>6930</a>
<a id='n6931' href='#n6931'>6931</a>
<a id='n6932' href='#n6932'>6932</a>
<a id='n6933' href='#n6933'>6933</a>
<a id='n6934' href='#n6934'>6934</a>
<a id='n6935' href='#n6935'>6935</a>
<a id='n6936' href='#n6936'>6936</a>
<a id='n6937' href='#n6937'>6937</a>
<a id='n6938' href='#n6938'>6938</a>
<a id='n6939' href='#n6939'>6939</a>
<a id='n6940' href='#n6940'>6940</a>
<a id='n6941' href='#n6941'>6941</a>
<a id='n6942' href='#n6942'>6942</a>
<a id='n6943' href='#n6943'>6943</a>
<a id='n6944' href='#n6944'>6944</a>
<a id='n6945' href='#n6945'>6945</a>
<a id='n6946' href='#n6946'>6946</a>
<a id='n6947' href='#n6947'>6947</a>
<a id='n6948' href='#n6948'>6948</a>
<a id='n6949' href='#n6949'>6949</a>
<a id='n6950' href='#n6950'>6950</a>
<a id='n6951' href='#n6951'>6951</a>
<a id='n6952' href='#n6952'>6952</a>
<a id='n6953' href='#n6953'>6953</a>
<a id='n6954' href='#n6954'>6954</a>
<a id='n6955' href='#n6955'>6955</a>
<a id='n6956' href='#n6956'>6956</a>
<a id='n6957' href='#n6957'>6957</a>
<a id='n6958' href='#n6958'>6958</a>
<a id='n6959' href='#n6959'>6959</a>
<a id='n6960' href='#n6960'>6960</a>
<a id='n6961' href='#n6961'>6961</a>
<a id='n6962' href='#n6962'>6962</a>
<a id='n6963' href='#n6963'>6963</a>
<a id='n6964' href='#n6964'>6964</a>
<a id='n6965' href='#n6965'>6965</a>
<a id='n6966' href='#n6966'>6966</a>
<a id='n6967' href='#n6967'>6967</a>
<a id='n6968' href='#n6968'>6968</a>
<a id='n6969' href='#n6969'>6969</a>
<a id='n6970' href='#n6970'>6970</a>
<a id='n6971' href='#n6971'>6971</a>
<a id='n6972' href='#n6972'>6972</a>
<a id='n6973' href='#n6973'>6973</a>
<a id='n6974' href='#n6974'>6974</a>
<a id='n6975' href='#n6975'>6975</a>
<a id='n6976' href='#n6976'>6976</a>
<a id='n6977' href='#n6977'>6977</a>
<a id='n6978' href='#n6978'>6978</a>
<a id='n6979' href='#n6979'>6979</a>
<a id='n6980' href='#n6980'>6980</a>
<a id='n6981' href='#n6981'>6981</a>
<a id='n6982' href='#n6982'>6982</a>
<a id='n6983' href='#n6983'>6983</a>
<a id='n6984' href='#n6984'>6984</a>
<a id='n6985' href='#n6985'>6985</a>
<a id='n6986' href='#n6986'>6986</a>
<a id='n6987' href='#n6987'>6987</a>
<a id='n6988' href='#n6988'>6988</a>
<a id='n6989' href='#n6989'>6989</a>
<a id='n6990' href='#n6990'>6990</a>
<a id='n6991' href='#n6991'>6991</a>
<a id='n6992' href='#n6992'>6992</a>
<a id='n6993' href='#n6993'>6993</a>
<a id='n6994' href='#n6994'>6994</a>
<a id='n6995' href='#n6995'>6995</a>
<a id='n6996' href='#n6996'>6996</a>
<a id='n6997' href='#n6997'>6997</a>
<a id='n6998' href='#n6998'>6998</a>
<a id='n6999' href='#n6999'>6999</a>
<a id='n7000' href='#n7000'>7000</a>
<a id='n7001' href='#n7001'>7001</a>
<a id='n7002' href='#n7002'>7002</a>
<a id='n7003' href='#n7003'>7003</a>
<a id='n7004' href='#n7004'>7004</a>
<a id='n7005' href='#n7005'>7005</a>
<a id='n7006' href='#n7006'>7006</a>
<a id='n7007' href='#n7007'>7007</a>
<a id='n7008' href='#n7008'>7008</a>
<a id='n7009' href='#n7009'>7009</a>
<a id='n7010' href='#n7010'>7010</a>
<a id='n7011' href='#n7011'>7011</a>
<a id='n7012' href='#n7012'>7012</a>
<a id='n7013' href='#n7013'>7013</a>
<a id='n7014' href='#n7014'>7014</a>
<a id='n7015' href='#n7015'>7015</a>
<a id='n7016' href='#n7016'>7016</a>
<a id='n7017' href='#n7017'>7017</a>
<a id='n7018' href='#n7018'>7018</a>
<a id='n7019' href='#n7019'>7019</a>
<a id='n7020' href='#n7020'>7020</a>
<a id='n7021' href='#n7021'>7021</a>
<a id='n7022' href='#n7022'>7022</a>
<a id='n7023' href='#n7023'>7023</a>
<a id='n7024' href='#n7024'>7024</a>
<a id='n7025' href='#n7025'>7025</a>
<a id='n7026' href='#n7026'>7026</a>
<a id='n7027' href='#n7027'>7027</a>
<a id='n7028' href='#n7028'>7028</a>
<a id='n7029' href='#n7029'>7029</a>
<a id='n7030' href='#n7030'>7030</a>
<a id='n7031' href='#n7031'>7031</a>
<a id='n7032' href='#n7032'>7032</a>
<a id='n7033' href='#n7033'>7033</a>
<a id='n7034' href='#n7034'>7034</a>
<a id='n7035' href='#n7035'>7035</a>
<a id='n7036' href='#n7036'>7036</a>
<a id='n7037' href='#n7037'>7037</a>
<a id='n7038' href='#n7038'>7038</a>
<a id='n7039' href='#n7039'>7039</a>
<a id='n7040' href='#n7040'>7040</a>
<a id='n7041' href='#n7041'>7041</a>
<a id='n7042' href='#n7042'>7042</a>
<a id='n7043' href='#n7043'>7043</a>
<a id='n7044' href='#n7044'>7044</a>
<a id='n7045' href='#n7045'>7045</a>
<a id='n7046' href='#n7046'>7046</a>
<a id='n7047' href='#n7047'>7047</a>
<a id='n7048' href='#n7048'>7048</a>
<a id='n7049' href='#n7049'>7049</a>
<a id='n7050' href='#n7050'>7050</a>
<a id='n7051' href='#n7051'>7051</a>
<a id='n7052' href='#n7052'>7052</a>
<a id='n7053' href='#n7053'>7053</a>
<a id='n7054' href='#n7054'>7054</a>
<a id='n7055' href='#n7055'>7055</a>
<a id='n7056' href='#n7056'>7056</a>
<a id='n7057' href='#n7057'>7057</a>
<a id='n7058' href='#n7058'>7058</a>
<a id='n7059' href='#n7059'>7059</a>
<a id='n7060' href='#n7060'>7060</a>
<a id='n7061' href='#n7061'>7061</a>
<a id='n7062' href='#n7062'>7062</a>
<a id='n7063' href='#n7063'>7063</a>
<a id='n7064' href='#n7064'>7064</a>
<a id='n7065' href='#n7065'>7065</a>
<a id='n7066' href='#n7066'>7066</a>
<a id='n7067' href='#n7067'>7067</a>
<a id='n7068' href='#n7068'>7068</a>
<a id='n7069' href='#n7069'>7069</a>
<a id='n7070' href='#n7070'>7070</a>
<a id='n7071' href='#n7071'>7071</a>
<a id='n7072' href='#n7072'>7072</a>
<a id='n7073' href='#n7073'>7073</a>
<a id='n7074' href='#n7074'>7074</a>
<a id='n7075' href='#n7075'>7075</a>
<a id='n7076' href='#n7076'>7076</a>
<a id='n7077' href='#n7077'>7077</a>
<a id='n7078' href='#n7078'>7078</a>
<a id='n7079' href='#n7079'>7079</a>
<a id='n7080' href='#n7080'>7080</a>
<a id='n7081' href='#n7081'>7081</a>
<a id='n7082' href='#n7082'>7082</a>
<a id='n7083' href='#n7083'>7083</a>
<a id='n7084' href='#n7084'>7084</a>
<a id='n7085' href='#n7085'>7085</a>
<a id='n7086' href='#n7086'>7086</a>
<a id='n7087' href='#n7087'>7087</a>
<a id='n7088' href='#n7088'>7088</a>
<a id='n7089' href='#n7089'>7089</a>
<a id='n7090' href='#n7090'>7090</a>
<a id='n7091' href='#n7091'>7091</a>
<a id='n7092' href='#n7092'>7092</a>
<a id='n7093' href='#n7093'>7093</a>
<a id='n7094' href='#n7094'>7094</a>
<a id='n7095' href='#n7095'>7095</a>
<a id='n7096' href='#n7096'>7096</a>
<a id='n7097' href='#n7097'>7097</a>
<a id='n7098' href='#n7098'>7098</a>
<a id='n7099' href='#n7099'>7099</a>
<a id='n7100' href='#n7100'>7100</a>
<a id='n7101' href='#n7101'>7101</a>
<a id='n7102' href='#n7102'>7102</a>
<a id='n7103' href='#n7103'>7103</a>
<a id='n7104' href='#n7104'>7104</a>
<a id='n7105' href='#n7105'>7105</a>
<a id='n7106' href='#n7106'>7106</a>
<a id='n7107' href='#n7107'>7107</a>
<a id='n7108' href='#n7108'>7108</a>
<a id='n7109' href='#n7109'>7109</a>
<a id='n7110' href='#n7110'>7110</a>
<a id='n7111' href='#n7111'>7111</a>
<a id='n7112' href='#n7112'>7112</a>
<a id='n7113' href='#n7113'>7113</a>
<a id='n7114' href='#n7114'>7114</a>
<a id='n7115' href='#n7115'>7115</a>
<a id='n7116' href='#n7116'>7116</a>
<a id='n7117' href='#n7117'>7117</a>
<a id='n7118' href='#n7118'>7118</a>
<a id='n7119' href='#n7119'>7119</a>
<a id='n7120' href='#n7120'>7120</a>
<a id='n7121' href='#n7121'>7121</a>
<a id='n7122' href='#n7122'>7122</a>
<a id='n7123' href='#n7123'>7123</a>
<a id='n7124' href='#n7124'>7124</a>
<a id='n7125' href='#n7125'>7125</a>
<a id='n7126' href='#n7126'>7126</a>
<a id='n7127' href='#n7127'>7127</a>
<a id='n7128' href='#n7128'>7128</a>
<a id='n7129' href='#n7129'>7129</a>
<a id='n7130' href='#n7130'>7130</a>
<a id='n7131' href='#n7131'>7131</a>
<a id='n7132' href='#n7132'>7132</a>
<a id='n7133' href='#n7133'>7133</a>
<a id='n7134' href='#n7134'>7134</a>
<a id='n7135' href='#n7135'>7135</a>
<a id='n7136' href='#n7136'>7136</a>
<a id='n7137' href='#n7137'>7137</a>
<a id='n7138' href='#n7138'>7138</a>
<a id='n7139' href='#n7139'>7139</a>
<a id='n7140' href='#n7140'>7140</a>
<a id='n7141' href='#n7141'>7141</a>
<a id='n7142' href='#n7142'>7142</a>
<a id='n7143' href='#n7143'>7143</a>
<a id='n7144' href='#n7144'>7144</a>
<a id='n7145' href='#n7145'>7145</a>
<a id='n7146' href='#n7146'>7146</a>
<a id='n7147' href='#n7147'>7147</a>
<a id='n7148' href='#n7148'>7148</a>
<a id='n7149' href='#n7149'>7149</a>
<a id='n7150' href='#n7150'>7150</a>
<a id='n7151' href='#n7151'>7151</a>
<a id='n7152' href='#n7152'>7152</a>
<a id='n7153' href='#n7153'>7153</a>
<a id='n7154' href='#n7154'>7154</a>
<a id='n7155' href='#n7155'>7155</a>
<a id='n7156' href='#n7156'>7156</a>
<a id='n7157' href='#n7157'>7157</a>
<a id='n7158' href='#n7158'>7158</a>
<a id='n7159' href='#n7159'>7159</a>
<a id='n7160' href='#n7160'>7160</a>
<a id='n7161' href='#n7161'>7161</a>
<a id='n7162' href='#n7162'>7162</a>
<a id='n7163' href='#n7163'>7163</a>
<a id='n7164' href='#n7164'>7164</a>
<a id='n7165' href='#n7165'>7165</a>
<a id='n7166' href='#n7166'>7166</a>
<a id='n7167' href='#n7167'>7167</a>
<a id='n7168' href='#n7168'>7168</a>
<a id='n7169' href='#n7169'>7169</a>
<a id='n7170' href='#n7170'>7170</a>
<a id='n7171' href='#n7171'>7171</a>
<a id='n7172' href='#n7172'>7172</a>
<a id='n7173' href='#n7173'>7173</a>
<a id='n7174' href='#n7174'>7174</a>
<a id='n7175' href='#n7175'>7175</a>
<a id='n7176' href='#n7176'>7176</a>
<a id='n7177' href='#n7177'>7177</a>
<a id='n7178' href='#n7178'>7178</a>
<a id='n7179' href='#n7179'>7179</a>
<a id='n7180' href='#n7180'>7180</a>
<a id='n7181' href='#n7181'>7181</a>
<a id='n7182' href='#n7182'>7182</a>
<a id='n7183' href='#n7183'>7183</a>
<a id='n7184' href='#n7184'>7184</a>
<a id='n7185' href='#n7185'>7185</a>
<a id='n7186' href='#n7186'>7186</a>
<a id='n7187' href='#n7187'>7187</a>
<a id='n7188' href='#n7188'>7188</a>
<a id='n7189' href='#n7189'>7189</a>
<a id='n7190' href='#n7190'>7190</a>
<a id='n7191' href='#n7191'>7191</a>
<a id='n7192' href='#n7192'>7192</a>
<a id='n7193' href='#n7193'>7193</a>
<a id='n7194' href='#n7194'>7194</a>
<a id='n7195' href='#n7195'>7195</a>
<a id='n7196' href='#n7196'>7196</a>
<a id='n7197' href='#n7197'>7197</a>
<a id='n7198' href='#n7198'>7198</a>
<a id='n7199' href='#n7199'>7199</a>
<a id='n7200' href='#n7200'>7200</a>
<a id='n7201' href='#n7201'>7201</a>
<a id='n7202' href='#n7202'>7202</a>
<a id='n7203' href='#n7203'>7203</a>
<a id='n7204' href='#n7204'>7204</a>
<a id='n7205' href='#n7205'>7205</a>
<a id='n7206' href='#n7206'>7206</a>
<a id='n7207' href='#n7207'>7207</a>
<a id='n7208' href='#n7208'>7208</a>
<a id='n7209' href='#n7209'>7209</a>
<a id='n7210' href='#n7210'>7210</a>
<a id='n7211' href='#n7211'>7211</a>
<a id='n7212' href='#n7212'>7212</a>
<a id='n7213' href='#n7213'>7213</a>
<a id='n7214' href='#n7214'>7214</a>
<a id='n7215' href='#n7215'>7215</a>
<a id='n7216' href='#n7216'>7216</a>
<a id='n7217' href='#n7217'>7217</a>
<a id='n7218' href='#n7218'>7218</a>
<a id='n7219' href='#n7219'>7219</a>
<a id='n7220' href='#n7220'>7220</a>
<a id='n7221' href='#n7221'>7221</a>
<a id='n7222' href='#n7222'>7222</a>
<a id='n7223' href='#n7223'>7223</a>
<a id='n7224' href='#n7224'>7224</a>
<a id='n7225' href='#n7225'>7225</a>
<a id='n7226' href='#n7226'>7226</a>
<a id='n7227' href='#n7227'>7227</a>
<a id='n7228' href='#n7228'>7228</a>
<a id='n7229' href='#n7229'>7229</a>
<a id='n7230' href='#n7230'>7230</a>
<a id='n7231' href='#n7231'>7231</a>
<a id='n7232' href='#n7232'>7232</a>
<a id='n7233' href='#n7233'>7233</a>
<a id='n7234' href='#n7234'>7234</a>
<a id='n7235' href='#n7235'>7235</a>
<a id='n7236' href='#n7236'>7236</a>
<a id='n7237' href='#n7237'>7237</a>
<a id='n7238' href='#n7238'>7238</a>
<a id='n7239' href='#n7239'>7239</a>
<a id='n7240' href='#n7240'>7240</a>
<a id='n7241' href='#n7241'>7241</a>
<a id='n7242' href='#n7242'>7242</a>
<a id='n7243' href='#n7243'>7243</a>
<a id='n7244' href='#n7244'>7244</a>
<a id='n7245' href='#n7245'>7245</a>
<a id='n7246' href='#n7246'>7246</a>
<a id='n7247' href='#n7247'>7247</a>
<a id='n7248' href='#n7248'>7248</a>
<a id='n7249' href='#n7249'>7249</a>
<a id='n7250' href='#n7250'>7250</a>
<a id='n7251' href='#n7251'>7251</a>
<a id='n7252' href='#n7252'>7252</a>
<a id='n7253' href='#n7253'>7253</a>
<a id='n7254' href='#n7254'>7254</a>
<a id='n7255' href='#n7255'>7255</a>
<a id='n7256' href='#n7256'>7256</a>
<a id='n7257' href='#n7257'>7257</a>
<a id='n7258' href='#n7258'>7258</a>
<a id='n7259' href='#n7259'>7259</a>
<a id='n7260' href='#n7260'>7260</a>
<a id='n7261' href='#n7261'>7261</a>
<a id='n7262' href='#n7262'>7262</a>
<a id='n7263' href='#n7263'>7263</a>
<a id='n7264' href='#n7264'>7264</a>
<a id='n7265' href='#n7265'>7265</a>
<a id='n7266' href='#n7266'>7266</a>
<a id='n7267' href='#n7267'>7267</a>
<a id='n7268' href='#n7268'>7268</a>
<a id='n7269' href='#n7269'>7269</a>
<a id='n7270' href='#n7270'>7270</a>
<a id='n7271' href='#n7271'>7271</a>
<a id='n7272' href='#n7272'>7272</a>
<a id='n7273' href='#n7273'>7273</a>
<a id='n7274' href='#n7274'>7274</a>
<a id='n7275' href='#n7275'>7275</a>
<a id='n7276' href='#n7276'>7276</a>
<a id='n7277' href='#n7277'>7277</a>
<a id='n7278' href='#n7278'>7278</a>
<a id='n7279' href='#n7279'>7279</a>
<a id='n7280' href='#n7280'>7280</a>
<a id='n7281' href='#n7281'>7281</a>
<a id='n7282' href='#n7282'>7282</a>
<a id='n7283' href='#n7283'>7283</a>
<a id='n7284' href='#n7284'>7284</a>
<a id='n7285' href='#n7285'>7285</a>
<a id='n7286' href='#n7286'>7286</a>
<a id='n7287' href='#n7287'>7287</a>
<a id='n7288' href='#n7288'>7288</a>
<a id='n7289' href='#n7289'>7289</a>
<a id='n7290' href='#n7290'>7290</a>
<a id='n7291' href='#n7291'>7291</a>
<a id='n7292' href='#n7292'>7292</a>
<a id='n7293' href='#n7293'>7293</a>
<a id='n7294' href='#n7294'>7294</a>
<a id='n7295' href='#n7295'>7295</a>
<a id='n7296' href='#n7296'>7296</a>
<a id='n7297' href='#n7297'>7297</a>
<a id='n7298' href='#n7298'>7298</a>
<a id='n7299' href='#n7299'>7299</a>
<a id='n7300' href='#n7300'>7300</a>
<a id='n7301' href='#n7301'>7301</a>
<a id='n7302' href='#n7302'>7302</a>
<a id='n7303' href='#n7303'>7303</a>
<a id='n7304' href='#n7304'>7304</a>
<a id='n7305' href='#n7305'>7305</a>
<a id='n7306' href='#n7306'>7306</a>
<a id='n7307' href='#n7307'>7307</a>
<a id='n7308' href='#n7308'>7308</a>
<a id='n7309' href='#n7309'>7309</a>
<a id='n7310' href='#n7310'>7310</a>
<a id='n7311' href='#n7311'>7311</a>
<a id='n7312' href='#n7312'>7312</a>
<a id='n7313' href='#n7313'>7313</a>
<a id='n7314' href='#n7314'>7314</a>
<a id='n7315' href='#n7315'>7315</a>
<a id='n7316' href='#n7316'>7316</a>
<a id='n7317' href='#n7317'>7317</a>
<a id='n7318' href='#n7318'>7318</a>
<a id='n7319' href='#n7319'>7319</a>
<a id='n7320' href='#n7320'>7320</a>
<a id='n7321' href='#n7321'>7321</a>
<a id='n7322' href='#n7322'>7322</a>
<a id='n7323' href='#n7323'>7323</a>
<a id='n7324' href='#n7324'>7324</a>
<a id='n7325' href='#n7325'>7325</a>
<a id='n7326' href='#n7326'>7326</a>
<a id='n7327' href='#n7327'>7327</a>
<a id='n7328' href='#n7328'>7328</a>
<a id='n7329' href='#n7329'>7329</a>
<a id='n7330' href='#n7330'>7330</a>
<a id='n7331' href='#n7331'>7331</a>
<a id='n7332' href='#n7332'>7332</a>
<a id='n7333' href='#n7333'>7333</a>
<a id='n7334' href='#n7334'>7334</a>
<a id='n7335' href='#n7335'>7335</a>
<a id='n7336' href='#n7336'>7336</a>
<a id='n7337' href='#n7337'>7337</a>
<a id='n7338' href='#n7338'>7338</a>
<a id='n7339' href='#n7339'>7339</a>
<a id='n7340' href='#n7340'>7340</a>
<a id='n7341' href='#n7341'>7341</a>
<a id='n7342' href='#n7342'>7342</a>
<a id='n7343' href='#n7343'>7343</a>
<a id='n7344' href='#n7344'>7344</a>
<a id='n7345' href='#n7345'>7345</a>
<a id='n7346' href='#n7346'>7346</a>
<a id='n7347' href='#n7347'>7347</a>
<a id='n7348' href='#n7348'>7348</a>
<a id='n7349' href='#n7349'>7349</a>
<a id='n7350' href='#n7350'>7350</a>
<a id='n7351' href='#n7351'>7351</a>
<a id='n7352' href='#n7352'>7352</a>
<a id='n7353' href='#n7353'>7353</a>
<a id='n7354' href='#n7354'>7354</a>
<a id='n7355' href='#n7355'>7355</a>
<a id='n7356' href='#n7356'>7356</a>
<a id='n7357' href='#n7357'>7357</a>
<a id='n7358' href='#n7358'>7358</a>
<a id='n7359' href='#n7359'>7359</a>
<a id='n7360' href='#n7360'>7360</a>
<a id='n7361' href='#n7361'>7361</a>
<a id='n7362' href='#n7362'>7362</a>
<a id='n7363' href='#n7363'>7363</a>
<a id='n7364' href='#n7364'>7364</a>
<a id='n7365' href='#n7365'>7365</a>
<a id='n7366' href='#n7366'>7366</a>
<a id='n7367' href='#n7367'>7367</a>
<a id='n7368' href='#n7368'>7368</a>
<a id='n7369' href='#n7369'>7369</a>
<a id='n7370' href='#n7370'>7370</a>
<a id='n7371' href='#n7371'>7371</a>
<a id='n7372' href='#n7372'>7372</a>
<a id='n7373' href='#n7373'>7373</a>
<a id='n7374' href='#n7374'>7374</a>
<a id='n7375' href='#n7375'>7375</a>
<a id='n7376' href='#n7376'>7376</a>
<a id='n7377' href='#n7377'>7377</a>
<a id='n7378' href='#n7378'>7378</a>
<a id='n7379' href='#n7379'>7379</a>
<a id='n7380' href='#n7380'>7380</a>
<a id='n7381' href='#n7381'>7381</a>
<a id='n7382' href='#n7382'>7382</a>
<a id='n7383' href='#n7383'>7383</a>
<a id='n7384' href='#n7384'>7384</a>
<a id='n7385' href='#n7385'>7385</a>
<a id='n7386' href='#n7386'>7386</a>
<a id='n7387' href='#n7387'>7387</a>
<a id='n7388' href='#n7388'>7388</a>
<a id='n7389' href='#n7389'>7389</a>
<a id='n7390' href='#n7390'>7390</a>
<a id='n7391' href='#n7391'>7391</a>
<a id='n7392' href='#n7392'>7392</a>
<a id='n7393' href='#n7393'>7393</a>
<a id='n7394' href='#n7394'>7394</a>
<a id='n7395' href='#n7395'>7395</a>
<a id='n7396' href='#n7396'>7396</a>
<a id='n7397' href='#n7397'>7397</a>
<a id='n7398' href='#n7398'>7398</a>
<a id='n7399' href='#n7399'>7399</a>
<a id='n7400' href='#n7400'>7400</a>
<a id='n7401' href='#n7401'>7401</a>
<a id='n7402' href='#n7402'>7402</a>
<a id='n7403' href='#n7403'>7403</a>
<a id='n7404' href='#n7404'>7404</a>
<a id='n7405' href='#n7405'>7405</a>
<a id='n7406' href='#n7406'>7406</a>
<a id='n7407' href='#n7407'>7407</a>
<a id='n7408' href='#n7408'>7408</a>
<a id='n7409' href='#n7409'>7409</a>
<a id='n7410' href='#n7410'>7410</a>
<a id='n7411' href='#n7411'>7411</a>
<a id='n7412' href='#n7412'>7412</a>
<a id='n7413' href='#n7413'>7413</a>
<a id='n7414' href='#n7414'>7414</a>
<a id='n7415' href='#n7415'>7415</a>
<a id='n7416' href='#n7416'>7416</a>
<a id='n7417' href='#n7417'>7417</a>
<a id='n7418' href='#n7418'>7418</a>
<a id='n7419' href='#n7419'>7419</a>
<a id='n7420' href='#n7420'>7420</a>
<a id='n7421' href='#n7421'>7421</a>
<a id='n7422' href='#n7422'>7422</a>
<a id='n7423' href='#n7423'>7423</a>
<a id='n7424' href='#n7424'>7424</a>
<a id='n7425' href='#n7425'>7425</a>
<a id='n7426' href='#n7426'>7426</a>
<a id='n7427' href='#n7427'>7427</a>
<a id='n7428' href='#n7428'>7428</a>
<a id='n7429' href='#n7429'>7429</a>
<a id='n7430' href='#n7430'>7430</a>
<a id='n7431' href='#n7431'>7431</a>
<a id='n7432' href='#n7432'>7432</a>
<a id='n7433' href='#n7433'>7433</a>
<a id='n7434' href='#n7434'>7434</a>
<a id='n7435' href='#n7435'>7435</a>
<a id='n7436' href='#n7436'>7436</a>
<a id='n7437' href='#n7437'>7437</a>
<a id='n7438' href='#n7438'>7438</a>
<a id='n7439' href='#n7439'>7439</a>
<a id='n7440' href='#n7440'>7440</a>
<a id='n7441' href='#n7441'>7441</a>
<a id='n7442' href='#n7442'>7442</a>
<a id='n7443' href='#n7443'>7443</a>
<a id='n7444' href='#n7444'>7444</a>
<a id='n7445' href='#n7445'>7445</a>
<a id='n7446' href='#n7446'>7446</a>
<a id='n7447' href='#n7447'>7447</a>
<a id='n7448' href='#n7448'>7448</a>
<a id='n7449' href='#n7449'>7449</a>
<a id='n7450' href='#n7450'>7450</a>
<a id='n7451' href='#n7451'>7451</a>
<a id='n7452' href='#n7452'>7452</a>
<a id='n7453' href='#n7453'>7453</a>
<a id='n7454' href='#n7454'>7454</a>
<a id='n7455' href='#n7455'>7455</a>
<a id='n7456' href='#n7456'>7456</a>
<a id='n7457' href='#n7457'>7457</a>
<a id='n7458' href='#n7458'>7458</a>
<a id='n7459' href='#n7459'>7459</a>
<a id='n7460' href='#n7460'>7460</a>
<a id='n7461' href='#n7461'>7461</a>
<a id='n7462' href='#n7462'>7462</a>
<a id='n7463' href='#n7463'>7463</a>
<a id='n7464' href='#n7464'>7464</a>
<a id='n7465' href='#n7465'>7465</a>
<a id='n7466' href='#n7466'>7466</a>
<a id='n7467' href='#n7467'>7467</a>
<a id='n7468' href='#n7468'>7468</a>
<a id='n7469' href='#n7469'>7469</a>
<a id='n7470' href='#n7470'>7470</a>
<a id='n7471' href='#n7471'>7471</a>
<a id='n7472' href='#n7472'>7472</a>
<a id='n7473' href='#n7473'>7473</a>
<a id='n7474' href='#n7474'>7474</a>
<a id='n7475' href='#n7475'>7475</a>
<a id='n7476' href='#n7476'>7476</a>
<a id='n7477' href='#n7477'>7477</a>
<a id='n7478' href='#n7478'>7478</a>
<a id='n7479' href='#n7479'>7479</a>
<a id='n7480' href='#n7480'>7480</a>
<a id='n7481' href='#n7481'>7481</a>
<a id='n7482' href='#n7482'>7482</a>
<a id='n7483' href='#n7483'>7483</a>
<a id='n7484' href='#n7484'>7484</a>
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<a id='n7486' href='#n7486'>7486</a>
<a id='n7487' href='#n7487'>7487</a>
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<a id='n7489' href='#n7489'>7489</a>
<a id='n7490' href='#n7490'>7490</a>
<a id='n7491' href='#n7491'>7491</a>
<a id='n7492' href='#n7492'>7492</a>
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<a id='n7494' href='#n7494'>7494</a>
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<a id='n7496' href='#n7496'>7496</a>
<a id='n7497' href='#n7497'>7497</a>
<a id='n7498' href='#n7498'>7498</a>
<a id='n7499' href='#n7499'>7499</a>
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<a id='n7509' href='#n7509'>7509</a>
<a id='n7510' href='#n7510'>7510</a>
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<a id='n7600' href='#n7600'>7600</a>
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<a id='n7602' href='#n7602'>7602</a>
<a id='n7603' href='#n7603'>7603</a>
<a id='n7604' href='#n7604'>7604</a>
<a id='n7605' href='#n7605'>7605</a>
<a id='n7606' href='#n7606'>7606</a>
<a id='n7607' href='#n7607'>7607</a>
<a id='n7608' href='#n7608'>7608</a>
<a id='n7609' href='#n7609'>7609</a>
<a id='n7610' href='#n7610'>7610</a>
<a id='n7611' href='#n7611'>7611</a>
<a id='n7612' href='#n7612'>7612</a>
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<a id='n7620' href='#n7620'>7620</a>
<a id='n7621' href='#n7621'>7621</a>
<a id='n7622' href='#n7622'>7622</a>
<a id='n7623' href='#n7623'>7623</a>
<a id='n7624' href='#n7624'>7624</a>
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</pre></td>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="c">% Generated using the yosys &#39;help -write-tex-command-reference-manual&#39; command.</span>

<span class="k">\section</span><span class="nb">{</span>abc -- use ABC for technology mapping<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:abc<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    abc [options] [selection]

This pass uses the ABC tool [1] for technology mapping of yosys&#39;s internal gate
library to a target architecture.

    -exe &lt;command&gt;
        use the specified command instead of &quot;&lt;yosys-bindir&gt;/yosys-abc&quot; to execute ABC.
        This can e.g. be used to call a specific version of ABC or a wrapper.

    -script &lt;file&gt;
        use the specified ABC script file instead of the default script.

        if &lt;file&gt; starts with a plus sign (+), then the rest of the filename
        string is interpreted as the command string to be passed to ABC. The
        leading plus sign is removed and all commas (,) in the string are
        replaced with blanks before the string is passed to ABC.

        if no -script parameter is given, the following scripts are used:

        for -liberty without -constr:
          strash; ifraig; scorr; dc2; dretime; strash; <span class="nb">&amp;</span>get -n; <span class="nb">&amp;</span>dch -f;
               <span class="nb">&amp;</span>nf <span class="nb">{</span>D<span class="nb">}</span>; <span class="nb">&amp;</span>put

        for -liberty with -constr:
          strash; ifraig; scorr; dc2; dretime; strash; <span class="nb">&amp;</span>get -n; <span class="nb">&amp;</span>dch -f;
               <span class="nb">&amp;</span>nf <span class="nb">{</span>D<span class="nb">}</span>; <span class="nb">&amp;</span>put; buffer; upsize <span class="nb">{</span>D<span class="nb">}</span>; dnsize <span class="nb">{</span>D<span class="nb">}</span>; stime -p

        for -lut/-luts (only one LUT size):
          strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2;
               lutpack <span class="nb">{</span>S<span class="nb">}</span>

        for -lut/-luts (different LUT sizes):
          strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2

        for -sop:
          strash; ifraig; scorr; dc2; dretime; strash; dch -f;
               cover <span class="nb">{</span>I<span class="nb">}</span> <span class="nb">{</span>P<span class="nb">}</span>

        otherwise:
          strash; ifraig; scorr; dc2; dretime; strash; <span class="nb">&amp;</span>get -n; <span class="nb">&amp;</span>dch -f;
               <span class="nb">&amp;</span>nf <span class="nb">{</span>D<span class="nb">}</span>; <span class="nb">&amp;</span>put

    -fast
        use different default scripts that are slightly faster (at the cost
        of output quality):

        for -liberty without -constr:
          strash; dretime; map <span class="nb">{</span>D<span class="nb">}</span>

        for -liberty with -constr:
          strash; dretime; map <span class="nb">{</span>D<span class="nb">}</span>; buffer; upsize <span class="nb">{</span>D<span class="nb">}</span>; dnsize <span class="nb">{</span>D<span class="nb">}</span>;
               stime -p

        for -lut/-luts:
          strash; dretime; if

        for -sop:
          strash; dretime; cover -I <span class="nb">{</span>I<span class="nb">}</span> -P <span class="nb">{</span>P<span class="nb">}</span>

        otherwise:
          strash; dretime; map

    -liberty &lt;file&gt;
        generate netlists for the specified cell library (using the liberty
        file format).

    -constr &lt;file&gt;
        pass this file with timing constraints to ABC. use with -liberty.

        a constr file contains two lines:
            set<span class="nb">_</span>driving<span class="nb">_</span>cell &lt;cell<span class="nb">_</span>name&gt;
            set<span class="nb">_</span>load &lt;floating<span class="nb">_</span>point<span class="nb">_</span>number&gt;

        the set<span class="nb">_</span>driving<span class="nb">_</span>cell statement defines which cell type is assumed to
        drive the primary inputs and the set<span class="nb">_</span>load statement sets the load in
        femtofarads for each primary output.

    -D &lt;picoseconds&gt;
        set delay target. the string <span class="nb">{</span>D<span class="nb">}</span> in the default scripts above is
        replaced by this option when used, and an empty string otherwise.
        this also replaces &#39;dretime&#39; with &#39;dretime; retime -o <span class="nb">{</span>D<span class="nb">}</span>&#39; in the
        default scripts above.

    -I &lt;num&gt;
        maximum number of SOP inputs.
        (replaces <span class="nb">{</span>I<span class="nb">}</span> in the default scripts above)

    -P &lt;num&gt;
        maximum number of SOP products.
        (replaces <span class="nb">{</span>P<span class="nb">}</span> in the default scripts above)

    -S &lt;num&gt;
        maximum number of LUT inputs shared.
        (replaces <span class="nb">{</span>S<span class="nb">}</span> in the default scripts above, default: -S 1)

    -lut &lt;width&gt;
        generate netlist using luts of (max) the specified width.

    -lut &lt;w1&gt;:&lt;w2&gt;
        generate netlist using luts of (max) the specified width &lt;w2&gt;. All
        luts with width &lt;= &lt;w1&gt; have constant cost. for luts larger than &lt;w1&gt;
        the area cost doubles with each additional input bit. the delay cost
        is still constant for all lut widths.

    -luts &lt;cost1&gt;,&lt;cost2&gt;,&lt;cost3&gt;,&lt;sizeN&gt;:&lt;cost4-N&gt;,..
        generate netlist using luts. Use the specified costs for luts with 1,
        2, 3, .. inputs.

    -sop
        map to sum-of-product cells and inverters

    -g type1,type2,...
        Map to the specified list of gate types. Supported gates types are:
           AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,
           NMUX, AOI3, OAI3, AOI4, OAI4.
        (The NOT gate is always added to this list automatically.)

        The following aliases can be used to reference common sets of gate types:
          simple: AND OR XOR MUX
          cmos2:  NAND NOR
          cmos3:  NAND NOR AOI3 OAI3
          cmos4:  NAND NOR AOI3 OAI3 AOI4 OAI4
          cmos:   NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR
          gates:  AND NAND OR NOR XOR XNOR ANDNOT ORNOT
          aig:    AND NAND OR NOR ANDNOT ORNOT

        The alias &#39;all&#39; represent the full set of all gate types.

        Prefix a gate type with a &#39;-&#39; to remove it from the list. For example
        the arguments &#39;AND,OR,XOR&#39; and &#39;simple,-MUX&#39; are equivalent.

        The default is &#39;all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4&#39;.

    -dff
        also pass <span class="s">$</span><span class="nb">_DFF_?_ and </span><span class="s">$</span><span class="nb">_</span>DFFE<span class="nb">_</span>??<span class="nb">_</span> cells through ABC. modules with many
        clock domains are automatically partitioned in clock domains and each
        domain is passed through ABC independently.

    -clk [!]&lt;clock-signal-name&gt;[,[!]&lt;enable-signal-name&gt;]
        use only the specified clock domain. this is like -dff, but only FF
        cells that belong to the specified clock domain are used.

    -keepff
        set the &quot;keep&quot; attribute on flip-flop output wires. (and thus preserve
        them, for example for equivalence checking.)

    -nocleanup
        when this option is used, the temporary files created by this pass
        are not removed. this is useful for debugging.

    -showtmp
        print the temp dir name in log. usually this is suppressed so that the
        command output is identical across runs.

    -markgroups
        set a &#39;abcgroup&#39; attribute on all objects created by ABC. The value of
        this attribute is a unique integer for each ABC process started. This
        is useful for debugging the partitioning of clock domains.

    -dress
        run the &#39;dress&#39; command after all other ABC commands. This aims to
        preserve naming by an equivalence check between the original and post-ABC
        netlists (experimental).

When neither -liberty nor -lut is used, the Yosys standard cell library is
loaded into ABC before the ABC script is executed.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to &quot;run ABC on your design&quot;. It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write<span class="nb">_</span>blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>abc9 -- use ABC9 for technology mapping<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:abc9<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    abc9 [options] [selection]

This script pass performs a sequence of commands to facilitate the use of the ABC
tool [1] for technology mapping of the current design to a target FPGA
architecture. Only fully-selected modules are supported.

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -exe &lt;command&gt;
        use the specified command instead of &quot;&lt;yosys-bindir&gt;/yosys-abc&quot; to execute ABC.
        This can e.g. be used to call a specific version of ABC or a wrapper.

    -script &lt;file&gt;
        use the specified ABC script file instead of the default script.

        if &lt;file&gt; starts with a plus sign (+), then the rest of the filename
        string is interpreted as the command string to be passed to ABC. The
        leading plus sign is removed and all commas (,) in the string are
        replaced with blanks before the string is passed to ABC.

        if no -script parameter is given, the following scripts are used:
          <span class="nb">&amp;</span>scorr; <span class="nb">&amp;</span>sweep; <span class="nb">&amp;</span>dc2; <span class="nb">&amp;</span>dch -f; <span class="nb">&amp;</span>ps; <span class="nb">&amp;</span>if <span class="nb">{</span>C<span class="nb">}</span> <span class="nb">{</span>W<span class="nb">}</span> <span class="nb">{</span>D<span class="nb">}</span> <span class="nb">{</span>R<span class="nb">}</span> -v; <span class="nb">&amp;</span>mfs

    -fast
        use different default scripts that are slightly faster (at the cost
        of output quality):
          <span class="nb">&amp;</span>if <span class="nb">{</span>C<span class="nb">}</span> <span class="nb">{</span>W<span class="nb">}</span> <span class="nb">{</span>D<span class="nb">}</span> <span class="nb">{</span>R<span class="nb">}</span> -v

    -D &lt;picoseconds&gt;
        set delay target. the string <span class="nb">{</span>D<span class="nb">}</span> in the default scripts above is
        replaced by this option when used, and an empty string otherwise
        (indicating best possible delay).

    -lut &lt;width&gt;
        generate netlist using luts of (max) the specified width.

    -lut &lt;w1&gt;:&lt;w2&gt;
        generate netlist using luts of (max) the specified width &lt;w2&gt;. All
        luts with width &lt;= &lt;w1&gt; have constant cost. for luts larger than &lt;w1&gt;
        the area cost doubles with each additional input bit. the delay cost
        is still constant for all lut widths.

    -lut &lt;file&gt;
        pass this file with lut library to ABC.

    -luts &lt;cost1&gt;,&lt;cost2&gt;,&lt;cost3&gt;,&lt;sizeN&gt;:&lt;cost4-N&gt;,..
        generate netlist using luts. Use the specified costs for luts with 1,
        2, 3, .. inputs.

    -maxlut &lt;width&gt;
        when auto-generating the lut library, discard all luts equal to or
        greater than this size (applicable when neither -lut nor -luts is
        specified).

    -dff
        also pass <span class="s">$</span><span class="nb">_ABC</span><span class="m">9</span><span class="nb">_FF_ cells through to ABC. modules with many clock</span>
<span class="nb">        domains are marked as such and automatically partitioned by ABC.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nocleanup</span>
<span class="nb">        when this option is used, the temporary files created by this pass</span>
<span class="nb">        are not removed. this is useful for debugging.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">showtmp</span>
<span class="nb">        print the temp dir name in log. usually this is suppressed so that the</span>
<span class="nb">        command output is identical across runs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">box &lt;file&gt;</span>
<span class="nb">        pass this file with box library to ABC.</span>

<span class="nb">Note that this is a logic optimization pass within Yosys that is calling ABC</span>
<span class="nb">internally. This is not going to &quot;run ABC on your design&quot;. It will instead run</span>
<span class="nb">ABC on logic snippets extracted from your design. You will not get any useful</span>
<span class="nb">output when passing an ABC script that writes a file. Instead write your full</span>
<span class="nb">design as an XAIGER file with `write_xaiger&#39; and then load that into ABC</span>
<span class="nb">externally if you want to use ABC to convert your design into another format.</span>

<span class="o">[</span><span class="m">1</span><span class="o">]</span><span class="nb"> http:</span><span class="o">//</span><span class="nb">www.eecs.berkeley.edu</span><span class="o">/</span><span class="nb">~alanmi</span><span class="o">/</span><span class="nb">abc</span><span class="o">/</span><span class="nb"></span>


<span class="nb">    pre:</span>
<span class="nb">        abc</span><span class="m">9</span><span class="nb">_ops </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        scc </span><span class="o">-</span><span class="nb">set_attr abc</span><span class="m">9</span><span class="nb">_scc_id {}</span>
<span class="nb">        abc</span><span class="m">9</span><span class="nb">_ops </span><span class="o">-</span><span class="nb">mark_scc </span><span class="o">-</span><span class="nb">prep_delays </span><span class="o">-</span><span class="nb">prep_xaiger </span><span class="o">[-</span><span class="nb">dff</span><span class="o">]</span><span class="nb">    </span><span class="o">(</span><span class="nb">option for </span><span class="o">-</span><span class="nb">dff</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        abc</span><span class="m">9</span><span class="nb">_ops </span><span class="o">-</span><span class="nb">prep_lut &lt;maxlut&gt;    </span><span class="o">(</span><span class="nb">skip if </span><span class="o">-</span><span class="nb">lut or </span><span class="o">-</span><span class="nb">luts</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        abc</span><span class="m">9</span><span class="nb">_ops </span><span class="o">-</span><span class="nb">prep_box </span><span class="o">[-</span><span class="nb">dff</span><span class="o">]</span><span class="nb">    </span><span class="o">(</span><span class="nb">skip if </span><span class="o">-</span><span class="nb">box</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        select </span><span class="o">-</span><span class="nb">set abc</span><span class="m">9</span><span class="nb">_holes A:abc</span><span class="m">9</span><span class="nb">_holes</span>
<span class="nb">        flatten </span><span class="o">-</span><span class="nb">wb @abc</span><span class="m">9</span><span class="nb">_holes</span>
<span class="nb">        techmap @abc</span><span class="m">9</span><span class="nb">_holes</span>
<span class="nb">        abc</span><span class="m">9</span><span class="nb">_ops </span><span class="o">-</span><span class="nb">prep_dff    </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">dff</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">purge @abc</span><span class="m">9</span><span class="nb">_holes</span>
<span class="nb">        aigmap</span>
<span class="nb">        wbflip @abc</span><span class="m">9</span><span class="nb">_holes</span>

<span class="nb">    map:</span>
<span class="nb">        foreach module in selection</span>
<span class="nb">            abc</span><span class="m">9</span><span class="nb">_ops </span><span class="o">-</span><span class="nb">write_lut &lt;abc</span><span class="o">-</span><span class="nb">temp</span><span class="o">-</span><span class="nb">dir&gt;</span><span class="o">/</span><span class="nb">input.lut    </span><span class="o">(</span><span class="nb">skip if &#39;</span><span class="o">-</span><span class="nb">lut&#39; or &#39;</span><span class="o">-</span><span class="nb">luts&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">            abc</span><span class="m">9</span><span class="nb">_ops </span><span class="o">-</span><span class="nb">write_box &lt;abc</span><span class="o">-</span><span class="nb">temp</span><span class="o">-</span><span class="nb">dir&gt;</span><span class="o">/</span><span class="nb">input.box</span>
<span class="nb">            write_xaiger </span><span class="o">-</span><span class="nb">map &lt;abc</span><span class="o">-</span><span class="nb">temp</span><span class="o">-</span><span class="nb">dir&gt;</span><span class="o">/</span><span class="nb">input.sym &lt;abc</span><span class="o">-</span><span class="nb">temp</span><span class="o">-</span><span class="nb">dir&gt;</span><span class="o">/</span><span class="nb">input.xaig</span>
<span class="nb">            abc</span><span class="m">9</span><span class="nb">_exe </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">-</span><span class="nb">cwd &lt;abc</span><span class="o">-</span><span class="nb">temp</span><span class="o">-</span><span class="nb">dir&gt; </span><span class="o">[-</span><span class="nb">lut &lt;abc</span><span class="o">-</span><span class="nb">temp</span><span class="o">-</span><span class="nb">dir&gt;</span><span class="o">/</span><span class="nb">input.lut</span><span class="o">]</span><span class="nb"> </span><span class="o">-</span><span class="nb">box &lt;abc</span><span class="o">-</span><span class="nb">temp</span><span class="o">-</span><span class="nb">dir&gt;</span><span class="o">/</span><span class="nb">input.box</span>
<span class="nb">            read_aiger </span><span class="o">-</span><span class="nb">xaiger </span><span class="o">-</span><span class="nb">wideports </span><span class="o">-</span><span class="nb">module_name &lt;module</span><span class="o">-</span><span class="nb">name&gt;</span><span class="s">$</span>abc9 -map &lt;abc-temp-dir&gt;/input.sym &lt;abc-temp-dir&gt;/output.aig
            abc9<span class="nb">_</span>ops -reintegrate
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>abc9<span class="k">\_</span>exe -- use ABC9 for technology mapping<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:abc9<span class="nb">_</span>exe<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    abc9<span class="nb">_</span>exe [options]

 
This pass uses the ABC tool [1] for technology mapping of the top module
(according to the (* top *) attribute or if only one module is currently selected)
to a target FPGA architecture.

    -exe &lt;command&gt;
        use the specified command instead of &quot;&lt;yosys-bindir&gt;/yosys-abc&quot; to execute ABC.
        This can e.g. be used to call a specific version of ABC or a wrapper.

    -script &lt;file&gt;
        use the specified ABC script file instead of the default script.

        if &lt;file&gt; starts with a plus sign (+), then the rest of the filename
        string is interpreted as the command string to be passed to ABC. The
        leading plus sign is removed and all commas (,) in the string are
        replaced with blanks before the string is passed to ABC.

        if no -script parameter is given, the following scripts are used:
          <span class="nb">&amp;</span>scorr; <span class="nb">&amp;</span>sweep; <span class="nb">&amp;</span>dc2; <span class="nb">&amp;</span>dch -f; <span class="nb">&amp;</span>ps; <span class="nb">&amp;</span>if <span class="nb">{</span>C<span class="nb">}</span> <span class="nb">{</span>W<span class="nb">}</span> <span class="nb">{</span>D<span class="nb">}</span> <span class="nb">{</span>R<span class="nb">}</span> -v; <span class="nb">&amp;</span>mfs

    -fast
        use different default scripts that are slightly faster (at the cost
        of output quality):
          <span class="nb">&amp;</span>if <span class="nb">{</span>C<span class="nb">}</span> <span class="nb">{</span>W<span class="nb">}</span> <span class="nb">{</span>D<span class="nb">}</span> <span class="nb">{</span>R<span class="nb">}</span> -v

    -D &lt;picoseconds&gt;
        set delay target. the string <span class="nb">{</span>D<span class="nb">}</span> in the default scripts above is
        replaced by this option when used, and an empty string otherwise
        (indicating best possible delay).

    -lut &lt;width&gt;
        generate netlist using luts of (max) the specified width.

    -lut &lt;w1&gt;:&lt;w2&gt;
        generate netlist using luts of (max) the specified width &lt;w2&gt;. All
        luts with width &lt;= &lt;w1&gt; have constant cost. for luts larger than &lt;w1&gt;
        the area cost doubles with each additional input bit. the delay cost
        is still constant for all lut widths.

    -lut &lt;file&gt;
        pass this file with lut library to ABC.

    -luts &lt;cost1&gt;,&lt;cost2&gt;,&lt;cost3&gt;,&lt;sizeN&gt;:&lt;cost4-N&gt;,..
        generate netlist using luts. Use the specified costs for luts with 1,
        2, 3, .. inputs.

    -showtmp
        print the temp dir name in log. usually this is suppressed so that the
        command output is identical across runs.

    -box &lt;file&gt;
        pass this file with box library to ABC.

    -cwd &lt;dir&gt;
        use this as the current working directory, inside which the &#39;input.xaig&#39;
        file is expected. temporary files will be created in this directory, and
        the mapped result will be written to &#39;output.aig&#39;.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to &quot;run ABC on your design&quot;. It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write<span class="nb">_</span>blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>abc9<span class="k">\_</span>ops -- helper functions for ABC9<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:abc9<span class="nb">_</span>ops<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    abc9<span class="nb">_</span>ops [options] [selection]

This pass contains a set of supporting operations for use during ABC technology
mapping, and is expected to be called in conjunction with other operations from
the `abc9&#39; script pass. Only fully-selected modules are supported.

    -check
        check that the design is valid, e.g. (* abc9<span class="nb">_</span>box<span class="nb">_</span>id *) values are unique,
        (* abc9<span class="nb">_</span>carry *) is only given for one input/output port, etc.

    -prep<span class="nb">_</span>delays
        insert `<span class="s">$</span><span class="nb">__ABC</span><span class="m">9</span><span class="nb">_DELAY&#39; blackbox cells into the design to account for</span>
<span class="nb">        certain required times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mark_scc</span>
<span class="nb">        for an arbitrarily chosen cell in each unique SCC of each selected module</span>
<span class="nb">        </span><span class="o">(</span><span class="nb">tagged with an </span><span class="o">(*</span><span class="nb"> abc</span><span class="m">9</span><span class="nb">_scc_id </span><span class="o">=</span><span class="nb"> &lt;int&gt; </span><span class="o">*)</span><span class="nb"> attribute</span><span class="o">)</span><span class="nb">, temporarily mark all</span>
<span class="nb">        wires driven by this cell&#39;s outputs with a </span><span class="o">(*</span><span class="nb"> keep </span><span class="o">*)</span><span class="nb"> attribute in order</span>
<span class="nb">        to break the SCC. this temporary attribute will be removed on </span><span class="o">-</span><span class="nb">reintegrate.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">prep_xaiger</span>
<span class="nb">        prepare the design for XAIGER output. this includes computing the</span>
<span class="nb">        topological ordering of ABC</span><span class="m">9</span><span class="nb"> boxes, as well as preparing the</span>
<span class="nb">        &#39;&lt;module</span><span class="o">-</span><span class="nb">name&gt;</span><span class="s">$</span>holes&#39; module that contains the logic behaviour of ABC9
        whiteboxes.

    -dff
        consider flop cells (those instantiating modules marked with (* abc9<span class="nb">_</span>flop *))
        during -prep<span class="nb">_{</span>delays,xaiger,box<span class="nb">}</span>.

    -prep<span class="nb">_</span>dff
        compute the clock domain and initial value of each flop in the design.
        process the &#39;<span class="s">$</span><span class="nb">holes&#39; module to support clock</span><span class="o">-</span><span class="nb">enable functionality.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">prep_lut &lt;maxlut&gt;</span>
<span class="nb">        pre</span><span class="o">-</span><span class="nb">compute the lut library by analysing all modules marked with</span>
<span class="nb">        </span><span class="o">(*</span><span class="nb"> abc</span><span class="m">9</span><span class="nb">_lut</span><span class="o">=</span><span class="nb">&lt;area&gt; </span><span class="o">*)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">write_lut &lt;dst&gt;</span>
<span class="nb">        write the pre</span><span class="o">-</span><span class="nb">computed lut library to &lt;dst&gt;.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">prep_box</span>
<span class="nb">        pre</span><span class="o">-</span><span class="nb">compute the box library by analysing all modules marked with</span>
<span class="nb">        </span><span class="o">(*</span><span class="nb"> abc</span><span class="m">9</span><span class="nb">_box </span><span class="o">*)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">write_box &lt;dst&gt;</span>
<span class="nb">        write the pre</span><span class="o">-</span><span class="nb">computed box library to &lt;dst&gt;.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">reintegrate</span>
<span class="nb">        for each selected module, re</span><span class="o">-</span><span class="nb">intergrate the module &#39;&lt;module</span><span class="o">-</span><span class="nb">name&gt;</span><span class="s">$</span>abc9&#39;
        by first recovering ABC9 boxes, and then stitching in the remaining primary
        inputs and outputs.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>add -- add objects to the design<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:add<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    add &lt;command&gt; [selection]

This command adds objects to the design. It operates on all fully selected
modules. So e.g. &#39;add -wire foo&#39; will add a wire foo to all selected modules.


    add <span class="nb">{</span>-wire|-input|-inout|-output<span class="nb">}</span> &lt;name&gt; &lt;width&gt; [selection]

Add a wire (input, inout, output port) with the given name and width. The
command will fail if the object exists already and has different properties
than the object to be created.


    add -global<span class="nb">_</span>input &lt;name&gt; &lt;width&gt; [selection]

Like &#39;add -input&#39;, but also connect the signal between instances of the
selected modules.


    add <span class="nb">{</span>-assert|-assume|-live|-fair|-cover<span class="nb">}</span> &lt;name1&gt; [-if &lt;name2&gt;]

Add an <span class="s">$</span><span class="nb">assert, </span><span class="s">$</span>assume, etc. cell connected to a wire named name1, with its
enable signal optionally connected to a wire named name2 (default: 1&#39;b1).


    add -mod &lt;name[s]&gt;

Add module[s] with the specified name[s].
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>aigmap -- map logic to and-inverter-graph circuit<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:aigmap<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    aigmap [options] [selection]

Replace all logic cells with circuits made of only <span class="s">$</span><span class="nb">_AND_ and</span>
<span class="s">$</span><span class="nb">_</span>NOT<span class="nb">_</span> cells.

    -nand
        Enable creation of <span class="s">$</span><span class="nb">_NAND_ cells</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">select</span>
<span class="nb">        Overwrite replaced cells in the current selection with new </span><span class="s">$</span><span class="nb">_</span>AND<span class="nb">_</span>,
        <span class="s">$</span><span class="nb">_NOT_, and </span><span class="s">$</span><span class="nb">_</span>NAND<span class="nb">_</span>, cells
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>alumacc -- extract ALU and MACC cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:alumacc<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    alumacc [selection]

This pass translates arithmetic operations like <span class="s">$</span><span class="nb">add, </span><span class="s">$</span>mul, <span class="s">$</span><span class="nb">lt, etc. to </span><span class="s">$</span>alu
and <span class="s">$</span><span class="nb">macc cells.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{anlogic</span><span class="nv">\_</span><span class="nb">eqn </span><span class="o">--</span><span class="nb"> Anlogic: Calculate equations for luts}</span>
<span class="nv">\label</span><span class="nb">{cmd:anlogic_eqn}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    anlogic_eqn </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Calculate equations for luts since bitstream generator depends on it.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{anlogic</span><span class="nv">\_</span><span class="nb">fixcarry </span><span class="o">--</span><span class="nb"> Anlogic: fix carry chain}</span>
<span class="nv">\label</span><span class="nb">{cmd:anlogic_fixcarry}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    anlogic_fixcarry </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Add Anlogic adders to fix carry chain if needed.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{assertpmux </span><span class="o">--</span><span class="nb"> adds asserts for parallel muxes}</span>
<span class="nv">\label</span><span class="nb">{cmd:assertpmux}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    assertpmux </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command adds asserts to the design that assert that all parallel muxes</span>
<span class="o">(</span><span class="s">$</span>pmux cells) have a maximum of one of their inputs enable at any time.

    -noinit
        do not enforce the pmux condition during the init state

    -always
        usually the <span class="s">$</span><span class="nb">pmux condition is only checked when the </span><span class="s">$</span>pmux output
        is used by the mux tree it drives. this option will deactivate this
        additional constraint and check the <span class="s">$</span><span class="nb">pmux condition always.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{async</span><span class="m">2</span><span class="nb">sync </span><span class="o">--</span><span class="nb"> convert async FF inputs to sync circuits}</span>
<span class="nv">\label</span><span class="nb">{cmd:async</span><span class="m">2</span><span class="nb">sync}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    async</span><span class="m">2</span><span class="nb">sync </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command replaces async FF inputs with sync circuits emulating the same</span>
<span class="nb">behavior for when the async signals are actually synchronized to the clock.</span>

<span class="nb">This pass assumes negative hold time for the async FF inputs. For example when</span>
<span class="nb">a reset deasserts with the clock edge, then the FF output will still drive the</span>
<span class="nb">reset value in the next cycle regardless of the data</span><span class="o">-</span><span class="nb">in value at the time of</span>
<span class="nb">the clock edge.</span>

<span class="nb">Currently only </span><span class="s">$</span>adff, <span class="s">$</span><span class="nb">dffsr, and </span><span class="s">$</span>dlatch cells are supported by this pass.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>attrmap -- renaming attributes<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:attrmap<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    attrmap [options] [selection]

This command renames attributes and/or maps key/value pairs to
other key/value pairs.

    -tocase &lt;name&gt;
        Match attribute names case-insensitively and set it to the specified
        name.

    -rename &lt;old<span class="nb">_</span>name&gt; &lt;new<span class="nb">_</span>name&gt;
        Rename attributes as specified

    -map &lt;old<span class="nb">_</span>name&gt;=&lt;old<span class="nb">_</span>value&gt; &lt;new<span class="nb">_</span>name&gt;=&lt;new<span class="nb">_</span>value&gt;
        Map key/value pairs as indicated.

    -imap &lt;old<span class="nb">_</span>name&gt;=&lt;old<span class="nb">_</span>value&gt; &lt;new<span class="nb">_</span>name&gt;=&lt;new<span class="nb">_</span>value&gt;
        Like -map, but use case-insensitive match for &lt;old<span class="nb">_</span>value&gt; when
        it is a string value.

    -remove &lt;name&gt;=&lt;value&gt;
        Remove attributes matching this pattern.

    -modattr
        Operate on module attributes instead of attributes on wires and cells.

For example, mapping Xilinx-style &quot;keep&quot; attributes to Yosys-style:

    attrmap -tocase keep -imap keep=&quot;true&quot; keep=1 <span class="k">\</span>
            -imap keep=&quot;false&quot; keep=0 -remove keep=0
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>attrmvcp -- move or copy attributes from wires to driving cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:attrmvcp<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    attrmvcp [options] [selection]

Move or copy attributes on wires to the cells driving them.

    -copy
        By default, attributes are moved. This will only add
        the attribute to the cell, without removing it from
        the wire.

    -purge
        If no selected cell consumes the attribute, then it is
        left on the wire by default. This option will cause the
        attribute to be removed from the wire, even if no selected
        cell takes it.

    -driven
        By default, attriburtes are moved to the cell driving the
        wire. With this option set it will be moved to the cell
        driven by the wire instead.

    -attr &lt;attrname&gt;
        Move or copy this attribute. This option can be used
        multiple times.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>autoname -- automatically assign names to objects<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:autoname<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    autoname [selection]

Assign auto-generated public names to objects with private names (the ones
with <span class="s">$</span><span class="o">-</span><span class="nb">prefix</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{blackbox </span><span class="o">--</span><span class="nb"> convert modules into blackbox modules}</span>
<span class="nv">\label</span><span class="nb">{cmd:blackbox}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    blackbox </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Convert modules into blackbox modules </span><span class="o">(</span><span class="nb">remove contents and set the blackbox</span>
<span class="nb">module attribute</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{bugpoint </span><span class="o">--</span><span class="nb"> minimize testcases}</span>
<span class="nv">\label</span><span class="nb">{cmd:bugpoint}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    bugpoint </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command minimizes testcases that crash Yosys. It removes an arbitrary part</span>
<span class="nb">of the design and recursively invokes Yosys with a given script, repeating these</span>
<span class="nb">steps while it can find a smaller design that still causes a crash. Once this</span>
<span class="nb">command finishes, it replaces the current design with the smallest testcase it</span>
<span class="nb">was able to produce.</span>

<span class="nb">It is possible to specify the kinds of design part that will be removed. If none</span>
<span class="nb">are specified, all parts of design will be removed.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">yosys &lt;filename&gt;</span>
<span class="nb">        use this Yosys binary. if not specified, `yosys` is used.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">script &lt;filename&gt;</span>
<span class="nb">        use this script to crash Yosys. required.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">grep &lt;string&gt;</span>
<span class="nb">        only consider crashes that place this string in the log file.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">fast</span>
<span class="nb">        run `proc_clean; clean </span><span class="o">-</span><span class="nb">purge` after each minimization step. converges</span>
<span class="nb">        faster, but produces larger testcases, and may fail to produce any</span>
<span class="nb">        testcase at all if the crash is related to dangling wires.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">clean</span>
<span class="nb">        run `proc_clean; clean </span><span class="o">-</span><span class="nb">purge` before checking testcase and after</span>
<span class="nb">        finishing. produces smaller and more useful testcases, but may fail to</span>
<span class="nb">        produce any testcase at all if the crash is related to dangling wires.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">modules</span>
<span class="nb">        try to remove modules.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ports</span>
<span class="nb">        try to remove module ports.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">cells</span>
<span class="nb">        try to remove cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">connections</span>
<span class="nb">        try to reconnect ports to &#39;x.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">assigns</span>
<span class="nb">        try to remove process assigns from cases.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">updates</span>
<span class="nb">        try to remove process updates from syncs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">runner &quot;&lt;prefix&gt;&quot;</span>
<span class="nb">        child process wrapping command, e.g., &quot;timeout </span><span class="m">30</span><span class="nb">&quot;, or valgrind.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{cd </span><span class="o">--</span><span class="nb"> a shortcut for &#39;select </span><span class="o">-</span><span class="nb">module &lt;name&gt;&#39;}</span>
<span class="nv">\label</span><span class="nb">{cmd:cd}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    cd &lt;modname&gt;</span>

<span class="nb">This is just a shortcut for &#39;select </span><span class="o">-</span><span class="nb">module &lt;modname&gt;&#39;.</span>


<span class="nb">    cd &lt;cellname&gt;</span>

<span class="nb">When no module with the specified name is found, but there is a cell</span>
<span class="nb">with the specified name in the current module, then this is equivalent</span>
<span class="nb">to &#39;cd &lt;celltype&gt;&#39;.</span>

<span class="nb">    cd ..</span>

<span class="nb">Remove trailing substrings that start with &#39;.&#39; in current module name until</span>
<span class="nb">the name of a module in the current design is generated, then switch to that</span>
<span class="nb">module. Otherwise clear the current selection.</span>

<span class="nb">    cd</span>

<span class="nb">This is just a shortcut for &#39;select </span><span class="o">-</span><span class="nb">clear&#39;.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{check </span><span class="o">--</span><span class="nb"> check for obvious problems in the design}</span>
<span class="nv">\label</span><span class="nb">{cmd:check}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    check </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass identifies the following problems in the current design:</span>

<span class="nb"> </span><span class="o">-</span><span class="nb"> combinatorial loops</span>

<span class="nb"> </span><span class="o">-</span><span class="nb"> two or more conflicting drivers for one wire</span>

<span class="nb"> </span><span class="o">-</span><span class="nb"> used wires that do not have a driver</span>

<span class="nb">Options:</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">noinit</span>
<span class="nb">    Also check for wires which have the &#39;init&#39; attribute set.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">initdrv</span>
<span class="nb">    Also check for wires that have the &#39;init&#39; attribute set and are not</span>
<span class="nb">    driven by an FF cell type.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">mapped</span>
<span class="nb">    Also check for internal cells that have not been mapped to cells of the</span>
<span class="nb">    target architecture.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">allow</span><span class="o">-</span><span class="nb">tbuf</span>
<span class="nb">    Modify the </span><span class="o">-</span><span class="nb">mapped behavior to still allow </span><span class="s">$</span><span class="nb">_</span>TBUF<span class="nb">_</span> cells.

  -assert
    Produce a runtime error if any problems are found in the current design.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>chformal -- change formal constraints of the design<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:chformal<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    chformal [types] [mode] [options] [selection]

Make changes to the formal constraints of the design. The [types] options
the type of constraint to operate on. If none of the following options are given,
the command will operate on all constraint types:

    -assert       <span class="s">$</span><span class="nb">assert cells, representing assert</span><span class="o">(</span><span class="nb">...</span><span class="o">)</span><span class="nb"> constraints</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">assume       </span><span class="s">$</span>assume cells, representing assume(...) constraints
    -live         <span class="s">$</span><span class="nb">live cells, representing assert</span><span class="o">(</span><span class="nb">s_eventually ...</span><span class="o">)</span><span class="nb"></span>
<span class="nb">    </span><span class="o">-</span><span class="nb">fair         </span><span class="s">$</span>fair cells, representing assume(s<span class="nb">_</span>eventually ...)
    -cover        <span class="s">$</span><span class="nb">cover cells, representing cover</span><span class="o">()</span><span class="nb"> statements</span>

<span class="nb">Exactly one of the following modes must be specified:</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">remove</span>
<span class="nb">        remove the cells and thus constraints from the design</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">early</span>
<span class="nb">        bypass FFs that only delay the activation of a constraint</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">delay &lt;N&gt;</span>
<span class="nb">        delay activation of the constraint by &lt;N&gt; clock cycles</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">skip &lt;N&gt;</span>
<span class="nb">        ignore activation of the constraint in the first &lt;N&gt; clock cycles</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">assert</span><span class="m">2</span><span class="nb">assume</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">assume</span><span class="m">2</span><span class="nb">assert</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">live</span><span class="m">2</span><span class="nb">fair</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">fair</span><span class="m">2</span><span class="nb">live</span>
<span class="nb">        change the roles of cells as indicated. these options can be combined</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{chparam </span><span class="o">--</span><span class="nb"> re</span><span class="o">-</span><span class="nb">evaluate modules with new parameters}</span>
<span class="nv">\label</span><span class="nb">{cmd:chparam}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    chparam </span><span class="o">[</span><span class="nb"> </span><span class="o">-</span><span class="nb">set name value </span><span class="o">]</span><span class="nb">... </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Re</span><span class="o">-</span><span class="nb">evaluate the selected modules with new parameters. String values must be</span>
<span class="nb">passed in double quotes </span><span class="o">(</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">.</span>


<span class="nb">    chparam </span><span class="o">-</span><span class="nb">list </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">List the available parameters of the selected modules.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{chtype </span><span class="o">--</span><span class="nb"> change type of cells in the design}</span>
<span class="nv">\label</span><span class="nb">{cmd:chtype}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    chtype </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Change the types of cells in the design.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set &lt;type&gt;</span>
<span class="nb">        set the cell type to the given type</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">map &lt;old_type&gt; &lt;new_type&gt;</span>
<span class="nb">        change cells types that match &lt;old_type&gt; to &lt;new_type&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{clean </span><span class="o">--</span><span class="nb"> remove unused cells and wires}</span>
<span class="nv">\label</span><span class="nb">{cmd:clean}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    clean </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This is identical to &#39;opt_clean&#39;, but less verbose.</span>

<span class="nb">When commands are separated using the &#39;;;&#39; token, this command will be executed</span>
<span class="nb">between the commands.</span>

<span class="nb">When commands are separated using the &#39;;;;&#39; token, this command will be executed</span>
<span class="nb">in </span><span class="o">-</span><span class="nb">purge mode between the commands.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{clk</span><span class="m">2</span><span class="nb">fflogic </span><span class="o">--</span><span class="nb"> convert clocked FFs to generic </span><span class="nv">\$</span><span class="nb">ff cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:clk</span><span class="m">2</span><span class="nb">fflogic}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    clk</span><span class="m">2</span><span class="nb">fflogic </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command replaces clocked flip</span><span class="o">-</span><span class="nb">flops with generic </span><span class="s">$</span>ff cells that use the
implicit global clock. This is useful for formal verification of designs with
multiple clocks.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>clkbufmap -- insert global buffers on clock networks<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:clkbufmap<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    clkbufmap [options] [selection]

Inserts global buffers between nets connected to clock inputs and their drivers.

In the absence of any selection, all wires without the &#39;clkbuf<span class="nb">_</span>inhibit&#39;
attribute will be considered for global buffer insertion.
Alternatively, to consider all wires without the &#39;buffer<span class="nb">_</span>type&#39; attribute set to
&#39;none&#39; or &#39;bufr&#39; one would specify:
  &#39;w:* a:buffer<span class="nb">_</span>type=none a:buffer<span class="nb">_</span>type=bufr <span class="c">%u %d&#39;</span>
as the selection.

    -buf &lt;celltype&gt; &lt;portname<span class="nb">_</span>out&gt;:&lt;portname<span class="nb">_</span>in&gt;
        Specifies the cell type to use for the global buffers
        and its port names.  The first port will be connected to
        the clock network sinks, and the second will be connected
        to the actual clock source.  This option is required.

    -inpad &lt;celltype&gt; &lt;portname<span class="nb">_</span>out&gt;:&lt;portname<span class="nb">_</span>in&gt;
        If specified, a PAD cell of the given type is inserted on
        clock nets that are also top module&#39;s inputs (in addition
        to the global buffer).
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>connect -- create or remove connections<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:connect<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    connect [-nomap] [-nounset] -set &lt;lhs-expr&gt; &lt;rhs-expr&gt;

Create a connection. This is equivalent to adding the statement &#39;assign
&lt;lhs-expr&gt; = &lt;rhs-expr&gt;;&#39; to the Verilog input. Per default, all existing
drivers for &lt;lhs-expr&gt; are unconnected. This can be overwritten by using
the -nounset option.


    connect [-nomap] -unset &lt;expr&gt;

Unconnect all existing drivers for the specified expression.


    connect [-nomap] -port &lt;cell&gt; &lt;port&gt; &lt;expr&gt;

Connect the specified cell port to the specified cell port.


Per default signal alias names are resolved and all signal names are mapped
the the signal name of the primary driver. Using the -nomap option deactivates
this behavior.

The connect command operates in one module only. Either only one module must
be selected or an active module must be set using the &#39;cd&#39; command.

This command does not operate on module with processes.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>connect<span class="k">\_</span>rpc -- connect to RPC frontend<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:connect<span class="nb">_</span>rpc<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    connect<span class="nb">_</span>rpc -exec &lt;command&gt; [args...]
    connect<span class="nb">_</span>rpc -path &lt;path&gt;

Load modules using an out-of-process frontend.

    -exec &lt;command&gt; [args...]
        run &lt;command&gt; with arguments [args...]. send requests on stdin, read
        responses from stdout.

    -path &lt;path&gt;
        connect to Unix domain socket at &lt;path&gt;. (Unix)
        connect to bidirectional byte-type named pipe at &lt;path&gt;. (Windows)

A simple JSON-based, newline-delimited protocol is used for communicating with
the frontend. Yosys requests data from the frontend by sending exactly 1 line
of JSON. Frontend responds with data or error message by replying with exactly
1 line of JSON as well.

    -&gt; <span class="nb">{</span>&quot;method&quot;: &quot;modules&quot;<span class="nb">}</span>
    &lt;- <span class="nb">{</span>&quot;modules&quot;: [&quot;&lt;module-name&gt;&quot;, ...]<span class="nb">}</span>
    &lt;- <span class="nb">{</span>&quot;error&quot;: &quot;&lt;error-message&gt;&quot;<span class="nb">}</span>
        request for the list of modules that can be derived by this frontend.
        the &#39;hierarchy&#39; command will call back into this frontend if a cell
        with type &lt;module-name&gt; is instantiated in the design.

    -&gt; <span class="nb">{</span>&quot;method&quot;: &quot;derive&quot;, &quot;module&quot;: &quot;&lt;module-name&quot;&gt;, &quot;parameters&quot;: <span class="nb">{</span>
        &quot;&lt;param-name&gt;&quot;: <span class="nb">{</span>&quot;type&quot;: &quot;[unsigned|signed|string|real]&quot;,
                           &quot;value&quot;: &quot;&lt;param-value&gt;&quot;<span class="nb">}</span>, ...<span class="nb">}}</span>
    &lt;- <span class="nb">{</span>&quot;frontend&quot;: &quot;[ilang|verilog|...]&quot;,&quot;source&quot;: &quot;&lt;source&gt;&quot;<span class="nb">}}</span>
    &lt;- <span class="nb">{</span>&quot;error&quot;: &quot;&lt;error-message&gt;&quot;<span class="nb">}</span>
        request for the module &lt;module-name&gt; to be derived for a specific set of
        parameters. &lt;param-name&gt; starts with <span class="k">\ </span>for named parameters, and with <span class="s">$</span><span class="nb"></span>
<span class="nb">        for unnamed parameters, which are numbered starting at </span><span class="m">1</span><span class="nb">.&lt;param</span><span class="o">-</span><span class="nb">value&gt;</span>
<span class="nb">        for integer parameters is always specified as a binary string of unlimited</span>
<span class="nb">        precision. the &lt;source&gt; returned by the frontend is hygienically parsed</span>
<span class="nb">        by a built</span><span class="o">-</span><span class="nb">in Yosys &lt;frontend&gt;, allowing the RPC frontend to return any</span>
<span class="nb">        convenient representation of the module. the derived module is cached,</span>
<span class="nb">        so the response should be the same whenever the same set of parameters</span>
<span class="nb">        is provided.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{connwrappers </span><span class="o">--</span><span class="nb"> match width of input</span><span class="o">-</span><span class="nb">output port pairs}</span>
<span class="nv">\label</span><span class="nb">{cmd:connwrappers}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    connwrappers </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Wrappers are used in coarse</span><span class="o">-</span><span class="nb">grain synthesis to wrap cells with smaller ports</span>
<span class="nb">in wrapper cells with a </span><span class="o">(</span><span class="nb">larger</span><span class="o">)</span><span class="nb"> constant port size. I.e. the upper bits</span>
<span class="nb">of the wrapper output are signed</span><span class="o">/</span><span class="nb">unsigned bit extended. This command uses this</span>
<span class="nb">knowledge to rewire the inputs of the driven cells to match the output of</span>
<span class="nb">the driving cell.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">signed &lt;cell_type&gt; &lt;port_name&gt; &lt;width_param&gt;</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">unsigned &lt;cell_type&gt; &lt;port_name&gt; &lt;width_param&gt;</span>
<span class="nb">        consider the specified signed</span><span class="o">/</span><span class="nb">unsigned wrapper output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">port &lt;cell_type&gt; &lt;port_name&gt; &lt;width_param&gt; &lt;sign_param&gt;</span>
<span class="nb">        use the specified parameter to decide if signed or unsigned</span>

<span class="nb">The options </span><span class="o">-</span><span class="nb">signed, </span><span class="o">-</span><span class="nb">unsigned, and </span><span class="o">-</span><span class="nb">port can be specified multiple times.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{coolrunner</span><span class="m">2</span><span class="nv">\_</span><span class="nb">fixup </span><span class="o">--</span><span class="nb"> insert necessary buffer cells for CoolRunner</span><span class="o">-</span><span class="nb">II architecture}</span>
<span class="nv">\label</span><span class="nb">{cmd:coolrunner</span><span class="m">2</span><span class="nb">_fixup}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    coolrunner</span><span class="m">2</span><span class="nb">_fixup </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Insert necessary buffer cells for CoolRunner</span><span class="o">-</span><span class="nb">II architecture.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{coolrunner</span><span class="m">2</span><span class="nv">\_</span><span class="nb">sop </span><span class="o">--</span><span class="nb"> break </span><span class="nv">\$</span><span class="nb">sop cells into ANDTERM</span><span class="o">/</span><span class="nb">ORTERM cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:coolrunner</span><span class="m">2</span><span class="nb">_sop}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    coolrunner</span><span class="m">2</span><span class="nb">_sop </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Break </span><span class="s">$</span>sop cells into ANDTERM/ORTERM cells.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>copy -- copy modules in the design<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:copy<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    copy old<span class="nb">_</span>name new<span class="nb">_</span>name

Copy the specified module. Note that selection patterns are not supported
by this command.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>cover -- print code coverage counters<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:cover<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    cover [options] [pattern]

Print the code coverage counters collected using the cover() macro in the Yosys
C++ code. This is useful to figure out what parts of Yosys are utilized by a
test bench.

    -q
        Do not print output to the normal destination (console and/or log file)

    -o file
        Write output to this file, truncate if exists.

    -a file
        Write output to this file, append if exists.

    -d dir
        Write output to a newly created file in the specified directory.

When one or more pattern (shell wildcards) are specified, then only counters
matching at least one pattern are printed.


It is also possible to instruct Yosys to print the coverage counters on program
exit to a file using environment variables:

    YOSYS<span class="nb">_</span>COVER<span class="nb">_</span>DIR=&quot;<span class="nb">{</span>dir-name<span class="nb">}</span>&quot; yosys <span class="nb">{</span>args<span class="nb">}</span>

        This will create a file (with an auto-generated name) in this
        directory and write the coverage counters to it.

    YOSYS<span class="nb">_</span>COVER<span class="nb">_</span>FILE=&quot;<span class="nb">{</span>file-name<span class="nb">}</span>&quot; yosys <span class="nb">{</span>args<span class="nb">}</span>

        This will append the coverage counters to the specified file.


Hint: Use the following AWK command to consolidate Yosys coverage files:

    gawk &#39;<span class="nb">{</span> p[<span class="s">$</span><span class="m">3</span><span class="o">]</span><span class="nb"> </span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>1; c[<span class="s">$</span><span class="m">3</span><span class="o">]</span><span class="nb"> </span><span class="o">+=</span><span class="nb"> </span><span class="s">$</span>2; <span class="nb">}</span> END <span class="nb">{</span> for (i in p)
      printf &quot;<span class="c">%-60s %10d %s\n&quot;, p[i], c[i], i; }&#39; {files} | sort -k3</span>


Coverage counters are only available in Yosys for Linux.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>cutpoint -- adds formal cut points to the design<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:cutpoint<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    cutpoint [options] [selection]

This command adds formal cut points to the design.

    -undef
        set cupoint nets to undef (x). the default behavior is to create a
        <span class="s">$</span><span class="nb">anyseq cell and drive the cutpoint net from that</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{debug </span><span class="o">--</span><span class="nb"> run command with debug log messages enabled}</span>
<span class="nv">\label</span><span class="nb">{cmd:debug}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    debug cmd</span>

<span class="nb">Execute the specified command with debug log messages enabled</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{delete </span><span class="o">--</span><span class="nb"> delete objects in the design}</span>
<span class="nv">\label</span><span class="nb">{cmd:delete}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    delete </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Deletes the selected objects. This will also remove entire modules, if the</span>
<span class="nb">whole module is selected.</span>


<span class="nb">    delete {</span><span class="o">-</span><span class="nb">input|</span><span class="o">-</span><span class="nb">output|</span><span class="o">-</span><span class="nb">port} </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Does not delete any object but removes the input and</span><span class="o">/</span><span class="nb">or output flag on the</span>
<span class="nb">selected wires, thus &#39;deleting&#39; module ports.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{deminout </span><span class="o">--</span><span class="nb"> demote inout ports to input or output}</span>
<span class="nv">\label</span><span class="nb">{cmd:deminout}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    deminout </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">&quot;Demote&quot; inout ports to input or output ports, if possible.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{design </span><span class="o">--</span><span class="nb"> save, restore and reset current design}</span>
<span class="nv">\label</span><span class="nb">{cmd:design}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    design </span><span class="o">-</span><span class="nb">reset</span>

<span class="nb">Clear the current design.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">save &lt;name&gt;</span>

<span class="nb">Save the current design under the given name.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">stash &lt;name&gt;</span>

<span class="nb">Save the current design under the given name and then clear the current design.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">push</span>

<span class="nb">Push the current design to the stack and then clear the current design.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">push</span><span class="o">-</span><span class="nb">copy</span>

<span class="nb">Push the current design to the stack without clearing the current design.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">pop</span>

<span class="nb">Reset the current design and pop the last design from the stack.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">load &lt;name&gt;</span>

<span class="nb">Reset the current design and load the design previously saved under the given</span>
<span class="nb">name.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">copy</span><span class="o">-</span><span class="nb">from &lt;name&gt; </span><span class="o">[-</span><span class="nb">as &lt;new_mod_name&gt;</span><span class="o">]</span><span class="nb"> &lt;selection&gt;</span>

<span class="nb">Copy modules from the specified design into the current one. The selection is</span>
<span class="nb">evaluated in the other design.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">copy</span><span class="o">-</span><span class="nb">to &lt;name&gt; </span><span class="o">[-</span><span class="nb">as &lt;new_mod_name&gt;</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Copy modules from the current design into the specified one.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">import &lt;name&gt; </span><span class="o">[-</span><span class="nb">as &lt;new_top_name&gt;</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Import the specified design into the current design. The source design must</span>
<span class="nb">either have a selected top module or the selection must contain exactly one</span>
<span class="nb">module that is then used as top module for this command.</span>


<span class="nb">    design </span><span class="o">-</span><span class="nb">reset</span><span class="o">-</span><span class="nb">vlog</span>

<span class="nb">The Verilog front</span><span class="o">-</span><span class="nb">end remembers defined macros and top</span><span class="o">-</span><span class="nb">level declarations</span>
<span class="nb">between calls to &#39;read_verilog&#39;. This command resets this memory.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{determine</span><span class="nv">\_</span><span class="nb">init </span><span class="o">--</span><span class="nb"> Determine the init value of cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:determine_init}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    determine_init </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Determine the init value of cells that doesn&#39;t allow unknown init value.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{dff</span><span class="m">2</span><span class="nb">dffe </span><span class="o">--</span><span class="nb"> transform </span><span class="nv">\$</span><span class="nb">dff cells to </span><span class="nv">\$</span><span class="nb">dffe cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:dff</span><span class="m">2</span><span class="nb">dffe}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    dff</span><span class="m">2</span><span class="nb">dffe </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass transforms </span><span class="s">$</span>dff cells driven by a tree of multiplexers with one or
more feedback paths to <span class="s">$</span><span class="nb">dffe cells. It also works on gate</span><span class="o">-</span><span class="nb">level cells such as</span>
<span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>P<span class="nb">_</span>, <span class="s">$</span><span class="nb">_DFF_N_ and </span><span class="s">$</span><span class="nb">_</span>MUX<span class="nb">_</span>.

    -unmap
        operate in the opposite direction: replace <span class="s">$</span><span class="nb">dffe cells with combinations</span>
<span class="nb">        of </span><span class="s">$</span>dff and <span class="s">$</span><span class="nb">mux cells. the options below are ignored in unmap mode.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">unmap</span><span class="o">-</span><span class="nb">mince N</span>
<span class="nb">        Same as </span><span class="o">-</span><span class="nb">unmap but only unmap </span><span class="s">$</span>dffe where the clock enable port
        signal is used by less <span class="s">$</span><span class="nb">dffe than the specified number</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">direct &lt;internal_gate_type&gt; &lt;external_gate_type&gt;</span>
<span class="nb">        map directly to external gate type. &lt;internal_gate_type&gt; can</span>
<span class="nb">        be any internal gate</span><span class="o">-</span><span class="nb">level FF cell </span><span class="o">(</span><span class="nb">except </span><span class="s">$</span><span class="nb">_</span>DFFE<span class="nb">_</span>??<span class="nb">_</span>). the
        &lt;external<span class="nb">_</span>gate<span class="nb">_</span>type&gt; is the cell type name for a cell with an
        identical interface to the &lt;internal<span class="nb">_</span>gate<span class="nb">_</span>type&gt;, except it
        also has an high-active enable port &#39;E&#39;.
          Usually &lt;external<span class="nb">_</span>gate<span class="nb">_</span>type&gt; is an intermediate cell type
        that is then translated to the final type using &#39;techmap&#39;.

    -direct-match &lt;pattern&gt;
        like -direct for all DFF cell types matching the expression.
        this will use <span class="s">$</span><span class="nb">__DFFE_</span><span class="o">*</span><span class="nb"> as &lt;external_gate_type&gt; matching the</span>
<span class="nb">        internal gate type </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>*<span class="nb">_</span>, and <span class="s">$</span><span class="nb">__DFFSE_</span><span class="o">*</span><span class="nb"> for those matching</span>
<span class="nb">        </span><span class="s">$</span><span class="nb">_</span>DFFS<span class="nb">_</span>*<span class="nb">_</span>, except for <span class="s">$</span><span class="nb">_DFF_</span><span class="o">[</span><span class="nb">NP</span><span class="o">]</span><span class="nb">_, which is converted to </span>
<span class="nb">        </span><span class="s">$</span><span class="nb">_</span>DFFE<span class="nb">_</span>[NP]<span class="nb">_</span>.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>dff2dffs -- process sync set/reset with SR over CE priority<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:dff2dffs<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    dff2dffs [options] [selection]

Merge synchronous set/reset <span class="s">$</span><span class="nb">_MUX_ cells to create </span><span class="s">$</span><span class="nb">__</span>DFFS<span class="nb">_</span>[NP][NP][01], to be run before
dff2dffe for SR over CE priority.

    -match-init
        Disallow merging synchronous set/reset that has polarity opposite of the
        output wire&#39;s init attribute (if any).
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>dffinit -- set INIT param on FF cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:dffinit<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    dffinit [options] [selection]

This pass sets an FF cell parameter to the the initial value of the net it
drives. (This is primarily used in FPGA flows.)

    -ff &lt;cell<span class="nb">_</span>name&gt; &lt;output<span class="nb">_</span>port&gt; &lt;init<span class="nb">_</span>param&gt;
        operate on the specified cell type. this option can be used
        multiple times.

    -highlow
        use the string values &quot;high&quot; and &quot;low&quot; to represent a single-bit
        initial value of 1 or 0. (multi-bit values are not supported in this
        mode.)

    -strinit &lt;string for high&gt; &lt;string for low&gt; 
        use string values in the command line to represent a single-bit
        initial value of 1 or 0. (multi-bit values are not supported in this
        mode.)

    -noreinit
        fail if the FF cell has already a defined initial value set in other
        passes and the initial value of the net it drives is not equal to
        the already defined initial value.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>dfflibmap -- technology mapping of flip-flops<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:dfflibmap<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    dfflibmap [-prepare] -liberty &lt;file&gt; [selection]

Map internal flip-flop cells to the flip-flop cells in the technology
library specified in the given liberty file.

This pass may add inverters as needed. Therefore it is recommended to
first run this pass and then map the logic paths to the target technology.

When called with -prepare, this command will convert the internal FF cells
to the internal cell types that best match the cells found in the given
liberty file.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>dump -- print parts of the design in ilang format<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:dump<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    dump [options] [selection]

Write the selected parts of the design to the console or specified file in
ilang format.

    -m
        also dump the module headers, even if only parts of a single
        module is selected

    -n
        only dump the module headers if the entire module is selected

    -o &lt;filename&gt;
        write to the specified file.

    -a &lt;filename&gt;
        like -outfile but append instead of overwrite
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>echo -- turning echoing back of commands on and off<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:echo<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    echo on

Print all commands to log before executing them.


    echo off

Do not print all commands to log before executing them. (default)
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>ecp5<span class="k">\_</span>ffinit -- ECP5: handle FF init values<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:ecp5<span class="nb">_</span>ffinit<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    ecp5<span class="nb">_</span>ffinit [options] [selection]

Remove init values for FF output signals when equal to reset value.
If reset is not used, set the reset value to the init value, otherwise
unmap out the reset (if not an async reset).
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>ecp5<span class="k">\_</span>gsr -- ECP5: handle GSR<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:ecp5<span class="nb">_</span>gsr<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    ecp5<span class="nb">_</span>gsr [options] [selection]

Trim active low async resets connected to GSR and resolve GSR parameter,
if a GSR or SGSR primitive is used in the design.

If any cell has the GSR parameter set to &quot;AUTO&quot;, this will be resolved
to &quot;ENABLED&quot; if a GSR primitive is present and the (* nogsr *) attribute
is not set, otherwise it will be resolved to &quot;DISABLED&quot;.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>edgetypes -- list all types of edges in selection<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:edgetypes<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    edgetypes [options] [selection]

This command lists all unique types of &#39;edges&#39; found in the selection. An &#39;edge&#39;
is a 4-tuple of source and sink cell type and port name.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>efinix<span class="k">\_</span>fixcarry -- Efinix: fix carry chain<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:efinix<span class="nb">_</span>fixcarry<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    efinix<span class="nb">_</span>fixcarry [options] [selection]

Add Efinix adders to fix carry chain if needed.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>efinix<span class="k">\_</span>gbuf -- Efinix: insert global clock buffers<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:efinix<span class="nb">_</span>gbuf<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    efinix<span class="nb">_</span>gbuf [options] [selection]

Add Efinix global clock buffers to top module as needed.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>equiv<span class="k">\_</span>add -- add a <span class="k">\$</span>equiv cell<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:equiv<span class="nb">_</span>add<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    equiv<span class="nb">_</span>add [-try] gold<span class="nb">_</span>sig gate<span class="nb">_</span>sig

This command adds an <span class="s">$</span><span class="nb">equiv cell for the specified signals.</span>


<span class="nb">    equiv_add </span><span class="o">[-</span><span class="nb">try</span><span class="o">]</span><span class="nb"> </span><span class="o">-</span><span class="nb">cell gold_cell gate_cell</span>

<span class="nb">This command adds </span><span class="s">$</span>equiv cells for the ports of the specified cells.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>equiv<span class="k">\_</span>induct -- proving <span class="k">\$</span>equiv cells using temporal induction<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:equiv<span class="nb">_</span>induct<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    equiv<span class="nb">_</span>induct [options] [selection]

Uses a version of temporal induction to prove <span class="s">$</span><span class="nb">equiv cells.</span>

<span class="nb">Only selected </span><span class="s">$</span>equiv cells are proven and only selected cells are used to
perform the proof.

    -undef
        enable modelling of undef states

    -seq &lt;N&gt;
        the max. number of time steps to be considered (default = 4)

This command is very effective in proving complex sequential circuits, when
the internal state of the circuit quickly propagates to <span class="s">$</span><span class="nb">equiv cells.</span>

<span class="nb">However, this command uses a weak definition of &#39;equivalence&#39;: This command</span>
<span class="nb">proves that the two circuits will not diverge after they produce equal</span>
<span class="nb">outputs </span><span class="o">(</span><span class="nb">observable points via </span><span class="s">$</span>equiv) for at least &lt;N&gt; cycles (the &lt;N&gt;
specified via -seq).

Combined with simulation this is very powerful because simulation can give
you confidence that the circuits start out synced for at least &lt;N&gt; cycles
after reset.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>equiv<span class="k">\_</span>make -- prepare a circuit for equivalence checking<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:equiv<span class="nb">_</span>make<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    equiv<span class="nb">_</span>make [options] gold<span class="nb">_</span>module gate<span class="nb">_</span>module equiv<span class="nb">_</span>module

This creates a module annotated with <span class="s">$</span><span class="nb">equiv cells from two presumably</span>
<span class="nb">equivalent modules. Use commands such as &#39;equiv_simple&#39; and &#39;equiv_status&#39;</span>
<span class="nb">to work with the created equivalent checking module.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">inames</span>
<span class="nb">        Also match cells and wires with </span><span class="s">$</span>... names.

    -blacklist &lt;file&gt;
        Do not match cells or signals that match the names in the file.

    -encfile &lt;file&gt;
        Match FSM encodings using the description from the file.
        See &#39;help fsm<span class="nb">_</span>recode&#39; for details.

Note: The circuit created by this command is not a miter (with something like
a trigger output), but instead uses <span class="s">$</span><span class="nb">equiv cells to encode the equivalence</span>
<span class="nb">checking problem. Use &#39;miter </span><span class="o">-</span><span class="nb">equiv&#39; if you want to create a miter circuit.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{equiv</span><span class="nv">\_</span><span class="nb">mark </span><span class="o">--</span><span class="nb"> mark equivalence checking regions}</span>
<span class="nv">\label</span><span class="nb">{cmd:equiv_mark}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    equiv_mark </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command marks the regions in an equivalence checking module. Region </span><span class="m">0</span><span class="nb"> is</span>
<span class="nb">the proven part of the circuit. Regions with higher numbers are connected</span>
<span class="nb">unproven subcricuits. The integer attribute &#39;equiv_region&#39; is set on all</span>
<span class="nb">wires and cells.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{equiv</span><span class="nv">\_</span><span class="nb">miter </span><span class="o">--</span><span class="nb"> extract miter from equiv circuit}</span>
<span class="nv">\label</span><span class="nb">{cmd:equiv_miter}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    equiv_miter </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> miter_module </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This creates a miter module for further analysis of the selected </span><span class="s">$</span>equiv cells.

    -trigger
        Create a trigger output

    -cmp
        Create cmp<span class="nb">_</span>* outputs for individual unproven <span class="s">$</span><span class="nb">equiv cells</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">assert</span>
<span class="nb">        Create a </span><span class="s">$</span>assert cell for each unproven <span class="s">$</span><span class="nb">equiv cell</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">undef</span>
<span class="nb">        Create compare logic that handles undefs correctly</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{equiv</span><span class="nv">\_</span><span class="nb">opt </span><span class="o">--</span><span class="nb"> prove equivalence for optimized circuit}</span>
<span class="nv">\label</span><span class="nb">{cmd:equiv_opt}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    equiv_opt </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">command</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command uses temporal induction to check circuit equivalence before and</span>
<span class="nb">after an optimization pass.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">run &lt;from_label&gt;:&lt;to_label&gt;</span>
<span class="nb">        only run the commands between the labels </span><span class="o">(</span><span class="nb">see below</span><span class="o">)</span><span class="nb">. an empty</span>
<span class="nb">        from label is synonymous to the start of the command list, and empty to</span>
<span class="nb">        label is synonymous to the end of the command list.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">map &lt;filename&gt;</span>
<span class="nb">        expand the modules in this file before proving equivalence. this is</span>
<span class="nb">        useful for handling architecture</span><span class="o">-</span><span class="nb">specific primitives.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">blacklist &lt;file&gt;</span>
<span class="nb">        Do not match cells or signals that match the names in the file</span>
<span class="nb">        </span><span class="o">(</span><span class="nb">passed to equiv_make</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">assert</span>
<span class="nb">        produce an error if the circuits are not equivalent.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">multiclock</span>
<span class="nb">        run clk</span><span class="m">2</span><span class="nb">fflogic before equivalence checking.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">async</span><span class="m">2</span><span class="nb">sync</span>
<span class="nb">        run async</span><span class="m">2</span><span class="nb">sync before equivalence checking.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">undef</span>
<span class="nb">        enable modelling of undef states during equiv_induct.</span>

<span class="nb">The following commands are executed by this verification command:</span>

<span class="nb">    run_pass:</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">auto</span><span class="o">-</span><span class="nb">top</span>
<span class="nb">        design </span><span class="o">-</span><span class="nb">save preopt</span>
<span class="nb">        </span><span class="o">[</span><span class="nb">command</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        design </span><span class="o">-</span><span class="nb">stash postopt</span>

<span class="nb">    prepare:</span>
<span class="nb">        design </span><span class="o">-</span><span class="nb">copy</span><span class="o">-</span><span class="nb">from preopt  </span><span class="o">-</span><span class="nb">as gold A:top</span>
<span class="nb">        design </span><span class="o">-</span><span class="nb">copy</span><span class="o">-</span><span class="nb">from postopt </span><span class="o">-</span><span class="nb">as gate A:top</span>

<span class="nb">    techmap:    </span><span class="o">(</span><span class="nb">only with </span><span class="o">-</span><span class="nb">map</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">wb </span><span class="o">-</span><span class="nb">D EQUIV </span><span class="o">-</span><span class="nb">autoproc </span><span class="o">-</span><span class="nb">map &lt;filename&gt; ...</span>

<span class="nb">    prove:</span>
<span class="nb">        clk</span><span class="m">2</span><span class="nb">fflogic    </span><span class="o">(</span><span class="nb">only with </span><span class="o">-</span><span class="nb">multiclock</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        async</span><span class="m">2</span><span class="nb">sync     </span><span class="o">(</span><span class="nb">only with </span><span class="o">-</span><span class="nb">async</span><span class="m">2</span><span class="nb">sync</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        equiv_make </span><span class="o">-</span><span class="nb">blacklist &lt;filename&gt; ... gold gate equiv</span>
<span class="nb">        equiv_induct </span><span class="o">[-</span><span class="nb">undef</span><span class="o">]</span><span class="nb"> equiv</span>
<span class="nb">        equiv_status </span><span class="o">[-</span><span class="nb">assert</span><span class="o">]</span><span class="nb"> equiv</span>

<span class="nb">    restore:</span>
<span class="nb">        design </span><span class="o">-</span><span class="nb">load preopt</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{equiv</span><span class="nv">\_</span><span class="nb">purge </span><span class="o">--</span><span class="nb"> purge equivalence checking module}</span>
<span class="nv">\label</span><span class="nb">{cmd:equiv_purge}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    equiv_purge </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command removes the proven part of an equivalence checking module, leaving</span>
<span class="nb">only the unproven segments in the design. This will also remove and add module</span>
<span class="nb">ports as needed.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{equiv</span><span class="nv">\_</span><span class="nb">remove </span><span class="o">--</span><span class="nb"> remove </span><span class="nv">\$</span><span class="nb">equiv cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:equiv_remove}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    equiv_remove </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command removes the selected </span><span class="s">$</span>equiv cells. If neither -gold nor -gate is
used then only proven cells are removed.

    -gold
        keep gold circuit

    -gate
        keep gate circuit
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>equiv<span class="k">\_</span>simple -- try proving simple <span class="k">\$</span>equiv instances<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:equiv<span class="nb">_</span>simple<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    equiv<span class="nb">_</span>simple [options] [selection]

This command tries to prove <span class="s">$</span><span class="nb">equiv cells using a simple direct SAT approach.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">v</span>
<span class="nb">        verbose output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">undef</span>
<span class="nb">        enable modelling of undef states</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">short</span>
<span class="nb">        create shorter input cones that stop at shared nodes. This yields</span>
<span class="nb">        simpler SAT problems but sometimes fails to prove equivalence.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nogroup</span>
<span class="nb">        disabling grouping of </span><span class="s">$</span>equiv cells by output wire

    -seq &lt;N&gt;
        the max. number of time steps to be considered (default = 1)
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>equiv<span class="k">\_</span>status -- print status of equivalent checking module<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:equiv<span class="nb">_</span>status<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    equiv<span class="nb">_</span>status [options] [selection]

This command prints status information for all selected <span class="s">$</span><span class="nb">equiv cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">assert</span>
<span class="nb">        produce an error if any unproven </span><span class="s">$</span>equiv cell is found
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>equiv<span class="k">\_</span>struct -- structural equivalence checking<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:equiv<span class="nb">_</span>struct<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    equiv<span class="nb">_</span>struct [options] [selection]

This command adds additional <span class="s">$</span><span class="nb">equiv cells based on the assumption that the</span>
<span class="nb">gold and gate circuit are structurally equivalent. Note that this can introduce</span>
<span class="nb">bad </span><span class="s">$</span>equiv cells in cases where the netlists are not structurally equivalent,
for example when analyzing circuits with cells with commutative inputs. This
command will also de-duplicate gates.

    -fwd
        by default this command performans forward sweeps until nothing can
        be merged by forwards sweeps, then backward sweeps until forward
        sweeps are effective again. with this option set only forward sweeps
        are performed.

    -fwonly &lt;cell<span class="nb">_</span>type&gt;
        add the specified cell type to the list of cell types that are only
        merged in forward sweeps and never in backward sweeps. <span class="s">$</span><span class="nb">equiv is in</span>
<span class="nb">        this list automatically.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">icells</span>
<span class="nb">        by default, the internal RTL and gate cell types are ignored. add</span>
<span class="nb">        this option to also process those cell types with this command.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">maxiter &lt;N&gt;</span>
<span class="nb">        maximum number of iterations to run before aborting</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{eval </span><span class="o">--</span><span class="nb"> evaluate the circuit given an input}</span>
<span class="nv">\label</span><span class="nb">{cmd:eval}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    eval </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command evaluates the value of a signal given the value of all required</span>
<span class="nb">inputs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set &lt;signal&gt; &lt;value&gt;</span>
<span class="nb">        set the specified signal to the specified value.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">undef</span>
<span class="nb">        set all unspecified source signals to undef </span><span class="o">(</span><span class="nb">x</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">table &lt;signal&gt;</span>
<span class="nb">        create a truth table using the specified input signals</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">show &lt;signal&gt;</span>
<span class="nb">        show the value for the specified signal. if no </span><span class="o">-</span><span class="nb">show option is passed</span>
<span class="nb">        then all output ports of the current module are used.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{exec </span><span class="o">--</span><span class="nb"> execute commands in the operating system shell}</span>
<span class="nv">\label</span><span class="nb">{cmd:exec}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    exec </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">--</span><span class="nb"> </span><span class="o">[</span><span class="nb">command</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Execute a command in the operating system shell.  All supplied arguments are</span>
<span class="nb">concatenated and passed as a command to popen</span><span class="o">(</span><span class="m">3</span><span class="o">)</span><span class="nb">.  Whitespace is not guaranteed</span>
<span class="nb">to be preserved, even if quoted.  stdin and stderr are not connected, while stdout is</span>
<span class="nb">logged unless the &quot;</span><span class="o">-</span><span class="nb">q&quot; option is specified.</span>


<span class="nb">    </span><span class="o">-</span><span class="nb">q</span>
<span class="nb">        Suppress stdout and stderr from subprocess</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">expect</span><span class="o">-</span><span class="nb">return &lt;int&gt;</span>
<span class="nb">        Generate an error if popen</span><span class="o">()</span><span class="nb"> does not return specified value.</span>
<span class="nb">        May only be specified once; the final specified value is controlling</span>
<span class="nb">        if specified multiple times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">expect</span><span class="o">-</span><span class="nb">stdout &lt;regex&gt;</span>
<span class="nb">        Generate an error if the specified regex does not match any line</span>
<span class="nb">        in subprocess&#39;s stdout.  May be specified multiple times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">not</span><span class="o">-</span><span class="nb">expect</span><span class="o">-</span><span class="nb">stdout &lt;regex&gt;</span>
<span class="nb">        Generate an error if the specified regex matches any line</span>
<span class="nb">        in subprocess&#39;s stdout.  May be specified multiple times.</span>


<span class="nb">    Example: exec </span><span class="o">-</span><span class="nb">q </span><span class="o">-</span><span class="nb">expect</span><span class="o">-</span><span class="nb">return </span><span class="m">0</span><span class="nb"> </span><span class="o">--</span><span class="nb"> echo &quot;bananapie&quot; | grep &quot;nana&quot;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{expose </span><span class="o">--</span><span class="nb"> convert internal signals to module ports}</span>
<span class="nv">\label</span><span class="nb">{cmd:expose}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    expose </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command exposes all selected internal signals of a module as additional</span>
<span class="nb">outputs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">dff</span>
<span class="nb">        only consider wires that are directly driven by register cell.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">cut</span>
<span class="nb">        when exposing a wire, create an input</span><span class="o">/</span><span class="nb">output pair and cut the internal</span>
<span class="nb">        signal path at that wire.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">input</span>
<span class="nb">        when exposing a wire, create an input port and disconnect the internal</span>
<span class="nb">        driver.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">shared</span>
<span class="nb">        only expose those signals that are shared among the selected modules.</span>
<span class="nb">        this is useful for preparing modules for equivalence checking.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">evert</span>
<span class="nb">        also turn connections to instances of other modules to additional</span>
<span class="nb">        inputs and outputs and remove the module instances.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">evert</span><span class="o">-</span><span class="nb">dff</span>
<span class="nb">        turn flip</span><span class="o">-</span><span class="nb">flops to sets of inputs and outputs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">sep &lt;separator&gt;</span>
<span class="nb">        when creating new wire</span><span class="o">/</span><span class="nb">port names, the original object name is suffixed</span>
<span class="nb">        with this separator </span><span class="o">(</span><span class="nb">default: &#39;.&#39;</span><span class="o">)</span><span class="nb"> and the port name or a type</span>
<span class="nb">        designator for the exposed signal.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{extract </span><span class="o">--</span><span class="nb"> find subcircuits and replace them with cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:extract}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    extract </span><span class="o">-</span><span class="nb">map &lt;map_file&gt; </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    extract </span><span class="o">-</span><span class="nb">mine &lt;out_file&gt; </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass looks for subcircuits that are isomorphic to any of the modules</span>
<span class="nb">in the given map file and replaces them with instances of this modules. The</span>
<span class="nb">map file can be a Verilog source file </span><span class="o">(*</span><span class="nb">.v</span><span class="o">)</span><span class="nb"> or an ilang file </span><span class="o">(*</span><span class="nb">.il</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">map &lt;map_file&gt;</span>
<span class="nb">        use the modules in this file as reference. This option can be used</span>
<span class="nb">        multiple times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">map </span><span class="c">%&lt;design-name&gt;</span>
<span class="nb">        use the modules in this in</span><span class="o">-</span><span class="nb">memory design as reference. This option can</span>
<span class="nb">        be used multiple times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">verbose</span>
<span class="nb">        print debug output while analyzing</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">constports</span>
<span class="nb">        also find instances with constant drivers. this may be much</span>
<span class="nb">        slower than the normal operation.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nodefaultswaps</span>
<span class="nb">        normally builtin port swapping rules for internal cells are used per</span>
<span class="nb">        default. This turns that off, so e.g. &#39;a^b&#39; does not match &#39;b^a&#39;</span>
<span class="nb">        when this option is used.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">compat &lt;needle_type&gt; &lt;haystack_type&gt;</span>
<span class="nb">        Per default, the cells in the map file </span><span class="o">(</span><span class="nb">needle</span><span class="o">)</span><span class="nb"> must have the</span>
<span class="nb">        type as the cells in the active design </span><span class="o">(</span><span class="nb">haystack</span><span class="o">)</span><span class="nb">. This option</span>
<span class="nb">        can be used to register additional pairs of types that should</span>
<span class="nb">        match. This option can be used multiple times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">swap &lt;needle_type&gt; &lt;port</span><span class="m">1</span><span class="nb">&gt;,&lt;port</span><span class="m">2</span><span class="nb">&gt;</span><span class="o">[</span><span class="nb">,...</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        Register a set of swappable ports for a needle cell type.</span>
<span class="nb">        This option can be used multiple times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">perm &lt;needle_type&gt; &lt;port</span><span class="m">1</span><span class="nb">&gt;,&lt;port</span><span class="m">2</span><span class="nb">&gt;</span><span class="o">[</span><span class="nb">,...</span><span class="o">]</span><span class="nb"> &lt;portA&gt;,&lt;portB&gt;</span><span class="o">[</span><span class="nb">,...</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        Register a valid permutation of swappable ports for a needle</span>
<span class="nb">        cell type. This option can be used multiple times.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">cell_attr &lt;attribute_name&gt;</span>
<span class="nb">        Attributes on cells with the given name must match.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">wire_attr &lt;attribute_name&gt;</span>
<span class="nb">        Attributes on wires with the given name must match.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ignore_parameters</span>
<span class="nb">        Do not use parameters when matching cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ignore_param &lt;cell_type&gt; &lt;parameter_name&gt;</span>
<span class="nb">        Do not use this parameter when matching cells.</span>

<span class="nb">This pass does not operate on modules with unprocessed processes in it.</span>
<span class="o">(</span><span class="nb">I.e. the &#39;proc&#39; pass should be used first to convert processes to netlists.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">This pass can also be used for mining for frequent subcircuits. In this mode</span>
<span class="nb">the following options are to be used instead of the </span><span class="o">-</span><span class="nb">map option.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mine &lt;out_file&gt;</span>
<span class="nb">        mine for frequent subcircuits and write them to the given ilang file</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mine_cells_span &lt;min&gt; &lt;max&gt;</span>
<span class="nb">        only mine for subcircuits with the specified number of cells</span>
<span class="nb">        default value: </span><span class="m">3</span><span class="nb"> </span><span class="m">5</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mine_min_freq &lt;num&gt;</span>
<span class="nb">        only mine for subcircuits with at least the specified number of matches</span>
<span class="nb">        default value: </span><span class="m">10</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mine_limit_matches_per_module &lt;num&gt;</span>
<span class="nb">        when calculating the number of matches for a subcircuit, don&#39;t count</span>
<span class="nb">        more than the specified number of matches per module</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mine_max_fanout &lt;num&gt;</span>
<span class="nb">        don&#39;t consider internal signals with more than &lt;num&gt; connections</span>

<span class="nb">The modules in the map file may have the attribute &#39;extract_order&#39; set to an</span>
<span class="nb">integer value. Then this value is used to determine the order in which the pass</span>
<span class="nb">tries to map the modules to the design </span><span class="o">(</span><span class="nb">ascending, default value is </span><span class="m">0</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">See &#39;help techmap&#39; for a pass that does the opposite thing.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{extract</span><span class="nv">\_</span><span class="nb">counter </span><span class="o">--</span><span class="nb"> Extract GreenPak</span><span class="m">4</span><span class="nb"> counter cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:extract_counter}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    extract_counter </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass converts non</span><span class="o">-</span><span class="nb">resettable or async resettable down counters to</span>
<span class="nb">counter cells. Use a target</span><span class="o">-</span><span class="nb">specific &#39;techmap&#39; map file to convert those cells</span>
<span class="nb">to the actual target cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">maxwidth N</span>
<span class="nb">        Only extract counters up to N bits wide </span><span class="o">(</span><span class="nb">default </span><span class="m">64</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">minwidth N</span>
<span class="nb">        Only extract counters at least N bits wide </span><span class="o">(</span><span class="nb">default </span><span class="m">2</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">allow_arst yes|no</span>
<span class="nb">        Allow counters to have async reset </span><span class="o">(</span><span class="nb">default yes</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">dir up|down|both</span>
<span class="nb">        Look for up</span><span class="o">-</span><span class="nb">counters, down</span><span class="o">-</span><span class="nb">counters, or both </span><span class="o">(</span><span class="nb">default down</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">pout X,Y,...</span>
<span class="nb">        Only allow parallel output from the counter to the listed cell types</span>
<span class="nb">        </span><span class="o">(</span><span class="nb">if not specified, parallel outputs are not restricted</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{extract</span><span class="nv">\_</span><span class="nb">fa </span><span class="o">--</span><span class="nb"> find and extract full</span><span class="o">/</span><span class="nb">half adders}</span>
<span class="nv">\label</span><span class="nb">{cmd:extract_fa}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    extract_fa </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass extracts full</span><span class="o">/</span><span class="nb">half adders from a gate</span><span class="o">-</span><span class="nb">level design.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">fa, </span><span class="o">-</span><span class="nb">ha</span>
<span class="nb">        Enable cell types </span><span class="o">(</span><span class="nb">fa</span><span class="o">=</span><span class="nb">full adder, ha</span><span class="o">=</span><span class="nb">half adder</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        All types are enabled if none of this options is used</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">d &lt;int&gt;</span>
<span class="nb">        Set maximum depth for extracted logic cones </span><span class="o">(</span><span class="nb">default</span><span class="o">=</span><span class="m">20</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">b &lt;int&gt;</span>
<span class="nb">        Set maximum breadth for extracted logic cones </span><span class="o">(</span><span class="nb">default</span><span class="o">=</span><span class="m">6</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">v</span>
<span class="nb">        Verbose output</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{extract</span><span class="nv">\_</span><span class="nb">reduce </span><span class="o">--</span><span class="nb"> converts gate chains into </span><span class="nv">\$</span><span class="nb">reduce</span><span class="nv">\_</span><span class="o">*</span><span class="nb"> cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:extract_reduce}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    extract_reduce </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">converts gate chains into </span><span class="s">$</span>reduce<span class="nb">_</span>* cells

This command finds chains of <span class="s">$</span><span class="nb">_AND_, </span><span class="s">$</span><span class="nb">_</span>OR<span class="nb">_</span>, and <span class="s">$</span><span class="nb">_XOR_ cells and replaces them</span>
<span class="nb">with their corresponding </span><span class="s">$</span>reduce<span class="nb">_</span>* cells. Because this command only operates on
these cell types, it is recommended to map the design to only these cell types
using the `abc -g` command. Note that, in some cases, it may be more effective
to map the design to only <span class="s">$</span><span class="nb">_AND_ cells, run extract_reduce, map the remaining</span>
<span class="nb">parts of the design to AND</span><span class="o">/</span><span class="nb">OR</span><span class="o">/</span><span class="nb">XOR cells, and run extract_reduce a second time.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">allow</span><span class="o">-</span><span class="nb">off</span><span class="o">-</span><span class="nb">chain</span>
<span class="nb">        Allows matching of cells that have loads outside the chain. These cells</span>
<span class="nb">        will be replicated and folded into the </span><span class="s">$</span>reduce<span class="nb">_</span>* cell, but the original
        cell will remain, driving its original loads.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>extractinv -- extract explicit inverter cells for invertible cell pins<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:extractinv<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    extractinv [options] [selection]

Searches the design for all cells with invertible pins controlled by a cell
parameter (eg. IS<span class="nb">_</span>CLK<span class="nb">_</span>INVERTED on many Xilinx cells) and removes the parameter.
If the parameter was set to 1, inserts an explicit inverter cell in front of
the pin instead.  Normally used for output to ISE, which does not support the
inversion parameters.

To mark a cell port as invertible, use (* invertible<span class="nb">_</span>pin = &quot;param<span class="nb">_</span>name&quot; *)
on the wire in the blackbox module.  The parameter value should have
the same width as the port, and will be effectively XORed with it.

    -inv &lt;celltype&gt; &lt;portname<span class="nb">_</span>out&gt;:&lt;portname<span class="nb">_</span>in&gt;
        Specifies the cell type to use for the inverters and its port names.
        This option is required.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>flatten -- flatten design<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:flatten<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    flatten [options] [selection]

This pass flattens the design by replacing cells by their implementation. This
pass is very similar to the &#39;techmap&#39; pass. The only difference is that this
pass is using the current design as mapping library.

Cells and/or modules with the &#39;keep<span class="nb">_</span>hierarchy&#39; attribute set will not be
flattened by this command.

    -wb
        Ignore the &#39;whitebox&#39; attribute on cell implementations.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>flowmap -- pack LUTs with FlowMap<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:flowmap<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    flowmap [options] [selection]

This pass uses the FlowMap technology mapping algorithm to pack logic gates
into k-LUTs with optimal depth. It allows mapping any circuit elements that can
be evaluated with the `eval` pass, including cells with multiple output ports
and multi-bit input and output ports.

    -maxlut k
        perform technology mapping for a k-LUT architecture. if not specified,
        defaults to 3.

    -minlut n
        only produce n-input or larger LUTs. if not specified, defaults to 1.

    -cells &lt;cell&gt;[,&lt;cell&gt;,...]
        map specified cells. if not specified, maps <span class="s">$</span><span class="nb">_NOT_, </span><span class="s">$</span><span class="nb">_</span>AND<span class="nb">_</span>, <span class="s">$</span><span class="nb">_OR_,</span>
<span class="nb">        </span><span class="s">$</span><span class="nb">_</span>XOR<span class="nb">_</span> and <span class="s">$</span><span class="nb">_MUX_, which are the outputs of the `simplemap` pass.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">relax</span>
<span class="nb">        perform depth relaxation and area minimization.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">r</span><span class="o">-</span><span class="nb">alpha n, </span><span class="o">-</span><span class="nb">r</span><span class="o">-</span><span class="nb">beta n, </span><span class="o">-</span><span class="nb">r</span><span class="o">-</span><span class="nb">gamma n</span>
<span class="nb">        parameters of depth relaxation heuristic potential function.</span>
<span class="nb">        if not specified, alpha</span><span class="o">=</span><span class="m">8</span><span class="nb">, beta</span><span class="o">=</span><span class="m">2</span><span class="nb">, gamma</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">optarea n</span>
<span class="nb">        optimize for area by trading off at most n logic levels for fewer LUTs.</span>
<span class="nb">        n may be zero, to optimize for area without increasing depth.</span>
<span class="nb">        implies </span><span class="o">-</span><span class="nb">relax.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">debug</span>
<span class="nb">        dump intermediate graphs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">debug</span><span class="o">-</span><span class="nb">relax</span>
<span class="nb">        explain decisions performed during depth relaxation.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fmcombine </span><span class="o">--</span><span class="nb"> combine two instances of a cell into one}</span>
<span class="nv">\label</span><span class="nb">{cmd:fmcombine}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fmcombine </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> module_name gold_cell gate_cell</span>

<span class="nb">This pass takes two cells, which are instances of the same module, and replaces</span>
<span class="nb">them with one instance of a special &#39;combined&#39; module, that effectively</span>
<span class="nb">contains two copies of the original module, plus some formal properties.</span>

<span class="nb">This is useful for formal test benches that check what differences in behavior</span>
<span class="nb">a slight difference in input causes in a module.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">initeq</span>
<span class="nb">        Insert assumptions that initially all FFs in both circuits have the</span>
<span class="nb">        same initial values.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">anyeq</span>
<span class="nb">        Do not duplicate </span><span class="s">$</span>anyseq/<span class="s">$</span><span class="nb">anyconst cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">fwd</span>
<span class="nb">        Insert forward hint assumptions into the combined module.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">bwd</span>
<span class="nb">        Insert backward hint assumptions into the combined module.</span>
<span class="nb">        </span><span class="o">(</span><span class="nb">Backward hints are logically equivalend to fordward hits, but</span>
<span class="nb">        some solvers are faster with bwd hints, or even both </span><span class="o">-</span><span class="nb">bwd and </span><span class="o">-</span><span class="nb">fwd.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nop</span>
<span class="nb">        Don&#39;t insert hint assumptions into the combined module.</span>
<span class="nb">        </span><span class="o">(</span><span class="nb">This should not provide any speedup over the original design, but</span>
<span class="nb">        strangely sometimes it does.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">If none of </span><span class="o">-</span><span class="nb">fwd, </span><span class="o">-</span><span class="nb">bwd, and </span><span class="o">-</span><span class="nb">nop is given, then </span><span class="o">-</span><span class="nb">fwd is used as default.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fminit </span><span class="o">--</span><span class="nb"> set init values</span><span class="o">/</span><span class="nb">sequences for formal}</span>
<span class="nv">\label</span><span class="nb">{cmd:fminit}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fminit </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> &lt;selection&gt;</span>

<span class="nb">This pass creates init constraints </span><span class="o">(</span><span class="nb">for example for reset sequences</span><span class="o">)</span><span class="nb"> in a formal</span>
<span class="nb">model.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">seq &lt;signal&gt; &lt;sequence&gt;</span>
<span class="nb">        Set sequence using comma</span><span class="o">-</span><span class="nb">separated list of values, use &#39;z for</span>
<span class="nb">        unconstrained bits. The last value is used for the remainder of the</span>
<span class="nb">        trace.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set &lt;signal&gt; &lt;value&gt;</span>
<span class="nb">        Add constant value constraint</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">posedge &lt;signal&gt;</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">negedge &lt;signal&gt;</span>
<span class="nb">        Set clock for init sequences</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{freduce </span><span class="o">--</span><span class="nb"> perform functional reduction}</span>
<span class="nv">\label</span><span class="nb">{cmd:freduce}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    freduce </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass performs functional reduction in the circuit. I.e. if two nodes are</span>
<span class="nb">equivalent, they are merged to one node and one of the redundant drivers is</span>
<span class="nb">disconnected. A subsequent call to &#39;clean&#39; will remove the redundant drivers.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">v, </span><span class="o">-</span><span class="nb">vv</span>
<span class="nb">        enable verbose or very verbose output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">inv</span>
<span class="nb">        enable explicit handling of inverted signals</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">stop &lt;n&gt;</span>
<span class="nb">        stop after &lt;n&gt; reduction operations. this is mostly used for</span>
<span class="nb">        debugging the freduce command itself.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">dump &lt;prefix&gt;</span>
<span class="nb">        dump the design to &lt;prefix&gt;_&lt;module&gt;_&lt;num&gt;.il after each reduction</span>
<span class="nb">        operation. this is mostly used for debugging the freduce command.</span>

<span class="nb">This pass is undef</span><span class="o">-</span><span class="nb">aware, i.e. it considers don&#39;t</span><span class="o">-</span><span class="nb">care values for detecting</span>
<span class="nb">equivalent nodes.</span>

<span class="nb">All selected wires are considered for rewiring. The selected cells cover the</span>
<span class="nb">circuit that is analyzed.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm </span><span class="o">--</span><span class="nb"> extract and optimize finite state machines}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass calls all the other fsm_</span><span class="o">*</span><span class="nb"> passes in a useful order. This performs</span>
<span class="nb">FSM extraction and optimization. It also calls opt_clean as needed:</span>

<span class="nb">    fsm_detect          unless got option </span><span class="o">-</span><span class="nb">nodetect</span>
<span class="nb">    fsm_extract</span>

<span class="nb">    fsm_opt</span>
<span class="nb">    opt_clean</span>
<span class="nb">    fsm_opt</span>

<span class="nb">    fsm_expand          if got option </span><span class="o">-</span><span class="nb">expand</span>
<span class="nb">    opt_clean           if got option </span><span class="o">-</span><span class="nb">expand</span>
<span class="nb">    fsm_opt             if got option </span><span class="o">-</span><span class="nb">expand</span>

<span class="nb">    fsm_recode          unless got option </span><span class="o">-</span><span class="nb">norecode</span>

<span class="nb">    fsm_info</span>

<span class="nb">    fsm_export          if got option </span><span class="o">-</span><span class="nb">export</span>
<span class="nb">    fsm_map             unless got option </span><span class="o">-</span><span class="nb">nomap</span>

<span class="nb">Options:</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">expand, </span><span class="o">-</span><span class="nb">norecode, </span><span class="o">-</span><span class="nb">export, </span><span class="o">-</span><span class="nb">nomap</span>
<span class="nb">        enable or disable passes as indicated above</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">fullexpand</span>
<span class="nb">        call expand with </span><span class="o">-</span><span class="nb">full option</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">encoding type</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">fm_set_fsm_file file</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">encfile file</span>
<span class="nb">        passed through to fsm_recode pass</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">detect </span><span class="o">--</span><span class="nb"> finding FSMs in design}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_detect}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_detect </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass detects finite state machines by identifying the state signal.</span>
<span class="nb">The state signal is then marked by setting the attribute &#39;fsm_encoding&#39;</span>
<span class="nb">on the state signal to &quot;auto&quot;.</span>

<span class="nb">Existing &#39;fsm_encoding&#39; attributes are not changed by this pass.</span>

<span class="nb">Signals can be protected from being detected by this pass by setting the</span>
<span class="nb">&#39;fsm_encoding&#39; attribute to &quot;none&quot;.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">expand </span><span class="o">--</span><span class="nb"> expand FSM cells by merging logic into it}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_expand}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_expand </span><span class="o">[-</span><span class="nb">full</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">The fsm_extract pass is conservative about the cells that belong to a finite</span>
<span class="nb">state machine. This pass can be used to merge additional auxiliary gates into</span>
<span class="nb">the finite state machine.</span>

<span class="nb">By default, fsm_expand is still a bit conservative regarding merging larger</span>
<span class="nb">word</span><span class="o">-</span><span class="nb">wide cells. Call with </span><span class="o">-</span><span class="nb">full to consider all cells for merging.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">export </span><span class="o">--</span><span class="nb"> exporting FSMs to KISS</span><span class="m">2</span><span class="nb"> files}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_export}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_export </span><span class="o">[-</span><span class="nb">noauto</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">o filename</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">origenc</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass creates a KISS</span><span class="m">2</span><span class="nb"> file for every selected FSM. For FSMs with the</span>
<span class="nb">&#39;fsm_export&#39; attribute set, the attribute value is used as filename, otherwise</span>
<span class="nb">the module and cell name is used as filename. If the parameter &#39;</span><span class="o">-</span><span class="nb">o&#39; is given,</span>
<span class="nb">the first exported FSM is written to the specified filename. This overwrites</span>
<span class="nb">the setting as specified with the &#39;fsm_export&#39; attribute. All other FSMs are</span>
<span class="nb">exported to the default name as mentioned above.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noauto</span>
<span class="nb">        only export FSMs that have the &#39;fsm_export&#39; attribute set</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">o filename</span>
<span class="nb">        filename of the first exported FSM</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">origenc</span>
<span class="nb">        use binary state encoding as state names instead of s</span><span class="m">0</span><span class="nb">, s</span><span class="m">1</span><span class="nb">, ...</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">extract </span><span class="o">--</span><span class="nb"> extracting FSMs in design}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_extract}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_extract </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass operates on all signals marked as FSM state signals using the</span>
<span class="nb">&#39;fsm_encoding&#39; attribute. It consumes the logic that creates the state signal</span>
<span class="nb">and uses the state signal to generate control signal and replaces it with an</span>
<span class="nb">FSM cell.</span>

<span class="nb">The generated FSM cell still generates the original state signal with its</span>
<span class="nb">original encoding. The &#39;fsm_opt&#39; pass can be used in combination with the</span>
<span class="nb">&#39;opt_clean&#39; pass to eliminate this signal.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">info </span><span class="o">--</span><span class="nb"> print information on finite state machines}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_info}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_info </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass dumps all internal information on FSM cells. It can be useful for</span>
<span class="nb">analyzing the synthesis process and is called automatically by the &#39;fsm&#39;</span>
<span class="nb">pass so that this information is included in the synthesis log file.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">map </span><span class="o">--</span><span class="nb"> mapping FSMs to basic logic}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_map}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_map </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass translates FSM cells to flip</span><span class="o">-</span><span class="nb">flops and logic.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">opt </span><span class="o">--</span><span class="nb"> optimize finite state machines}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_opt}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_opt </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass optimizes FSM cells. It detects which output signals are actually</span>
<span class="nb">not used and removes them from the FSM. This pass is usually used in</span>
<span class="nb">combination with the &#39;opt_clean&#39; pass </span><span class="o">(</span><span class="nb">see also &#39;help fsm&#39;</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{fsm</span><span class="nv">\_</span><span class="nb">recode </span><span class="o">--</span><span class="nb"> recoding finite state machines}</span>
<span class="nv">\label</span><span class="nb">{cmd:fsm_recode}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    fsm_recode </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass reassign the state encodings for FSM cells. At the moment only</span>
<span class="nb">one</span><span class="o">-</span><span class="nb">hot encoding and binary encoding is supported.</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">encoding &lt;type&gt;</span>
<span class="nb">        specify the encoding scheme used for FSMs without the</span>
<span class="nb">        &#39;fsm_encoding&#39; attribute or with the attribute set to `auto&#39;.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">fm_set_fsm_file &lt;file&gt;</span>
<span class="nb">        generate a file containing the mapping from old to new FSM encoding</span>
<span class="nb">        in form of Synopsys Formality set_fsm_</span><span class="o">*</span><span class="nb"> commands.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">encfile &lt;file&gt;</span>
<span class="nb">        write the mappings from old to new FSM encoding to a file in the</span>
<span class="nb">        following format:</span>

<span class="nb">            .fsm &lt;module_name&gt; &lt;state_signal&gt;</span>
<span class="nb">            .map &lt;old_bitpattern&gt; &lt;new_bitpattern&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{greenpak</span><span class="m">4</span><span class="nv">\_</span><span class="nb">dffinv </span><span class="o">--</span><span class="nb"> merge greenpak</span><span class="m">4</span><span class="nb"> inverters and DFF</span><span class="o">/</span><span class="nb">latches}</span>
<span class="nv">\label</span><span class="nb">{cmd:greenpak</span><span class="m">4</span><span class="nb">_dffinv}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    greenpak</span><span class="m">4</span><span class="nb">_dffinv </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Merge GP_INV cells with GP_DFF</span><span class="o">*</span><span class="nb"> and GP_DLATCH</span><span class="o">*</span><span class="nb"> cells.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{help </span><span class="o">--</span><span class="nb"> display help messages}</span>
<span class="nv">\label</span><span class="nb">{cmd:help}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    help  ................  list all commands</span>
<span class="nb">    help &lt;command&gt;  ......  print help message for given command</span>
<span class="nb">    help </span><span class="o">-</span><span class="nb">all  ...........  print complete command reference</span>

<span class="nb">    help </span><span class="o">-</span><span class="nb">cells ..........  list all cell types</span>
<span class="nb">    help &lt;celltype&gt;  .....  print help message for given cell type</span>
<span class="nb">    help &lt;celltype&gt;</span><span class="o">+</span><span class="nb">  ....  print verilog code for given cell type</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{hierarchy </span><span class="o">--</span><span class="nb"> check, expand and clean up design hierarchy}</span>
<span class="nv">\label</span><span class="nb">{cmd:hierarchy}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    hierarchy </span><span class="o">[-</span><span class="nb">check</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">top &lt;module&gt;</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    hierarchy </span><span class="o">-</span><span class="nb">generate &lt;cell</span><span class="o">-</span><span class="nb">types&gt; &lt;port</span><span class="o">-</span><span class="nb">decls&gt;</span>

<span class="nb">In parametric designs, a module might exists in several variations with</span>
<span class="nb">different parameter values. This pass looks at all modules in the current</span>
<span class="nb">design an re</span><span class="o">-</span><span class="nb">runs the language frontends for the parametric modules as</span>
<span class="nb">needed. It also resolves assignments to wired logic data types </span><span class="o">(</span><span class="nb">wand</span><span class="o">/</span><span class="nb">wor</span><span class="o">)</span><span class="nb">,</span>
<span class="nb">resolves positional module parameters, unroll array instances, and more.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        also check the design hierarchy. this generates an error when</span>
<span class="nb">        an unknown module is used as cell type.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">simcheck</span>
<span class="nb">        like </span><span class="o">-</span><span class="nb">check, but also throw an error if blackbox modules are</span>
<span class="nb">        instantiated, and throw an error if the design has no top module.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">purge_lib</span>
<span class="nb">        by default the hierarchy command will not remove library </span><span class="o">(</span><span class="nb">blackbox</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        modules. use this option to also remove unused blackbox modules.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">libdir &lt;directory&gt;</span>
<span class="nb">        search for files named &lt;module_name&gt;.v in the specified directory</span>
<span class="nb">        for unknown modules and automatically run read_verilog for each</span>
<span class="nb">        unknown module.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">keep_positionals</span>
<span class="nb">        per default this pass also converts positional arguments in cells</span>
<span class="nb">        to arguments using port names. This option disables this behavior.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">keep_portwidths</span>
<span class="nb">        per default this pass adjusts the port width on cells that are</span>
<span class="nb">        module instances when the width does not match the module port. This</span>
<span class="nb">        option disables this behavior.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nodefaults</span>
<span class="nb">        do not resolve input port default values</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nokeep_asserts</span>
<span class="nb">        per default this pass sets the &quot;keep&quot; attribute on all modules</span>
<span class="nb">        that directly or indirectly contain one or more formal properties.</span>
<span class="nb">        This option disables this behavior.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top &lt;module&gt;</span>
<span class="nb">        use the specified top module to build the design hierarchy. Modules</span>
<span class="nb">        outside this tree </span><span class="o">(</span><span class="nb">unused modules</span><span class="o">)</span><span class="nb"> are removed.</span>

<span class="nb">        when the </span><span class="o">-</span><span class="nb">top option is used, the &#39;top&#39; attribute will be set on the</span>
<span class="nb">        specified top module. otherwise a module with the &#39;top&#39; attribute set</span>
<span class="nb">        will implicitly be used as top module, if such a module exists.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">auto</span><span class="o">-</span><span class="nb">top</span>
<span class="nb">        automatically determine the top of the design hierarchy and mark it.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">chparam name value </span>
<span class="nb">       elaborate the top module using this parameter value. Modules on which</span>
<span class="nb">       this parameter does not exist may cause a warning message to be output.</span>
<span class="nb">       This option can be specified multiple times to override multiple</span>
<span class="nb">       parameters. String values must be passed in double quotes </span><span class="o">(</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">In </span><span class="o">-</span><span class="nb">generate mode this pass generates blackbox modules for the given cell</span>
<span class="nb">types </span><span class="o">(</span><span class="nb">wildcards supported</span><span class="o">)</span><span class="nb">. For this the design is searched for cells that</span>
<span class="nb">match the given types and then the given port declarations are used to</span>
<span class="nb">determine the direction of the ports. The syntax for a port declaration is:</span>

<span class="nb">    {i|o|io}</span><span class="o">[</span><span class="nb">@&lt;num&gt;</span><span class="o">]</span><span class="nb">:&lt;portname&gt;</span>

<span class="nb">Input ports are specified with the &#39;i&#39; prefix, output ports with the &#39;o&#39;</span>
<span class="nb">prefix and inout ports with the &#39;io&#39; prefix. The optional &lt;num&gt; specifies</span>
<span class="nb">the position of the port in the parameter list </span><span class="o">(</span><span class="nb">needed when instantiated</span>
<span class="nb">using positional arguments</span><span class="o">)</span><span class="nb">. When &lt;num&gt; is not specified, the &lt;portname&gt; can</span>
<span class="nb">also contain wildcard characters.</span>

<span class="nb">This pass ignores the current selection and always operates on all modules</span>
<span class="nb">in the current design.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{hilomap </span><span class="o">--</span><span class="nb"> technology mapping of constant hi</span><span class="o">-</span><span class="nb"> and</span><span class="o">/</span><span class="nb">or lo</span><span class="o">-</span><span class="nb">drivers}</span>
<span class="nv">\label</span><span class="nb">{cmd:hilomap}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    hilomap </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Map constants to &#39;tielo&#39; and &#39;tiehi&#39; driver cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">hicell &lt;celltype&gt; &lt;portname&gt;</span>
<span class="nb">        Replace constant hi bits with this cell.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">locell &lt;celltype&gt; &lt;portname&gt;</span>
<span class="nb">        Replace constant lo bits with this cell.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">singleton</span>
<span class="nb">        Create only one hi</span><span class="o">/</span><span class="nb">lo cell and connect all constant bits</span>
<span class="nb">        to that cell. Per default a separate cell is created for</span>
<span class="nb">        each constant bit.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{history </span><span class="o">--</span><span class="nb"> show last interactive commands}</span>
<span class="nv">\label</span><span class="nb">{cmd:history}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    history</span>

<span class="nb">This command prints all commands in the shell history buffer. This are</span>
<span class="nb">all commands executed in an interactive session, but not the commands</span>
<span class="nb">from executed scripts.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{ice</span><span class="m">40</span><span class="nv">\_</span><span class="nb">braminit </span><span class="o">--</span><span class="nb"> iCE</span><span class="m">40</span><span class="nb">: perform SB</span><span class="nv">\_</span><span class="nb">RAM</span><span class="m">40</span><span class="nv">\_</span><span class="m">4</span><span class="nb">K initialization from file}</span>
<span class="nv">\label</span><span class="nb">{cmd:ice</span><span class="m">40</span><span class="nb">_braminit}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    ice</span><span class="m">40</span><span class="nb">_braminit</span>

<span class="nb">This command processes all SB_RAM</span><span class="m">40</span><span class="nb">_</span><span class="m">4</span><span class="nb">K blocks with a non</span><span class="o">-</span><span class="nb">empty INIT_FILE</span>
<span class="nb">parameter and converts it into the required INIT_x attributes</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{ice</span><span class="m">40</span><span class="nv">\_</span><span class="nb">dsp </span><span class="o">--</span><span class="nb"> iCE</span><span class="m">40</span><span class="nb">: map multipliers}</span>
<span class="nv">\label</span><span class="nb">{cmd:ice</span><span class="m">40</span><span class="nb">_dsp}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    ice</span><span class="m">40</span><span class="nb">_dsp </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Map multipliers </span><span class="o">(</span><span class="s">$</span>mul/SB<span class="nb">_</span>MAC16) and multiply-accumulate (<span class="s">$</span><span class="nb">mul</span><span class="o">/</span><span class="nb">SB_MAC</span><span class="m">16</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="s">$</span>add)
cells into iCE40 DSP resources.
Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.

Pack input registers (A, B, <span class="nb">{</span>C,D<span class="nb">}</span>; with optional hold), pipeline registers
(<span class="nb">{</span>F,J,K,G<span class="nb">}</span>, H), output registers (O -- full 32-bits or lower 16-bits only; with
optional hold), and post-adder into into the SB<span class="nb">_</span>MAC16 resource.

Multiply-accumulate operations using the post-adder with feedback on the <span class="nb">{</span>C,D<span class="nb">}</span>
input will be folded into the DSP. In this scenario only, resetting the
the accumulator to an arbitrary value can be inferred to use the <span class="nb">{</span>C,D<span class="nb">}</span> input.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>ice40<span class="k">\_</span>ffinit -- iCE40: handle FF init values<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:ice40<span class="nb">_</span>ffinit<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    ice40<span class="nb">_</span>ffinit [options] [selection]

Remove zero init values for FF output signals. Add inverters to implement
nonzero init values.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>ice40<span class="k">\_</span>ffssr -- iCE40: merge synchronous set/reset into FF cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:ice40<span class="nb">_</span>ffssr<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    ice40<span class="nb">_</span>ffssr [options] [selection]

Merge synchronous set/reset <span class="s">$</span><span class="nb">_MUX_ cells into iCE</span><span class="m">40</span><span class="nb"> FFs.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{ice</span><span class="m">40</span><span class="nv">\_</span><span class="nb">opt </span><span class="o">--</span><span class="nb"> iCE</span><span class="m">40</span><span class="nb">: perform simple optimizations}</span>
<span class="nv">\label</span><span class="nb">{cmd:ice</span><span class="m">40</span><span class="nb">_opt}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    ice</span><span class="m">40</span><span class="nb">_opt </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command executes the following script:</span>

<span class="nb">    do</span>
<span class="nb">        &lt;ice</span><span class="m">40</span><span class="nb"> specific optimizations&gt;</span>
<span class="nb">        opt_expr </span><span class="o">-</span><span class="nb">mux_undef </span><span class="o">-</span><span class="nb">undriven </span><span class="o">[-</span><span class="nb">full</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_merge</span>
<span class="nb">        opt_rmdff</span>
<span class="nb">        opt_clean</span>
<span class="nb">    while &lt;changed design&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{ice</span><span class="m">40</span><span class="nv">\_</span><span class="nb">wrapcarry </span><span class="o">--</span><span class="nb"> iCE</span><span class="m">40</span><span class="nb">: wrap carries}</span>
<span class="nv">\label</span><span class="nb">{cmd:ice</span><span class="m">40</span><span class="nb">_wrapcarry}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    ice</span><span class="m">40</span><span class="nb">_wrapcarry </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Wrap manually instantiated SB_CARRY cells, along with their associated SB_LUT</span><span class="m">4</span><span class="nb">s,</span>
<span class="nb">into an internal </span><span class="s">$</span><span class="nb">__</span>ICE40<span class="nb">_</span>CARRY<span class="nb">_</span>WRAPPER cell for preservation across technology
mapping.

Attributes on both cells will have their names prefixed with &#39;SB<span class="nb">_</span>CARRY.&#39; or
&#39;SB<span class="nb">_</span>LUT4.&#39; and attached to the wrapping cell.
A (* keep *) attribute on either cell will be logically OR-ed together.

    -unwrap
        unwrap <span class="s">$</span><span class="nb">__ICE</span><span class="m">40</span><span class="nb">_CARRY_WRAPPER cells back into SB_CARRYs and SB_LUT</span><span class="m">4</span><span class="nb">s,</span>
<span class="nb">        including restoring their attributes.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{insbuf </span><span class="o">--</span><span class="nb"> insert buffer cells for connected wires}</span>
<span class="nv">\label</span><span class="nb">{cmd:insbuf}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    insbuf </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Insert buffer cells into the design for directly connected wires.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">buf &lt;celltype&gt; &lt;in</span><span class="o">-</span><span class="nb">portname&gt; &lt;out</span><span class="o">-</span><span class="nb">portname&gt;</span>
<span class="nb">        Use the given cell type instead of </span><span class="s">$</span><span class="nb">_</span>BUF<span class="nb">_</span>. (Notice that the next
        call to &quot;clean&quot; will remove all <span class="s">$</span><span class="nb">_BUF_ in the design.</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{iopadmap </span><span class="o">--</span><span class="nb"> technology mapping of i</span><span class="o">/</span><span class="nb">o pads </span><span class="o">(</span><span class="nb">or buffers</span><span class="o">)</span><span class="nb">}</span>
<span class="nv">\label</span><span class="nb">{cmd:iopadmap}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    iopadmap </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Map module inputs</span><span class="o">/</span><span class="nb">outputs to PAD cells from a library. This pass</span>
<span class="nb">can only map to very simple PAD cells. Use &#39;techmap&#39; to further map</span>
<span class="nb">the resulting cells to more sophisticated PAD cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">inpad &lt;celltype&gt; &lt;portname&gt;</span><span class="o">[</span><span class="nb">:&lt;portname&gt;</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        Map module input ports to the given cell type with the</span>
<span class="nb">        given output port name. if a </span><span class="m">2</span><span class="nb">nd portname is given, the</span>
<span class="nb">        signal is passed through the pad call, using the </span><span class="m">2</span><span class="nb">nd</span>
<span class="nb">        portname as the port facing the module port.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">outpad &lt;celltype&gt; &lt;portname&gt;</span><span class="o">[</span><span class="nb">:&lt;portname&gt;</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    </span><span class="o">-</span><span class="nb">inoutpad &lt;celltype&gt; &lt;portname&gt;</span><span class="o">[</span><span class="nb">:&lt;portname&gt;</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        Similar to </span><span class="o">-</span><span class="nb">inpad, but for output and inout ports.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">toutpad &lt;celltype&gt; &lt;portname&gt;:&lt;portname&gt;</span><span class="o">[</span><span class="nb">:&lt;portname&gt;</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        Merges </span><span class="s">$</span><span class="nb">_</span>TBUF<span class="nb">_</span> cells into the output pad cell. This takes precedence
        over the other -outpad cell. The first portname is the enable input
        of the tristate driver.

    -tinoutpad &lt;celltype&gt; &lt;portname&gt;:&lt;portname&gt;:&lt;portname&gt;[:&lt;portname&gt;]
        Merges <span class="s">$</span><span class="nb">_TBUF_ cells into the inout pad cell. This takes precedence</span>
<span class="nb">        over the other </span><span class="o">-</span><span class="nb">inoutpad cell. The first portname is the enable input</span>
<span class="nb">        of the tristate driver and the </span><span class="m">2</span><span class="nb">nd portname is the internal output</span>
<span class="nb">        buffering the external signal.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ignore &lt;celltype&gt; &lt;portname&gt;</span><span class="o">[</span><span class="nb">:&lt;portname&gt;</span><span class="o">]*</span><span class="nb"></span>
<span class="nb">        Skips mapping inputs</span><span class="o">/</span><span class="nb">outputs that are already connected to given</span>
<span class="nb">        ports of the given cell.  Can be used multiple times.  This is in</span>
<span class="nb">        addition to the cells specified as mapping targets.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">widthparam &lt;param_name&gt;</span>
<span class="nb">        Use the specified parameter name to set the port width.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nameparam &lt;param_name&gt;</span>
<span class="nb">        Use the specified parameter to set the port name.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">bits</span>
<span class="nb">        create individual bit</span><span class="o">-</span><span class="nb">wide buffers even for ports that</span>
<span class="nb">        are wider. </span><span class="o">(</span><span class="nb">the default behavior is to create word</span><span class="o">-</span><span class="nb">wide</span>
<span class="nb">        buffers using </span><span class="o">-</span><span class="nb">widthparam to set the word size on the cell.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">Tristate PADS </span><span class="o">(-</span><span class="nb">toutpad, </span><span class="o">-</span><span class="nb">tinoutpad</span><span class="o">)</span><span class="nb"> always operate in </span><span class="o">-</span><span class="nb">bits mode.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{json </span><span class="o">--</span><span class="nb"> write design in JSON format}</span>
<span class="nv">\label</span><span class="nb">{cmd:json}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    json </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write a JSON netlist of all selected objects.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">o &lt;filename&gt;</span>
<span class="nb">        write to the specified file.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">aig</span>
<span class="nb">        also include AIG models for the different gate types</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">compat</span><span class="o">-</span><span class="nb">int</span>
<span class="nb">        emit </span><span class="m">32</span><span class="o">-</span><span class="nb">bit or smaller fully</span><span class="o">-</span><span class="nb">defined parameter values directly</span>
<span class="nb">        as JSON numbers </span><span class="o">(</span><span class="nb">for compatibility with old parsers</span><span class="o">)</span><span class="nb"></span>

<span class="nb">See &#39;help write_json&#39; for a description of the JSON format used.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{log </span><span class="o">--</span><span class="nb"> print text and log files}</span>
<span class="nv">\label</span><span class="nb">{cmd:log}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    log string</span>

<span class="nb">Print the given string to the screen and</span><span class="o">/</span><span class="nb">or the log file. This is useful for TCL</span>
<span class="nb">scripts, because the TCL command &quot;puts&quot; only goes to stdout but not to</span>
<span class="nb">logfiles.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">stdout</span>
<span class="nb">        Print the output to stdout too. This is useful when all Yosys is executed</span>
<span class="nb">        with a script and the </span><span class="o">-</span><span class="nb">q </span><span class="o">(</span><span class="nb">quiet operation</span><span class="o">)</span><span class="nb"> argument to notify the user.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">stderr</span>
<span class="nb">        Print the output to stderr too.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nolog</span>
<span class="nb">        Don&#39;t use the internal log</span><span class="o">()</span><span class="nb"> command. Use either </span><span class="o">-</span><span class="nb">stdout or </span><span class="o">-</span><span class="nb">stderr,</span>
<span class="nb">        otherwise no output will be generated at all.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">n</span>
<span class="nb">        do not append a newline</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{logger </span><span class="o">--</span><span class="nb"> set logger properties}</span>
<span class="nv">\label</span><span class="nb">{cmd:logger}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    logger </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command sets global logger properties, also available using command line</span>
<span class="nb">options.</span>

<span class="nb">    </span><span class="o">-[</span><span class="nb">no</span><span class="o">]</span><span class="nb">time</span>
<span class="nb">        enable</span><span class="o">/</span><span class="nb">disable display of timestamp in log output.</span>

<span class="nb">    </span><span class="o">-[</span><span class="nb">no</span><span class="o">]</span><span class="nb">stderr</span>
<span class="nb">        enable</span><span class="o">/</span><span class="nb">disable logging errors to stderr.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">warn regex</span>
<span class="nb">        print a warning for all log messages matching the regex.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nowarn regex</span>
<span class="nb">        if a warning message matches the regex, it is printed as regular</span>
<span class="nb">        message instead.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">werror regex</span>
<span class="nb">        if a warning message matches the regex, it is printed as error</span>
<span class="nb">        message instead and the tool terminates with a nonzero return code.</span>

<span class="nb">    </span><span class="o">-[</span><span class="nb">no</span><span class="o">]</span><span class="nb">debug</span>
<span class="nb">        globally enable</span><span class="o">/</span><span class="nb">disable debug log messages.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">experimental &lt;feature&gt;</span>
<span class="nb">        do not print warnings for the specified experimental feature</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">expect &lt;type&gt; &lt;regex&gt; &lt;expected_count&gt;</span>
<span class="nb">        expect log,warning or error to appear. In case of error return code is </span><span class="m">0</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">expect</span><span class="o">-</span><span class="nb">no</span><span class="o">-</span><span class="nb">warnings</span>
<span class="nb">        gives error in case there is at least one warning that is not expected.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{ls </span><span class="o">--</span><span class="nb"> list modules or objects in modules}</span>
<span class="nv">\label</span><span class="nb">{cmd:ls}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    ls </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">When no active module is selected, this prints a list of modules.</span>

<span class="nb">When an active module is selected, this prints a list of objects in the module.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{ltp </span><span class="o">--</span><span class="nb"> print longest topological path}</span>
<span class="nv">\label</span><span class="nb">{cmd:ltp}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    ltp </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command prints the longest topological path in the design. </span><span class="o">(</span><span class="nb">Only considers</span>
<span class="nb">paths within a single module, so the design must be flattened.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noff</span>
<span class="nb">        automatically exclude FF cell types</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{lut</span><span class="m">2</span><span class="nb">mux </span><span class="o">--</span><span class="nb"> convert </span><span class="nv">\$</span><span class="nb">lut to </span><span class="nv">\$\_</span><span class="nb">MUX</span><span class="nv">\_</span><span class="nb">}</span>
<span class="nv">\label</span><span class="nb">{cmd:lut</span><span class="m">2</span><span class="nb">mux}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    lut</span><span class="m">2</span><span class="nb">mux </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass converts </span><span class="s">$</span>lut cells to <span class="s">$</span><span class="nb">_MUX_ gates.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{maccmap </span><span class="o">--</span><span class="nb"> mapping macc cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:maccmap}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    maccmap </span><span class="o">[-</span><span class="nb">unmap</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass maps </span><span class="s">$</span>macc cells to yosys <span class="s">$</span><span class="nb">fa and </span><span class="s">$</span>alu cells. When the -unmap option
is used then the <span class="s">$</span><span class="nb">macc cell is mapped to </span><span class="s">$</span>add, <span class="s">$</span><span class="nb">sub, etc. cells instead.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{memory </span><span class="o">--</span><span class="nb"> translate memories to basic cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:memory}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    memory </span><span class="o">[-</span><span class="nb">nomap</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">nordff</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">memx</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">bram &lt;bram_rules&gt;</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass calls all the other memory_</span><span class="o">*</span><span class="nb"> passes in a useful order:</span>

<span class="nb">    opt_mem</span>
<span class="nb">    memory_dff </span><span class="o">[-</span><span class="nb">nordff</span><span class="o">]</span><span class="nb">                </span><span class="o">(-</span><span class="nb">memx implies </span><span class="o">-</span><span class="nb">nordff</span><span class="o">)</span><span class="nb"></span>
<span class="nb">    opt_clean</span>
<span class="nb">    memory_share</span>
<span class="nb">    opt_clean</span>
<span class="nb">    memory_memx                         </span><span class="o">(</span><span class="nb">when called with </span><span class="o">-</span><span class="nb">memx</span><span class="o">)</span><span class="nb"></span>
<span class="nb">    memory_collect</span>
<span class="nb">    memory_bram </span><span class="o">-</span><span class="nb">rules &lt;bram_rules&gt;     </span><span class="o">(</span><span class="nb">when called with </span><span class="o">-</span><span class="nb">bram</span><span class="o">)</span><span class="nb"></span>
<span class="nb">    memory_map                          </span><span class="o">(</span><span class="nb">skipped if called with </span><span class="o">-</span><span class="nb">nomap</span><span class="o">)</span><span class="nb"></span>

<span class="nb">This converts memories to word</span><span class="o">-</span><span class="nb">wide DFFs and address decoders</span>
<span class="nb">or multiport memory blocks if called with the </span><span class="o">-</span><span class="nb">nomap option.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{memory</span><span class="nv">\_</span><span class="nb">bram </span><span class="o">--</span><span class="nb"> map memories to block rams}</span>
<span class="nv">\label</span><span class="nb">{cmd:memory_bram}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    memory_bram </span><span class="o">-</span><span class="nb">rules &lt;rule_file&gt; </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass converts the multi</span><span class="o">-</span><span class="nb">port </span><span class="s">$</span>mem memory cells into block ram instances.
The given rules file describes the available resources and how they should be
used.

The rules file contains configuration options, a set of block ram description
and a sequence of match rules.

The option &#39;attr<span class="nb">_</span>icase&#39; configures how attribute values are matched. The value 0
means case-sensitive, 1 means case-insensitive.

A block ram description looks like this:

    bram RAMB1024X32     # name of BRAM cell
      init 1             # set to &#39;1&#39; if BRAM can be initialized
      abits 10           # number of address bits
      dbits 32           # number of data bits
      groups 2           # number of port groups
      ports  1 1         # number of ports in each group
      wrmode 1 0         # set to &#39;1&#39; if this groups is write ports
      enable 4 1         # number of enable bits
      transp 0 2         # transparent (for read ports)
      clocks 1 2         # clock configuration
      clkpol 2 2         # clock polarity configuration
    endbram

For the option &#39;transp&#39; the value 0 means non-transparent, 1 means transparent
and a value greater than 1 means configurable. All groups with the same
value greater than 1 share the same configuration bit.

For the option &#39;clocks&#39; the value 0 means non-clocked, and a value greater
than 0 means clocked. All groups with the same value share the same clock
signal.

For the option &#39;clkpol&#39; the value 0 means negative edge, 1 means positive edge
and a value greater than 1 means configurable. All groups with the same value
greater than 1 share the same configuration bit.

Using the same bram name in different bram blocks will create different variants
of the bram. Verilog configuration parameters for the bram are created as needed.

It is also possible to create variants by repeating statements in the bram block
and appending &#39;@&lt;label&gt;&#39; to the individual statements.

A match rule looks like this:

    match RAMB1024X32
      max waste 16384    # only use this bram if &lt;= 16k ram bits are unused
      min efficiency 80  # only use this bram if efficiency is at least 80<span class="c">%</span>
    endmatch

It is possible to match against the following values with min/max rules:

    words  ........  number of words in memory in design
    abits  ........  number of address bits on memory in design
    dbits  ........  number of data bits on memory in design
    wports  .......  number of write ports on memory in design
    rports  .......  number of read ports on memory in design
    ports  ........  number of ports on memory in design
    bits  .........  number of bits in memory in design
    dups ..........  number of duplications for more read ports

    awaste  .......  number of unused address slots for this match
    dwaste  .......  number of unused data bits for this match
    bwaste  .......  number of unused bram bits for this match
    waste  ........  total number of unused bram bits (bwaste*dups)
    efficiency  ...  total percentage of used and non-duplicated bits

    acells  .......  number of cells in &#39;address-direction&#39;
    dcells  .......  number of cells in &#39;data-direction&#39;
    cells  ........  total number of cells (acells*dcells*dups)

A match containing the command &#39;attribute&#39; followed by a list of space
separated &#39;name[=string<span class="nb">_</span>value]&#39; values requires that the memory contains any
one of the given attribute name and string values (where specified), or name
and integer 1 value (if no string<span class="nb">_</span>value given, since Verilog will interpret
&#39;(* attr *)&#39; as &#39;(* attr=1 *)&#39;).
A name prefixed with &#39;!&#39; indicates that the attribute must not exist.

The interface for the created bram instances is derived from the bram
description. Use &#39;techmap&#39; to convert the created bram instances into
instances of the actual bram cells of your target architecture.

A match containing the command &#39;or<span class="nb">_</span>next<span class="nb">_</span>if<span class="nb">_</span>better&#39; is only used if it
has a higher efficiency than the next match (and the one after that if
the next also has &#39;or<span class="nb">_</span>next<span class="nb">_</span>if<span class="nb">_</span>better&#39; set, and so forth).

A match containing the command &#39;make<span class="nb">_</span>transp&#39; will add external circuitry
to simulate &#39;transparent read&#39;, if necessary.

A match containing the command &#39;make<span class="nb">_</span>outreg&#39; will add external flip-flops
to implement synchronous read ports, if necessary.

A match containing the command &#39;shuffle<span class="nb">_</span>enable A&#39; will re-organize
the data bits to accommodate the enable pattern of port A.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>memory<span class="k">\_</span>collect -- creating multi-port memory cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:memory<span class="nb">_</span>collect<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    memory<span class="nb">_</span>collect [selection]

This pass collects memories and memory ports and creates generic multiport
memory cells.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>memory<span class="k">\_</span>dff -- merge input/output DFFs into memories<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:memory<span class="nb">_</span>dff<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    memory<span class="nb">_</span>dff [options] [selection]

This pass detects DFFs at memory ports and merges them into the memory port.
I.e. it consumes an asynchronous memory port and the flip-flops at its
interface and yields a synchronous memory port.

    -nordfff
        do not merge registers on read ports
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>memory<span class="k">\_</span>map -- translate multiport memories to basic cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:memory<span class="nb">_</span>map<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    memory<span class="nb">_</span>map [options] [selection]

This pass converts multiport memory cells as generated by the memory<span class="nb">_</span>collect
pass to word-wide DFFs and address decoders.

    -attr !&lt;name&gt;
        do not map memories that have attribute &lt;name&gt; set.

    -attr &lt;name&gt;[=&lt;value&gt;]
        for memories that have attribute &lt;name&gt; set, only map them if its value
        is a string &lt;value&gt; (if specified), or an integer 1 (otherwise). if this
        option is specified multiple times, map the memory if the attribute is
        to any of the values.

    -iattr
        for -attr, ignore case of &lt;value&gt;.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>memory<span class="k">\_</span>memx -- emulate vlog sim behavior for mem ports<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:memory<span class="nb">_</span>memx<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    memory<span class="nb">_</span>memx [selection]

This pass adds additional circuitry that emulates the Verilog simulation
behavior for out-of-bounds memory reads and writes.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>memory<span class="k">\_</span>nordff -- extract read port FFs from memories<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:memory<span class="nb">_</span>nordff<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    memory<span class="nb">_</span>nordff [options] [selection]

This pass extracts FFs from memory read ports. This results in a netlist
similar to what one would get from calling memory<span class="nb">_</span>dff with -nordff.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>memory<span class="k">\_</span>share -- consolidate memory ports<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:memory<span class="nb">_</span>share<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    memory<span class="nb">_</span>share [selection]

This pass merges share-able memory ports into single memory ports.

The following methods are used to consolidate the number of memory ports:

  - When write ports are connected to async read ports accessing the same
    address, then this feedback path is converted to a write port with
    byte/part enable signals.

  - When multiple write ports access the same address then this is converted
    to a single write port with a more complex data and/or enable logic path.

  - When multiple write ports are never accessed at the same time (a SAT
    solver is used to determine this), then the ports are merged into a single
    write port.

Note that in addition to the algorithms implemented in this pass, the <span class="s">$</span><span class="nb">memrd</span>
<span class="nb">and </span><span class="s">$</span>memwr cells are also subject to generic resource sharing passes (and other
optimizations) such as &quot;share&quot; and &quot;opt<span class="nb">_</span>merge&quot;.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>memory<span class="k">\_</span>unpack -- unpack multi-port memory cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:memory<span class="nb">_</span>unpack<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    memory<span class="nb">_</span>unpack [selection]

This pass converts the multi-port <span class="s">$</span><span class="nb">mem memory cells into individual </span><span class="s">$</span>memrd and
<span class="s">$</span><span class="nb">memwr cells. It is the counterpart to the memory_collect pass.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{miter </span><span class="o">--</span><span class="nb"> automatically create a miter circuit}</span>
<span class="nv">\label</span><span class="nb">{cmd:miter}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    miter </span><span class="o">-</span><span class="nb">equiv </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> gold_name gate_name miter_name</span>

<span class="nb">Creates a miter circuit for equivalence checking. The gold</span><span class="o">-</span><span class="nb"> and gate</span><span class="o">-</span><span class="nb"> modules</span>
<span class="nb">must have the same interfaces. The miter circuit will have all inputs of the</span>
<span class="nb">two source modules, prefixed with &#39;in_&#39;. The miter circuit has a &#39;trigger&#39;</span>
<span class="nb">output that goes high if an output mismatch between the two source modules is</span>
<span class="nb">detected.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ignore_gold_x</span>
<span class="nb">        a undef </span><span class="o">(</span><span class="nb">x</span><span class="o">)</span><span class="nb"> bit in the gold module output will match any value in</span>
<span class="nb">        the gate module output.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">make_outputs</span>
<span class="nb">        also route the gold</span><span class="o">-</span><span class="nb"> and gate</span><span class="o">-</span><span class="nb">outputs to &#39;gold_</span><span class="o">*</span><span class="nb">&#39; and &#39;gate_</span><span class="o">*</span><span class="nb">&#39; outputs</span>
<span class="nb">        on the miter circuit.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">make_outcmp</span>
<span class="nb">        also create a cmp_</span><span class="o">*</span><span class="nb"> output for each gold</span><span class="o">/</span><span class="nb">gate output pair.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">make_assert</span>
<span class="nb">        also create an &#39;assert&#39; cell that checks if trigger is always low.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">flatten</span>
<span class="nb">        call &#39;flatten </span><span class="o">-</span><span class="nb">wb; opt_expr </span><span class="o">-</span><span class="nb">keepdc </span><span class="o">-</span><span class="nb">undriven;;&#39; on the miter circuit.</span>


<span class="nb">    miter </span><span class="o">-</span><span class="nb">assert </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> module </span><span class="o">[</span><span class="nb">miter_name</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Creates a miter circuit for property checking. All input ports are kept,</span>
<span class="nb">output ports are discarded. An additional output &#39;trigger&#39; is created that</span>
<span class="nb">goes high when an assert is violated. Without a miter_name, the existing</span>
<span class="nb">module is modified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">make_outputs</span>
<span class="nb">        keep module output ports.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">flatten</span>
<span class="nb">        call &#39;flatten </span><span class="o">-</span><span class="nb">wb; opt_expr </span><span class="o">-</span><span class="nb">keepdc </span><span class="o">-</span><span class="nb">undriven;;&#39; on the miter circuit.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{mutate </span><span class="o">--</span><span class="nb"> generate or apply design mutations}</span>
<span class="nv">\label</span><span class="nb">{cmd:mutate}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    mutate </span><span class="o">-</span><span class="nb">list N </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Create a list of N mutations using an even sampling.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">o filename</span>
<span class="nb">        Write list to this file instead of console output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">s filename</span>
<span class="nb">        Write a list of all src tags found in the design to the specified file</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">seed N</span>
<span class="nb">        RNG seed for selecting mutations</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">none</span>
<span class="nb">        Include a &quot;none&quot; mutation in the output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ctrl name width value</span>
<span class="nb">        Add </span><span class="o">-</span><span class="nb">ctrl options to the output. Use &#39;value&#39; for first mutation, then</span>
<span class="nb">        simply count up from there.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mode name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">module name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">cell name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">port name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">portbit int</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">ctrlbit int</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">wire name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">wirebit int</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">src string</span>
<span class="nb">        Filter list of mutation candidates to those matching</span>
<span class="nb">        the given parameters.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">cfg option int</span>
<span class="nb">        Set a configuration option. Options available:</span>
<span class="nb">          weight_pq_w weight_pq_b weight_pq_c weight_pq_s</span>
<span class="nb">          weight_pq_mw weight_pq_mb weight_pq_mc weight_pq_ms</span>
<span class="nb">          weight_cover pick_cover_prcnt</span>


<span class="nb">    mutate </span><span class="o">-</span><span class="nb">mode MODE </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Apply the given mutation.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ctrl name width value</span>
<span class="nb">        Add a control signal with the given name and width. The mutation is</span>
<span class="nb">        activated if the control signal equals the given value.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">module name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">cell name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">port name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">portbit int</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">ctrlbit int</span>
<span class="nb">        Mutation parameters, as generated by &#39;mutate </span><span class="o">-</span><span class="nb">list N&#39;.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">wire name</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">wirebit int</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">src string</span>
<span class="nb">        Ignored. </span><span class="o">(</span><span class="nb">They are generated by </span><span class="o">-</span><span class="nb">list for documentation purposes.</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{muxcover </span><span class="o">--</span><span class="nb"> cover trees of MUX cells with wider MUXes}</span>
<span class="nv">\label</span><span class="nb">{cmd:muxcover}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    muxcover </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Cover trees of </span><span class="s">$</span><span class="nb">_</span>MUX<span class="nb">_</span> cells with <span class="s">$</span><span class="nb">_MUX{</span><span class="m">4</span><span class="nb">,</span><span class="m">8</span><span class="nb">,</span><span class="m">16</span><span class="nb">}_ cells</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mux</span><span class="m">4</span><span class="o">[=</span><span class="nb">cost</span><span class="o">]</span><span class="nb">, </span><span class="o">-</span><span class="nb">mux</span><span class="m">8</span><span class="o">[=</span><span class="nb">cost</span><span class="o">]</span><span class="nb">, </span><span class="o">-</span><span class="nb">mux</span><span class="m">16</span><span class="o">[=</span><span class="nb">cost</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        Cover </span><span class="s">$</span><span class="nb">_</span>MUX<span class="nb">_</span> trees using the specified types of MUXes (with optional
        integer costs). If none of these options are given, the effect is the
        same as if all of them are.
        Default costs: <span class="s">$</span><span class="nb">_MUX</span><span class="m">4</span><span class="nb">_ </span><span class="o">=</span><span class="nb"> </span><span class="m">220</span><span class="nb">, </span><span class="s">$</span><span class="nb">_</span>MUX8<span class="nb">_</span> = 460, 
                       <span class="s">$</span><span class="nb">_MUX</span><span class="m">16</span><span class="nb">_ </span><span class="o">=</span><span class="nb"> </span><span class="m">940</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mux</span><span class="m">2</span><span class="o">=</span><span class="nb">cost</span>
<span class="nb">        Use the specified cost for </span><span class="s">$</span><span class="nb">_</span>MUX<span class="nb">_</span> cells when making covering decisions.
        Default cost: <span class="s">$</span><span class="nb">_MUX_ </span><span class="o">=</span><span class="nb"> </span><span class="m">100</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">dmux</span><span class="o">=</span><span class="nb">cost</span>
<span class="nb">        Use the specified cost for </span><span class="s">$</span><span class="nb">_</span>MUX<span class="nb">_</span> cells used in decoders.
        Default cost: 90

    -nodecode
        Do not insert decoder logic. This reduces the number of possible
        substitutions, but guarantees that the resulting circuit is not
        less efficient than the original circuit.

    -nopartial
        Do not consider mappings that use <span class="s">$</span><span class="nb">_MUX&lt;N&gt;_ to select from less</span>
<span class="nb">        than &lt;N&gt; different signals.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{muxpack </span><span class="o">--</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">mux</span><span class="o">/</span><span class="nv">\$</span><span class="nb">pmux cascades to </span><span class="nv">\$</span><span class="nb">pmux}</span>
<span class="nv">\label</span><span class="nb">{cmd:muxpack}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    muxpack </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass converts cascaded chains of </span><span class="s">$</span>pmux cells (e.g. those create from case
constructs) and <span class="s">$</span><span class="nb">mux cells </span><span class="o">(</span><span class="nb">e.g. those created by if</span><span class="o">-</span><span class="nb">else constructs</span><span class="o">)</span><span class="nb"> into</span>
<span class="s">$</span>pmux cells.

This optimisation is conservative --- it will only pack <span class="s">$</span><span class="nb">mux or </span><span class="s">$</span>pmux cells
whose select lines are driven by &#39;<span class="s">$</span><span class="nb">eq&#39; cells with other such cells if it can be</span>
<span class="nb">certain that their select inputs are mutually exclusive.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{nlutmap </span><span class="o">--</span><span class="nb"> map to LUTs of different sizes}</span>
<span class="nv">\label</span><span class="nb">{cmd:nlutmap}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    nlutmap </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass uses successive calls to &#39;abc&#39; to map to an architecture. That</span>
<span class="nb">provides a small number of differently sized LUTs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">luts N_</span><span class="m">1</span><span class="nb">,N_</span><span class="m">2</span><span class="nb">,N_</span><span class="m">3</span><span class="nb">,...</span>
<span class="nb">        The number of LUTs with </span><span class="m">1</span><span class="nb">, </span><span class="m">2</span><span class="nb">, </span><span class="m">3</span><span class="nb">, ... inputs that are</span>
<span class="nb">        available in the target architecture.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">assert</span>
<span class="nb">        Create an error if not all logic can be mapped</span>

<span class="nb">Excess logic that does not fit into the specified LUTs is mapped back</span>
<span class="nb">to generic logic gates </span><span class="o">(</span><span class="s">$</span><span class="nb">_</span>AND<span class="nb">_</span>, etc.).
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>onehot -- optimize <span class="k">\$</span>eq cells for onehot signals<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:onehot<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    onehot [options] [selection]

This pass optimizes <span class="s">$</span><span class="nb">eq cells that compare one</span><span class="o">-</span><span class="nb">hot signals against constants</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">v, </span><span class="o">-</span><span class="nb">vv</span>
<span class="nb">        verbose output</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{opt </span><span class="o">--</span><span class="nb"> perform simple optimizations}</span>
<span class="nv">\label</span><span class="nb">{cmd:opt}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    opt </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass calls all the other opt_</span><span class="o">*</span><span class="nb"> passes in a useful order. This performs</span>
<span class="nb">a series of trivial optimizations and cleanups. This pass executes the other</span>
<span class="nb">passes in the following order:</span>

<span class="nb">    opt_expr </span><span class="o">[-</span><span class="nb">mux_undef</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">mux_bool</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">undriven</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">clkinv</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">fine</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">full</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">keepdc</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    opt_merge </span><span class="o">[-</span><span class="nb">share_all</span><span class="o">]</span><span class="nb"> </span><span class="o">-</span><span class="nb">nomux</span>

<span class="nb">    do</span>
<span class="nb">        opt_muxtree</span>
<span class="nb">        opt_reduce </span><span class="o">[-</span><span class="nb">fine</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">full</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_merge </span><span class="o">[-</span><span class="nb">share_all</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_share </span><span class="o">(-</span><span class="nb">full only</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        opt_rmdff </span><span class="o">[-</span><span class="nb">keepdc</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">sat</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_clean </span><span class="o">[-</span><span class="nb">purge</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_expr </span><span class="o">[-</span><span class="nb">mux_undef</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">mux_bool</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">undriven</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">clkinv</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">fine</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">full</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">keepdc</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    while &lt;changed design&gt;</span>

<span class="nb">When called with </span><span class="o">-</span><span class="nb">fast the following script is used instead:</span>

<span class="nb">    do</span>
<span class="nb">        opt_expr </span><span class="o">[-</span><span class="nb">mux_undef</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">mux_bool</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">undriven</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">clkinv</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">fine</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">full</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">keepdc</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_merge </span><span class="o">[-</span><span class="nb">share_all</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_rmdff </span><span class="o">[-</span><span class="nb">keepdc</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">sat</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_clean </span><span class="o">[-</span><span class="nb">purge</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    while &lt;changed design in opt_rmdff&gt;</span>

<span class="nb">Note: Options in square brackets </span><span class="o">(</span><span class="nb">such as </span><span class="o">[-</span><span class="nb">keepdc</span><span class="o">])</span><span class="nb"> are passed through to</span>
<span class="nb">the opt_</span><span class="o">*</span><span class="nb"> commands when given to &#39;opt&#39;.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{opt</span><span class="nv">\_</span><span class="nb">clean </span><span class="o">--</span><span class="nb"> remove unused cells and wires}</span>
<span class="nv">\label</span><span class="nb">{cmd:opt_clean}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    opt_clean </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass identifies wires and cells that are unused and removes them. Other</span>
<span class="nb">passes often remove cells but leave the wires in the design or reconnect the</span>
<span class="nb">wires but leave the old cells in the design. This pass can be used to clean up</span>
<span class="nb">after the passes that do the actual work.</span>

<span class="nb">This pass only operates on completely selected modules without processes.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">purge</span>
<span class="nb">        also remove internal nets if they have a public name</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{opt</span><span class="nv">\_</span><span class="nb">demorgan </span><span class="o">--</span><span class="nb"> Optimize reductions with DeMorgan equivalents}</span>
<span class="nv">\label</span><span class="nb">{cmd:opt_demorgan}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    opt_demorgan </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass pushes inverters through </span><span class="s">$</span>reduce<span class="nb">_</span>* cells if this will reduce the
overall gate count of the circuit
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>expr -- perform const folding and simple expression rewriting<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>expr<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>expr [options] [selection]

This pass performs const folding on internal cell types with constant inputs.
It also performs some simple expression rewriting.

    -mux<span class="nb">_</span>undef
        remove &#39;undef&#39; inputs from <span class="s">$</span><span class="nb">mux, </span><span class="s">$</span>pmux and <span class="s">$</span><span class="nb">_MUX_ cells</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">mux_bool</span>
<span class="nb">        replace </span><span class="s">$</span>mux cells with inverters or buffers when possible

    -undriven
        replace undriven nets with undef (x) constants

    -clkinv
        optimize clock inverters by changing FF types

    -fine
        perform fine-grain optimizations

    -full
        alias for -mux<span class="nb">_</span>undef -mux<span class="nb">_</span>bool -undriven -fine

    -keepdc
        some optimizations change the behavior of the circuit with respect to
        don&#39;t-care bits. for example in &#39;a+0&#39; a single x-bit in &#39;a&#39; will cause
        all result bits to be set to x. this behavior changes when &#39;a+0&#39; is
        replaced by &#39;a&#39;. the -keepdc option disables all such optimizations.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>lut -- optimize LUT cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>lut<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>lut [options] [selection]

This pass combines cascaded <span class="s">$</span><span class="nb">lut cells with unused inputs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">dlogic &lt;type&gt;:&lt;cell</span><span class="o">-</span><span class="nb">port&gt;</span><span class="o">=</span><span class="nb">&lt;LUT</span><span class="o">-</span><span class="nb">input&gt;</span><span class="o">[</span><span class="nb">:&lt;cell</span><span class="o">-</span><span class="nb">port&gt;</span><span class="o">=</span><span class="nb">&lt;LUT</span><span class="o">-</span><span class="nb">input&gt;...</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        preserve connections to dedicated logic cell &lt;type&gt; that has ports</span>
<span class="nb">        &lt;cell</span><span class="o">-</span><span class="nb">port&gt; connected to LUT inputs &lt;LUT</span><span class="o">-</span><span class="nb">input&gt;. this includes</span>
<span class="nb">        the case where both LUT and dedicated logic input are connected to</span>
<span class="nb">        the same constant.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">limit N</span>
<span class="nb">        only perform the first N combines, then stop. useful for debugging.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{opt</span><span class="nv">\_</span><span class="nb">lut</span><span class="nv">\_</span><span class="nb">ins </span><span class="o">--</span><span class="nb"> discard unused LUT inputs}</span>
<span class="nv">\label</span><span class="nb">{cmd:opt_lut_ins}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    opt_lut_ins </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass removes unused inputs from LUT cells </span><span class="o">(</span><span class="nb">that is, inputs that can not</span>
<span class="nb">influence the output signal given this LUT&#39;s value</span><span class="o">)</span><span class="nb">.  While such LUTs cannot</span>
<span class="nb">be directly emitted by ABC, they can be a result of various post</span><span class="o">-</span><span class="nb">ABC</span>
<span class="nb">transformations, such as mapping wide LUTs </span><span class="o">(</span><span class="nb">not all sub</span><span class="o">-</span><span class="nb">LUTs will use the</span>
<span class="nb">full set of inputs</span><span class="o">)</span><span class="nb"> or optimizations such as xilinx_dffopt.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">tech &lt;technology&gt;</span>
<span class="nb">        Instead of generic </span><span class="s">$</span>lut cells, operate on LUT cells specific
        to the given technology.  Valid values are: xilinx, ecp5, gowin.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>mem -- optimize memories<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>mem<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>mem [options] [selection]

This pass performs various optimizations on memories in the design.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>merge -- consolidate identical cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>merge<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>merge [options] [selection]

This pass identifies cells with identical type and input signals. Such cells
are then merged to one cell.

    -nomux
        Do not merge MUX cells.

    -share<span class="nb">_</span>all
        Operate on all cell types, not just built-in types.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>muxtree -- eliminate dead trees in multiplexer trees<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>muxtree<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>muxtree [selection]

This pass analyzes the control signals for the multiplexer trees in the design
and identifies inputs that can never be active. It then removes this dead
branches from the multiplexer trees.

This pass only operates on completely selected modules without processes.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>reduce -- simplify large MUXes and AND/OR gates<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>reduce<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>reduce [options] [selection]

This pass performs two interlinked optimizations:

1. it consolidates trees of large AND gates or OR gates and eliminates
duplicated inputs.

2. it identifies duplicated inputs to MUXes and replaces them with a single
input with the original control signals OR&#39;ed together.

    -fine
      perform fine-grain optimizations

    -full
      alias for -fine
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>rmdff -- remove DFFs with constant inputs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>rmdff<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>rmdff [-keepdc] [-sat] [selection]

This pass identifies flip-flops with constant inputs and replaces them with
a constant driver.

    -sat
        additionally invoke SAT solver to detect and remove flip-flops (with 
        non-constant inputs) that can also be replaced with a constant driver
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>opt<span class="k">\_</span>share -- merge mutually exclusive cells of the same type that share an input signal<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:opt<span class="nb">_</span>share<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    opt<span class="nb">_</span>share [selection]

This pass identifies mutually exclusive cells of the same type that:
    (a) share an input signal,
    (b) drive the same <span class="s">$</span><span class="nb">mux, </span><span class="s">$</span><span class="nb">_</span>MUX<span class="nb">_</span>, or <span class="s">$</span><span class="nb">pmux multiplexing cell,</span>

<span class="nb">allowing the cell to be merged and the multiplexer to be moved from</span>
<span class="nb">multiplexing its output to multiplexing the non</span><span class="o">-</span><span class="nb">shared input signals.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{paramap </span><span class="o">--</span><span class="nb"> renaming cell parameters}</span>
<span class="nv">\label</span><span class="nb">{cmd:paramap}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    paramap </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command renames cell parameters and</span><span class="o">/</span><span class="nb">or maps key</span><span class="o">/</span><span class="nb">value pairs to</span>
<span class="nb">other key</span><span class="o">/</span><span class="nb">value pairs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">tocase &lt;name&gt;</span>
<span class="nb">        Match attribute names case</span><span class="o">-</span><span class="nb">insensitively and set it to the specified</span>
<span class="nb">        name.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">rename &lt;old_name&gt; &lt;new_name&gt;</span>
<span class="nb">        Rename attributes as specified</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">map &lt;old_name&gt;</span><span class="o">=</span><span class="nb">&lt;old_value&gt; &lt;new_name&gt;</span><span class="o">=</span><span class="nb">&lt;new_value&gt;</span>
<span class="nb">        Map key</span><span class="o">/</span><span class="nb">value pairs as indicated.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">imap &lt;old_name&gt;</span><span class="o">=</span><span class="nb">&lt;old_value&gt; &lt;new_name&gt;</span><span class="o">=</span><span class="nb">&lt;new_value&gt;</span>
<span class="nb">        Like </span><span class="o">-</span><span class="nb">map, but use case</span><span class="o">-</span><span class="nb">insensitive match for &lt;old_value&gt; when</span>
<span class="nb">        it is a string value.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">remove &lt;name&gt;</span><span class="o">=</span><span class="nb">&lt;value&gt;</span>
<span class="nb">        Remove attributes matching this pattern.</span>

<span class="nb">For example, mapping Diamond</span><span class="o">-</span><span class="nb">style ECP</span><span class="m">5</span><span class="nb"> &quot;init&quot; attributes to Yosys</span><span class="o">-</span><span class="nb">style:</span>

<span class="nb">    paramap </span><span class="o">-</span><span class="nb">tocase INIT t:LUT</span><span class="m">4</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{peepopt </span><span class="o">--</span><span class="nb"> collection of peephole optimizers}</span>
<span class="nv">\label</span><span class="nb">{cmd:peepopt}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    peepopt </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass applies a collection of peephole optimizers to the current design.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{plugin </span><span class="o">--</span><span class="nb"> load and list loaded plugins}</span>
<span class="nv">\label</span><span class="nb">{cmd:plugin}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    plugin </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Load and list loaded plugins.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">i &lt;plugin_filename&gt;</span>
<span class="nb">        Load </span><span class="o">(</span><span class="nb">install</span><span class="o">)</span><span class="nb"> the specified plugin.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">a &lt;alias_name&gt;</span>
<span class="nb">        Register the specified alias name for the loaded plugin</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">l</span>
<span class="nb">        List loaded plugins</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{pmux</span><span class="m">2</span><span class="nb">shiftx </span><span class="o">--</span><span class="nb"> transform </span><span class="nv">\$</span><span class="nb">pmux cells to </span><span class="nv">\$</span><span class="nb">shiftx cells}</span>
<span class="nv">\label</span><span class="nb">{cmd:pmux</span><span class="m">2</span><span class="nb">shiftx}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    pmux</span><span class="m">2</span><span class="nb">shiftx </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass transforms </span><span class="s">$</span>pmux cells to <span class="s">$</span><span class="nb">shiftx cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">v, </span><span class="o">-</span><span class="nb">vv</span>
<span class="nb">        verbose output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">min_density &lt;percentage&gt;</span>
<span class="nb">        specifies the minimum density for the shifter</span>
<span class="nb">        default: </span><span class="m">50</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">min_choices &lt;int&gt;</span>
<span class="nb">        specified the minimum number of choices for a control signal</span>
<span class="nb">        default: </span><span class="m">3</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">onehot ignore|pmux|shiftx</span>
<span class="nb">        select strategy for one</span><span class="o">-</span><span class="nb">hot encoded control signals</span>
<span class="nb">        default: pmux</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">norange</span>
<span class="nb">        disable </span><span class="s">$</span>sub inference for &quot;range decoders&quot;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>pmuxtree -- transform <span class="k">\$</span>pmux cells to trees of <span class="k">\$</span>mux cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:pmuxtree<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    pmuxtree [selection]

This pass transforms <span class="s">$</span><span class="nb">pmux cells to trees of </span><span class="s">$</span>mux cells.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>portlist -- list (top-level) ports<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:portlist<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    portlist [options] [selection]

This command lists all module ports found in the selected modules.

If no selection is provided then it lists the ports on the top module.

  -m
    print verilog blackbox module definitions instead of port lists
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>prep -- generic synthesis script<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:prep<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    prep [options]

This command runs a conservative RTL synthesis. A typical application for this
is the preparation stage of a verification flow. This command does not operate
on partly selected designs.

    -top &lt;module&gt;
        use the specified module as top module (default=&#39;top&#39;)

    -auto-top
        automatically determine the top of the design hierarchy

    -flatten
        flatten the design before synthesis. this will pass &#39;-auto-top&#39; to
        &#39;hierarchy&#39; if no top module is specified.

    -ifx
        passed to &#39;proc&#39;. uses verilog simulation behavior for verilog if/case
        undef handling. this also prevents &#39;wreduce&#39; from being run.

    -memx
        simulate verilog simulation behavior for out-of-bounds memory accesses
        using the &#39;memory<span class="nb">_</span>memx&#39; pass.

    -nomem
        do not run any of the memory<span class="nb">_</span>* passes

    -rdff
        do not pass -nordff to &#39;memory<span class="nb">_</span>dff&#39;. This enables merging of FFs into
        memory read ports.

    -nokeepdc
        do not call opt<span class="nb">_</span>* with -keepdc

    -run &lt;from<span class="nb">_</span>label&gt;[:&lt;to<span class="nb">_</span>label&gt;]
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.


The following commands are executed by this synthesis command:

    begin:
        hierarchy -check [-top &lt;top&gt; | -auto-top]

    coarse:
        proc [-ifx]
        flatten    (if -flatten)
        opt<span class="nb">_</span>expr -keepdc
        opt<span class="nb">_</span>clean
        check
        opt -keepdc
        wreduce -keepdc [-memx]
        memory<span class="nb">_</span>dff [-nordff]
        memory<span class="nb">_</span>memx    (if -memx)
        opt<span class="nb">_</span>clean
        memory<span class="nb">_</span>collect
        opt -keepdc -fast

    check:
        stat
        check
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc -- translate processes to netlists<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc [options] [selection]

This pass calls all the other proc<span class="nb">_</span>* passes in the most common order.

    proc<span class="nb">_</span>clean
    proc<span class="nb">_</span>rmdead
    proc<span class="nb">_</span>prune
    proc<span class="nb">_</span>init
    proc<span class="nb">_</span>arst
    proc<span class="nb">_</span>mux
    proc<span class="nb">_</span>dlatch
    proc<span class="nb">_</span>dff
    proc<span class="nb">_</span>clean

This replaces the processes in the design with multiplexers,
flip-flops and latches.

The following options are supported:

    -global<span class="nb">_</span>arst [!]&lt;netname&gt;
        This option is passed through to proc<span class="nb">_</span>arst.

    -ifx
        This option is passed through to proc<span class="nb">_</span>mux. proc<span class="nb">_</span>rmdead is not
        executed in -ifx mode.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>arst -- detect asynchronous resets<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>arst<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>arst [-global<span class="nb">_</span>arst [!]&lt;netname&gt;] [selection]

This pass identifies asynchronous resets in the processes and converts them
to a different internal representation that is suitable for generating
flip-flop cells with asynchronous resets.

    -global<span class="nb">_</span>arst [!]&lt;netname&gt;
        In modules that have a net with the given name, use this net as async
        reset for registers that have been assign initial values in their
        declaration (&#39;reg foobar = constant<span class="nb">_</span>value;&#39;). Use the &#39;!&#39; modifier for
        active low reset signals. Note: the frontend stores the default value
        in the &#39;init&#39; attribute on the net.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>clean -- remove empty parts of processes<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>clean<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>clean [options] [selection]

    -quiet
        do not print any messages.

This pass removes empty parts of processes and ultimately removes a process
if it contains only empty structures.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>dff -- extract flip-flops from processes<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>dff<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>dff [selection]

This pass identifies flip-flops in the processes and converts them to
d-type flip-flop cells.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>dlatch -- extract latches from processes<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>dlatch<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>dlatch [selection]

This pass identifies latches in the processes and converts them to
d-type latches.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>init -- convert initial block to init attributes<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>init<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>init [selection]

This pass extracts the &#39;init&#39; actions from processes (generated from Verilog
&#39;initial&#39; blocks) and sets the initial value to the &#39;init&#39; attribute on the
respective wire.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>mux -- convert decision trees to multiplexers<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>mux<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>mux [options] [selection]

This pass converts the decision trees in processes (originating from if-else
and case statements) to trees of multiplexer cells.

    -ifx
        Use Verilog simulation behavior with respect to undef values in
        &#39;case&#39; expressions and &#39;if&#39; conditions.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>prune -- remove redundant assignments<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>prune<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>prune [selection]

This pass identifies assignments in processes that are always overwritten by
a later assignment to the same signal and removes them.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>proc<span class="k">\_</span>rmdead -- eliminate dead trees in decision trees<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:proc<span class="nb">_</span>rmdead<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    proc<span class="nb">_</span>rmdead [selection]

This pass identifies unreachable branches in decision trees and removes them.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>qwp -- quadratic wirelength placer<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:qwp<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    qwp [options] [selection]

This command runs quadratic wirelength placement on the selected modules and
annotates the cells in the design with &#39;qwp<span class="nb">_</span>position&#39; attributes.

    -ltr
        Add left-to-right constraints: constrain all inputs on the left border
        outputs to the right border.

    -alpha
        Add constraints for inputs/outputs to be placed in alphanumerical
        order along the y-axis (top-to-bottom).

    -grid N
        Number of grid divisions in x- and y-direction. (default=16)

    -dump &lt;html<span class="nb">_</span>file<span class="nb">_</span>name&gt;
        Dump a protocol of the placement algorithm to the html file.

    -v
        Verbose solver output for profiling or debugging

Note: This implementation of a quadratic wirelength placer uses exact
dense matrix operations. It is only a toy-placer for small circuits.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>read -- load HDL designs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:read<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    read <span class="nb">{</span>-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal<span class="nb">}</span> &lt;verilog-file&gt;..

Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support
is only available via Verific.)

Additional -D&lt;macro&gt;[=&lt;value&gt;] options may be added after the option indicating
the language version (and before file names) to set additional verilog defines.


    read <span class="nb">{</span>-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl<span class="nb">}</span> &lt;vhdl-file&gt;..

Load the specified VHDL files. (Requires Verific.)


    read -define &lt;macro&gt;[=&lt;value&gt;]..

Set global Verilog/SystemVerilog defines.


    read -undef &lt;macro&gt;..

Unset global Verilog/SystemVerilog defines.


    read -incdir &lt;directory&gt;

Add directory to global Verilog/SystemVerilog include directories.


    read -verific
    read -noverific

Subsequent calls to &#39;read&#39; will either use or not use Verific. Calling &#39;read&#39;
with -verific will result in an error on Yosys binaries that are built without
Verific support. The default is to use Verific if it is available.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>read<span class="k">\_</span>aiger -- read AIGER file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:read<span class="nb">_</span>aiger<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    read<span class="nb">_</span>aiger [options] [filename]

Load module from an AIGER file into the current design.

    -module<span class="nb">_</span>name &lt;module<span class="nb">_</span>name&gt;
        name of module to be created (default: &lt;filename&gt;)

    -clk<span class="nb">_</span>name &lt;wire<span class="nb">_</span>name&gt;
        if specified, AIGER latches to be transformed into <span class="s">$</span><span class="nb">_DFF_P_ cells</span>
<span class="nb">        clocked by wire of this name. otherwise, </span><span class="s">$</span><span class="nb">_</span>FF<span class="nb">_</span> cells will be used

    -map &lt;filename&gt;
        read file with port and latch symbols

    -wideports
        merge ports that match the pattern &#39;name[int]&#39; into a single
        multi-bit port &#39;name&#39;

    -xaiger
        read XAIGER extensions
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>read<span class="k">\_</span>blif -- read BLIF file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:read<span class="nb">_</span>blif<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    read<span class="nb">_</span>blif [options] [filename]

Load modules from a BLIF file into the current design.

    -sop
        Create <span class="s">$</span><span class="nb">sop cells instead of </span><span class="s">$</span>lut cells

    -wideports
        Merge ports that match the pattern &#39;name[int]&#39; into a single
        multi-bit port &#39;name&#39;.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>read<span class="k">\_</span>ilang -- read modules from ilang file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:read<span class="nb">_</span>ilang<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    read<span class="nb">_</span>ilang [filename]

Load modules from an ilang file to the current design. (ilang is a text
representation of a design in yosys&#39;s internal format.)

    -nooverwrite
        ignore re-definitions of modules. (the default behavior is to
        create an error message if the existing module is not a blackbox
        module, and overwrite the existing module if it is a blackbox module.)

    -overwrite
        overwrite existing modules with the same name

    -lib
        only create empty blackbox modules
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>read<span class="k">\_</span>json -- read JSON file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:read<span class="nb">_</span>json<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    read<span class="nb">_</span>json [filename]

Load modules from a JSON file into the current design See &quot;help write<span class="nb">_</span>json&quot;
for a description of the file format.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>read<span class="k">\_</span>liberty -- read cells from liberty file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:read<span class="nb">_</span>liberty<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    read<span class="nb">_</span>liberty [filename]

Read cells from liberty file as modules into current design.

    -lib
        only create empty blackbox modules

    -nooverwrite
        ignore re-definitions of modules. (the default behavior is to
        create an error message if the existing module is not a blackbox
        module, and overwrite the existing module if it is  a blackbox module.)

    -overwrite
        overwrite existing modules with the same name

    -ignore<span class="nb">_</span>miss<span class="nb">_</span>func
        ignore cells with missing function specification of outputs

    -ignore<span class="nb">_</span>miss<span class="nb">_</span>dir
        ignore cells with a missing or invalid direction
        specification on a pin

    -ignore<span class="nb">_</span>miss<span class="nb">_</span>data<span class="nb">_</span>latch
        ignore latches with missing data and/or enable pins

    -setattr &lt;attribute<span class="nb">_</span>name&gt;
        set the specified attribute (to the value 1) on all loaded modules
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>read<span class="k">\_</span>verilog -- read modules from Verilog file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:read<span class="nb">_</span>verilog<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    read<span class="nb">_</span>verilog [options] [filename]

Load modules from a Verilog file to the current design. A large subset of
Verilog-2005 is supported.

    -sv
        enable support for SystemVerilog features. (only a small subset
        of SystemVerilog is supported)

    -formal
        enable support for SystemVerilog assertions and some Yosys extensions
        replace the implicit -D SYNTHESIS with -D FORMAL

    -noassert
        ignore assert() statements

    -noassume
        ignore assume() statements

    -norestrict
        ignore restrict() statements

    -assume-asserts
        treat all assert() statements like assume() statements

    -assert-assumes
        treat all assume() statements like assert() statements

    -debug
        alias for -dump<span class="nb">_</span>ast1 -dump<span class="nb">_</span>ast2 -dump<span class="nb">_</span>vlog1 -dump<span class="nb">_</span>vlog2 -yydebug

    -dump<span class="nb">_</span>ast1
        dump abstract syntax tree (before simplification)

    -dump<span class="nb">_</span>ast2
        dump abstract syntax tree (after simplification)

    -no<span class="nb">_</span>dump<span class="nb">_</span>ptr
        do not include hex memory addresses in dump (easier to diff dumps)

    -dump<span class="nb">_</span>vlog1
        dump ast as Verilog code (before simplification)

    -dump<span class="nb">_</span>vlog2
        dump ast as Verilog code (after simplification)

    -dump<span class="nb">_</span>rtlil
        dump generated RTLIL netlist

    -yydebug
        enable parser debug output

    -nolatches
        usually latches are synthesized into logic loops
        this option prohibits this and sets the output to &#39;x&#39;
        in what would be the latches hold condition

        this behavior can also be achieved by setting the
        &#39;nolatches&#39; attribute on the respective module or
        always block.

    -nomem2reg
        under certain conditions memories are converted to registers
        early during simplification to ensure correct handling of
        complex corner cases. this option disables this behavior.

        this can also be achieved by setting the &#39;nomem2reg&#39;
        attribute on the respective module or register.

        This is potentially dangerous. Usually the front-end has good
        reasons for converting an array to a list of registers.
        Prohibiting this step will likely result in incorrect synthesis
        results.

    -mem2reg
        always convert memories to registers. this can also be
        achieved by setting the &#39;mem2reg&#39; attribute on the respective
        module or register.

    -nomeminit
        do not infer <span class="s">$</span><span class="nb">meminit cells and instead convert initialized</span>
<span class="nb">        memories to registers directly in the front</span><span class="o">-</span><span class="nb">end.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ppdump</span>
<span class="nb">        dump Verilog code after pre</span><span class="o">-</span><span class="nb">processor</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nopp</span>
<span class="nb">        do not run the pre</span><span class="o">-</span><span class="nb">processor</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nodpi</span>
<span class="nb">        disable DPI</span><span class="o">-</span><span class="nb">C support</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noblackbox</span>
<span class="nb">        do not automatically add a </span><span class="o">(*</span><span class="nb"> blackbox </span><span class="o">*)</span><span class="nb"> attribute to an</span>
<span class="nb">        empty module.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">lib</span>
<span class="nb">        only create empty blackbox modules. This implies </span><span class="o">-</span><span class="nb">DBLACKBOX.</span>
<span class="nb">        modules with the </span><span class="o">(*</span><span class="nb"> whitebox </span><span class="o">*)</span><span class="nb"> attribute will be preserved.</span>
<span class="nb">        </span><span class="o">(*</span><span class="nb"> lib_whitebox </span><span class="o">*)</span><span class="nb"> will be treated like </span><span class="o">(*</span><span class="nb"> whitebox </span><span class="o">*)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nowb</span>
<span class="nb">        delete </span><span class="o">(*</span><span class="nb"> whitebox </span><span class="o">*)</span><span class="nb"> and </span><span class="o">(*</span><span class="nb"> lib_whitebox </span><span class="o">*)</span><span class="nb"> attributes from</span>
<span class="nb">        all modules.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">specify</span>
<span class="nb">        parse and import specify blocks</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noopt</span>
<span class="nb">        don&#39;t perform basic optimizations </span><span class="o">(</span><span class="nb">such as const folding</span><span class="o">)</span><span class="nb"> in the</span>
<span class="nb">        high</span><span class="o">-</span><span class="nb">level front</span><span class="o">-</span><span class="nb">end.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">icells</span>
<span class="nb">        interpret cell types starting with &#39;</span><span class="s">$</span>&#39; as internal cell types

    -pwires
        add a wire for each module parameter

    -nooverwrite
        ignore re-definitions of modules. (the default behavior is to
        create an error message if the existing module is not a black box
        module, and overwrite the existing module otherwise.)

    -overwrite
        overwrite existing modules with the same name

    -defer
        only read the abstract syntax tree and defer actual compilation
        to a later &#39;hierarchy&#39; command. Useful in cases where the default
        parameters of modules yield invalid or not synthesizable code.

    -noautowire
        make the default of `default<span class="nb">_</span>nettype be &quot;none&quot; instead of &quot;wire&quot;.

    -setattr &lt;attribute<span class="nb">_</span>name&gt;
        set the specified attribute (to the value 1) on all loaded modules

    -Dname[=definition]
        define the preprocessor symbol &#39;name&#39; and set its optional value
        &#39;definition&#39;

    -Idir
        add &#39;dir&#39; to the directories which are used when searching include
        files

The command &#39;verilog<span class="nb">_</span>defaults&#39; can be used to register default options for
subsequent calls to &#39;read<span class="nb">_</span>verilog&#39;.

Note that the Verilog frontend does a pretty good job of processing valid
verilog input, but has not very good error reporting. It generally is
recommended to use a simulator (for example Icarus Verilog) for checking
the syntax of the code, rather than to rely on read<span class="nb">_</span>verilog for that.

Depending on if read<span class="nb">_</span>verilog is run in -formal mode, either the macro
SYNTHESIS or FORMAL is defined automatically. In addition, read<span class="nb">_</span>verilog
always defines the macro YOSYS.

See the Yosys README file for a list of non-standard Verilog features
supported by the Yosys Verilog front-end.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>rename -- rename object in the design<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:rename<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    rename old<span class="nb">_</span>name new<span class="nb">_</span>name

Rename the specified object. Note that selection patterns are not supported
by this command.



    rename -output old<span class="nb">_</span>name new<span class="nb">_</span>name

Like above, but also make the wire an output. This will fail if the object is
not a wire.


    rename -src [selection]

Assign names auto-generated from the src attribute to all selected wires and
cells with private names.


    rename -wire [selection]

Assign auto-generated names based on the wires they drive to all selected
cells with private names. Ignores cells driving privatly named wires.


    rename -enumerate [-pattern &lt;pattern&gt;] [selection]

Assign short auto-generated names to all selected wires and cells with private
names. The -pattern option can be used to set the pattern for the new names.
The character <span class="c">% in the pattern is replaced with a integer number. The default</span>
pattern is &#39;<span class="nb">_</span><span class="c">%_&#39;.</span>


    rename -hide [selection]

Assign private names (the ones with <span class="s">$</span><span class="o">-</span><span class="nb">prefix</span><span class="o">)</span><span class="nb"> to all selected wires and cells</span>
<span class="nb">with public names. This ignores all selected ports.</span>


<span class="nb">    rename </span><span class="o">-</span><span class="nb">top new_name</span>

<span class="nb">Rename top module.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{rmports </span><span class="o">--</span><span class="nb"> remove module ports with no connections}</span>
<span class="nv">\label</span><span class="nb">{cmd:rmports}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    rmports </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass identifies ports in the selected modules which are not used or</span>
<span class="nb">driven and removes them.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{sat </span><span class="o">--</span><span class="nb"> solve a SAT problem in the circuit}</span>
<span class="nv">\label</span><span class="nb">{cmd:sat}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    sat </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command solves a SAT problem defined over the currently selected circuit</span>
<span class="nb">and additional constraints passed as parameters.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">all</span>
<span class="nb">        show all solutions to the problem </span><span class="o">(</span><span class="nb">this can grow exponentially, use</span>
<span class="nb">        </span><span class="o">-</span><span class="nb">max &lt;N&gt; instead to get &lt;N&gt; solutions</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">max &lt;N&gt;</span>
<span class="nb">        like </span><span class="o">-</span><span class="nb">all, but limit number of solutions to &lt;N&gt;</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">enable_undef</span>
<span class="nb">        enable modeling of undef value </span><span class="o">(</span><span class="nb">aka &#39;x</span><span class="o">-</span><span class="nb">bits&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        this option is implied by </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">def, </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">undef et. cetera</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">max_undef</span>
<span class="nb">        maximize the number of undef bits in solutions, giving a better</span>
<span class="nb">        picture of which input bits are actually vital to the solution.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set &lt;signal&gt; &lt;value&gt;</span>
<span class="nb">        set the specified signal to the specified value.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">def &lt;signal&gt;</span>
<span class="nb">        add a constraint that all bits of the given signal must be defined</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">any</span><span class="o">-</span><span class="nb">undef &lt;signal&gt;</span>
<span class="nb">        add a constraint that at least one bit of the given signal is undefined</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">all</span><span class="o">-</span><span class="nb">undef &lt;signal&gt;</span>
<span class="nb">        add a constraint that all bits of the given signal are undefined</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">def</span><span class="o">-</span><span class="nb">inputs</span>
<span class="nb">        add </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">def constraints for all module inputs</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">show &lt;signal&gt;</span>
<span class="nb">        show the model for the specified signal. if no </span><span class="o">-</span><span class="nb">show option is</span>
<span class="nb">        passed then a set of signals to be shown is automatically selected.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">show</span><span class="o">-</span><span class="nb">inputs, </span><span class="o">-</span><span class="nb">show</span><span class="o">-</span><span class="nb">outputs, </span><span class="o">-</span><span class="nb">show</span><span class="o">-</span><span class="nb">ports</span>
<span class="nb">        add all module </span><span class="o">(</span><span class="nb">input</span><span class="o">/</span><span class="nb">output</span><span class="o">)</span><span class="nb"> ports to the list of shown signals</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">show</span><span class="o">-</span><span class="nb">regs, </span><span class="o">-</span><span class="nb">show</span><span class="o">-</span><span class="nb">public, </span><span class="o">-</span><span class="nb">show</span><span class="o">-</span><span class="nb">all</span>
<span class="nb">        show all registers, show signals with &#39;public&#39; names, show all signals</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ignore_div_by_zero</span>
<span class="nb">        ignore all solutions that involve a division by zero</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">ignore_unknown_cells</span>
<span class="nb">        ignore all cells that can not be matched to a SAT model</span>

<span class="nb">The following options can be used to set up a sequential problem:</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">seq &lt;N&gt;</span>
<span class="nb">        set up a sequential problem with &lt;N&gt; time steps. The steps will</span>
<span class="nb">        be numbered from </span><span class="m">1</span><span class="nb"> to N.</span>

<span class="nb">        note: for large &lt;N&gt; it can be significantly faster to use</span>
<span class="nb">        </span><span class="o">-</span><span class="nb">tempinduct</span><span class="o">-</span><span class="nb">baseonly </span><span class="o">-</span><span class="nb">maxsteps &lt;N&gt; instead of </span><span class="o">-</span><span class="nb">seq &lt;N&gt;.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">at &lt;N&gt; &lt;signal&gt; &lt;value&gt;</span>
<span class="nb">    </span><span class="o">-</span><span class="nb">unset</span><span class="o">-</span><span class="nb">at &lt;N&gt; &lt;signal&gt;</span>
<span class="nb">        set or unset the specified signal to the specified value in the</span>
<span class="nb">        given timestep. this has priority over a </span><span class="o">-</span><span class="nb">set for the same signal.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">assumes</span>
<span class="nb">        set all assumptions provided via </span><span class="s">$</span>assume cells

    -set-def-at &lt;N&gt; &lt;signal&gt;
    -set-any-undef-at &lt;N&gt; &lt;signal&gt;
    -set-all-undef-at &lt;N&gt; &lt;signal&gt;
        add undef constraints in the given timestep.

    -set-init &lt;signal&gt; &lt;value&gt;
        set the initial value for the register driving the signal to the value

    -set-init-undef
        set all initial states (not set using -set-init) to undef

    -set-init-def
        do not force a value for the initial state but do not allow undef

    -set-init-zero
        set all initial states (not set using -set-init) to zero

    -dump<span class="nb">_</span>vcd &lt;vcd-file-name&gt;
        dump SAT model (counter example in proof) to VCD file

    -dump<span class="nb">_</span>json &lt;json-file-name&gt;
        dump SAT model (counter example in proof) to a WaveJSON file.

    -dump<span class="nb">_</span>cnf &lt;cnf-file-name&gt;
        dump CNF of SAT problem (in DIMACS format). in temporal induction
        proofs this is the CNF of the first induction step.

The following additional options can be used to set up a proof. If also -seq
is passed, a temporal induction proof is performed.

    -tempinduct
        Perform a temporal induction proof. In a temporal induction proof it is
        proven that the condition holds forever after the number of time steps
        specified using -seq.

    -tempinduct-def
        Perform a temporal induction proof. Assume an initial state with all
        registers set to defined values for the induction step.

    -tempinduct-baseonly
        Run only the basecase half of temporal induction (requires -maxsteps)

    -tempinduct-inductonly
        Run only the induction half of temporal induction

    -tempinduct-skip &lt;N&gt;
        Skip the first &lt;N&gt; steps of the induction proof.

        note: this will assume that the base case holds for &lt;N&gt; steps.
        this must be proven independently with &quot;-tempinduct-baseonly
        -maxsteps &lt;N&gt;&quot;. Use -initsteps if you just want to set a
        minimal induction length.

    -prove &lt;signal&gt; &lt;value&gt;
        Attempt to proof that &lt;signal&gt; is always &lt;value&gt;.

    -prove-x &lt;signal&gt; &lt;value&gt;
        Like -prove, but an undef (x) bit in the lhs matches any value on
        the right hand side. Useful for equivalence checking.

    -prove-asserts
        Prove that all asserts in the design hold.

    -prove-skip &lt;N&gt;
        Do not enforce the prove-condition for the first &lt;N&gt; time steps.

    -maxsteps &lt;N&gt;
        Set a maximum length for the induction.

    -initsteps &lt;N&gt;
        Set initial length for the induction.
        This will speed up the search of the right induction length
        for deep induction proofs.

    -stepsize &lt;N&gt;
        Increase the size of the induction proof in steps of &lt;N&gt;.
        This will speed up the search of the right induction length
        for deep induction proofs.

    -timeout &lt;N&gt;
        Maximum number of seconds a single SAT instance may take.

    -verify
        Return an error and stop the synthesis script if the proof fails.

    -verify-no-timeout
        Like -verify but do not return an error for timeouts.

    -falsify
        Return an error and stop the synthesis script if the proof succeeds.

    -falsify-no-timeout
        Like -falsify but do not return an error for timeouts.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>scatter -- add additional intermediate nets<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:scatter<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    scatter [selection]

This command adds additional intermediate nets on all cell ports. This is used
for testing the correct use of the SigMap helper in passes. If you don&#39;t know
what this means: don&#39;t worry -- you only need this pass when testing your own
extensions to Yosys.

Use the opt<span class="nb">_</span>clean command to get rid of the additional nets.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>scc -- detect strongly connected components (logic loops)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:scc<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    scc [options] [selection]

This command identifies strongly connected components (aka logic loops) in the
design.

    -expect &lt;num&gt;
        expect to find exactly &lt;num&gt; SSCs. A different number of SSCs will
        produce an error.

    -max<span class="nb">_</span>depth &lt;num&gt;
        limit to loops not longer than the specified number of cells. This
        can e.g. be useful in identifying small local loops in a module that
        implements one large SCC.

    -nofeedback
        do not count cells that have their output fed back into one of their
        inputs as single-cell scc.

    -all<span class="nb">_</span>cell<span class="nb">_</span>types
        Usually this command only considers internal non-memory cells. With
        this option set, all cells are considered. For unknown cells all ports
        are assumed to be bidirectional &#39;inout&#39; ports.

    -set<span class="nb">_</span>attr &lt;name&gt; &lt;value&gt;
        set the specified attribute on all cells that are part of a logic
        loop. the special token <span class="nb">{}</span> in the value is replaced with a unique
        identifier for the logic loop.

    -select
        replace the current selection with a selection of all cells and wires
        that are part of a found logic loop
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>scratchpad -- get/set values in the scratchpad<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:scratchpad<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    scratchpad [options]

This pass allows to read and modify values from the scratchpad of the current
design. Options:

    -get &lt;identifier&gt;
        print the value saved in the scratchpad under the given identifier.

    -set &lt;identifier&gt; &lt;value&gt;
        save the given value in the scratchpad under the given identifier.

    -unset &lt;identifier&gt;
        remove the entry for the given identifier from the scratchpad.

    -copy &lt;identifier<span class="nb">_</span>from&gt; &lt;identifier<span class="nb">_</span>to&gt;
        copy the value of the first identifier to the second identifier.

    -assert &lt;identifier&gt; &lt;value&gt;
        assert that the entry for the given identifier is set to the given value.

    -assert-set &lt;identifier&gt;
        assert that the entry for the given identifier exists.

    -assert-unset &lt;identifier&gt;
        assert that the entry for the given identifier does not exist.

The identifier may not contain whitespace. By convention, it is usually prefixed
by the name of the pass that uses it, e.g. &#39;opt.did<span class="nb">_</span>something&#39;. If the value
contains whitespace, it must be enclosed in double quotes.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>script -- execute commands from file or wire<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:script<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    script &lt;filename&gt; [&lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;]
    script -scriptwire [selection]

This command executes the yosys commands in the specified file (default
behaviour), or commands embedded in the constant text value connected to the
selected wires.

In the default (file) case, the 2nd argument can be used to only execute the
section of the file between the specified labels. An empty from label is
synonymous with the beginning of the file and an empty to label is synonymous
with the end of the file.

If only one label is specified (without &#39;:&#39;) then only the block
marked with that label (until the next label) is executed.

In &quot;-scriptwire&quot; mode, the commands on the selected wire(s) will be executed
in the scope of (and thus, relative to) the wires&#39; owning module(s). This
&#39;-module&#39; mode can be exited by using the &#39;cd&#39; command.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>select -- modify and view the list of selected objects<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:select<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    select [ -add | -del | -set &lt;name&gt; ] <span class="nb">{</span>-read &lt;filename&gt; | &lt;selection&gt;<span class="nb">}</span>
    select [ &lt;assert<span class="nb">_</span>option&gt; ] <span class="nb">{</span>-read &lt;filename&gt; | &lt;selection&gt;<span class="nb">}</span>
    select [ -list | -write &lt;filename&gt; | -count | -clear ]
    select -module &lt;modname&gt;

Most commands use the list of currently selected objects to determine which part
of the design to operate on. This command can be used to modify and view this
list of selected objects.

Note that many commands support an optional [selection] argument that can be
used to override the global selection for the command. The syntax of this
optional argument is identical to the syntax of the &lt;selection&gt; argument
described here.

    -add, -del
        add or remove the given objects to the current selection.
        without this options the current selection is replaced.

    -set &lt;name&gt;
        do not modify the current selection. instead save the new selection
        under the given name (see @&lt;name&gt; below). to save the current selection,
        use &quot;select -set &lt;name&gt; <span class="c">%&quot;</span>

    -assert-none
        do not modify the current selection. instead assert that the given
        selection is empty. i.e. produce an error if any object matching the
        selection is found.

    -assert-any
        do not modify the current selection. instead assert that the given
        selection is non-empty. i.e. produce an error if no object matching
        the selection is found.

    -assert-count N
        do not modify the current selection. instead assert that the given
        selection contains exactly N objects.

    -assert-max N
        do not modify the current selection. instead assert that the given
        selection contains less than or exactly N objects.

    -assert-min N
        do not modify the current selection. instead assert that the given
        selection contains at least N objects.

    -list
        list all objects in the current selection

    -write &lt;filename&gt;
        like -list but write the output to the specified file

    -read &lt;filename&gt;
        read the specified file (written by -write)

    -count
        count all objects in the current selection

    -clear
        clear the current selection. this effectively selects the whole
        design. it also resets the selected module (see -module). use the
        command &#39;select *&#39; to select everything but stay in the current module.

    -none
        create an empty selection. the current module is unchanged.

    -module &lt;modname&gt;
        limit the current scope to the specified module.
        the difference between this and simply selecting the module
        is that all object names are interpreted relative to this
        module after this command until the selection is cleared again.

When this command is called without an argument, the current selection
is displayed in a compact form (i.e. only the module name when a whole module
is selected).

The &lt;selection&gt; argument itself is a series of commands for a simple stack
machine. Each element on the stack represents a set of selected objects.
After this commands have been executed, the union of all remaining sets
on the stack is computed and used as selection for the command.

Pushing (selecting) object when not in -module mode:

    &lt;mod<span class="nb">_</span>pattern&gt;
        select the specified module(s)

    &lt;mod<span class="nb">_</span>pattern&gt;/&lt;obj<span class="nb">_</span>pattern&gt;
        select the specified object(s) from the module(s)

Pushing (selecting) object when in -module mode:

    &lt;obj<span class="nb">_</span>pattern&gt;
        select the specified object(s) from the current module

A &lt;mod<span class="nb">_</span>pattern&gt; can be a module name, wildcard expression (*, ?, [..])
matching module names, or one of the following:

    A:&lt;pattern&gt;, A:&lt;pattern&gt;=&lt;pattern&gt;
        all modules with an attribute matching the given pattern
        in addition to = also &lt;, &lt;=, &gt;=, and &gt; are supported

    N:&lt;pattern&gt;
        all modules with a name matching the given pattern
        (i.e. &#39;N:&#39; is optional as it is the default matching rule)

An &lt;obj<span class="nb">_</span>pattern&gt; can be an object name, wildcard expression, or one of
the following:

    w:&lt;pattern&gt;
        all wires with a name matching the given wildcard pattern

    i:&lt;pattern&gt;, o:&lt;pattern&gt;, x:&lt;pattern&gt;
        all inputs (i:), outputs (o:) or any ports (x:) with matching names

    s:&lt;size&gt;, s:&lt;min&gt;:&lt;max&gt;
        all wires with a matching width

    m:&lt;pattern&gt;
        all memories with a name matching the given pattern

    c:&lt;pattern&gt;
        all cells with a name matching the given pattern

    t:&lt;pattern&gt;
        all cells with a type matching the given pattern

    p:&lt;pattern&gt;
        all processes with a name matching the given pattern

    a:&lt;pattern&gt;
        all objects with an attribute name matching the given pattern

    a:&lt;pattern&gt;=&lt;pattern&gt;
        all objects with a matching attribute name-value-pair.
        in addition to = also &lt;, &lt;=, &gt;=, and &gt; are supported

    r:&lt;pattern&gt;, r:&lt;pattern&gt;=&lt;pattern&gt;
        cells with matching parameters. also with &lt;, &lt;=, &gt;= and &gt;.

    n:&lt;pattern&gt;
        all objects with a name matching the given pattern
        (i.e. &#39;n:&#39; is optional as it is the default matching rule)

    @&lt;name&gt;
        push the selection saved prior with &#39;select -set &lt;name&gt; ...&#39;

The following actions can be performed on the top sets on the stack:

    <span class="c">%</span>
        push a copy of the current selection to the stack

    <span class="c">%%</span>
        replace the stack with a union of all elements on it

    <span class="c">%n</span>
        replace top set with its invert

    <span class="c">%u</span>
        replace the two top sets on the stack with their union

    <span class="c">%i</span>
        replace the two top sets on the stack with their intersection

    <span class="c">%d</span>
        pop the top set from the stack and subtract it from the new top

    <span class="c">%D</span>
        like <span class="c">%d but swap the roles of two top sets on the stack</span>

    <span class="c">%c</span>
        create a copy of the top set from the stack and push it

    <span class="c">%x[&lt;num1&gt;|*][.&lt;num2&gt;][:&lt;rule&gt;[:&lt;rule&gt;..]]</span>
        expand top set &lt;num1&gt; num times according to the specified rules.
        (i.e. select all cells connected to selected wires and select all
        wires connected to selected cells) The rules specify which cell
        ports to use for this. the syntax for a rule is a &#39;-&#39; for exclusion
        and a &#39;+&#39; for inclusion, followed by an optional comma separated
        list of cell types followed by an optional comma separated list of
        cell ports in square brackets. a rule can also be just a cell or wire
        name that limits the expansion (is included but does not go beyond).
        select at most &lt;num2&gt; objects. a warning message is printed when this
        limit is reached. When &#39;*&#39; is used instead of &lt;num1&gt; then the process
        is repeated until no further object are selected.

    <span class="c">%ci[&lt;num1&gt;|*][.&lt;num2&gt;][:&lt;rule&gt;[:&lt;rule&gt;..]]</span>
    <span class="c">%co[&lt;num1&gt;|*][.&lt;num2&gt;][:&lt;rule&gt;[:&lt;rule&gt;..]]</span>
        similar to <span class="c">%x, but only select input (%ci) or output cones (%co)</span>

    <span class="c">%xe[...] %cie[...] %coe</span>
        like <span class="c">%x, %ci, and %co but only consider combinatorial cells</span>

    <span class="c">%a</span>
        expand top set by selecting all wires that are (at least in part)
        aliases for selected wires.

    <span class="c">%s</span>
        expand top set by adding all modules that implement cells in selected
        modules

    <span class="c">%m</span>
        expand top set by selecting all modules that contain selected objects

    <span class="c">%M</span>
        select modules that implement selected cells

    <span class="c">%C</span>
        select cells that implement selected modules

    <span class="c">%R[&lt;num&gt;]</span>
        select &lt;num&gt; random objects from top selection (default 1)

Example: the following command selects all wires that are connected to a
&#39;GATE&#39; input of a &#39;SWITCH&#39; cell:

    select */t:SWITCH <span class="c">%x:+[GATE] */t:SWITCH %d</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>setattr -- set/unset attributes on objects<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:setattr<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    setattr [ -mod ] [ -set name value | -unset name ]... [selection]

Set/unset the given attributes on the selected objects. String values must be
passed in double quotes (&quot;).

When called with -mod, this command will set and unset attributes on modules
instead of objects within modules.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>setparam -- set/unset parameters on objects<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:setparam<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    setparam [ -type cell<span class="nb">_</span>type ] [ -set name value | -unset name ]... [selection]

Set/unset the given parameters on the selected cells. String values must be
passed in double quotes (&quot;).

The -type option can be used to change the cell type of the selected cells.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>setundef -- replace undef values with defined constants<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:setundef<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    setundef [options] [selection]

This command replaces undef (x) constants with defined (0/1) constants.

    -undriven
        also set undriven nets to constant values

    -expose
        also expose undriven nets as inputs (use with -undriven)

    -zero
        replace with bits cleared (0)

    -one
        replace with bits set (1)

    -undef
        replace with undef (x) bits, may be used with -undriven

    -anyseq
        replace with <span class="s">$</span><span class="nb">anyseq drivers </span><span class="o">(</span><span class="nb">for formal</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">anyconst</span>
<span class="nb">        replace with </span><span class="s">$</span>anyconst drivers (for formal)

    -random &lt;seed&gt;
        replace with random bits using the specified integer as seed
        value for the random number generator.

    -init
        also create/update init values for flip-flops

    -params
        replace undef in cell parameters
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>sf2<span class="k">\_</span>iobs -- SF2: insert IO buffers<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:sf2<span class="nb">_</span>iobs<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    sf2<span class="nb">_</span>iobs [options] [selection]

Add SF2 I/O buffers and global buffers to top module as needed.

    -clkbuf
        Insert PAD-&gt;global<span class="nb">_</span>net clock buffers
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>share -- perform sat-based resource sharing<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:share<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    share [options] [selection]

This pass merges shareable resources into a single resource. A SAT solver
is used to determine if two resources are share-able.

  -force
    Per default the selection of cells that is considered for sharing is
    narrowed using a list of cell types. With this option all selected
    cells are considered for resource sharing.

    IMPORTANT NOTE: If the -all option is used then no cells with internal
    state must be selected!

  -aggressive
    Per default some heuristics are used to reduce the number of cells
    considered for resource sharing to only large resources. This options
    turns this heuristics off, resulting in much more cells being considered
    for resource sharing.

  -fast
    Only consider the simple part of the control logic in SAT solving, resulting
    in much easier SAT problems at the cost of maybe missing some opportunities
    for resource sharing.

  -limit N
    Only perform the first N merges, then stop. This is useful for debugging.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>shell -- enter interactive command mode<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:shell<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    shell

This command enters the interactive command mode. This can be useful
in a script to interrupt the script at a certain point and allow for
interactive inspection or manual synthesis of the design at this point.

The command prompt of the interactive shell indicates the current
selection (see &#39;help select&#39;):

    yosys&gt;
        the entire design is selected

    yosys*&gt;
        only part of the design is selected

    yosys [modname]&gt;
        the entire module &#39;modname&#39; is selected using &#39;select -module modname&#39;

    yosys [modname]*&gt;
        only part of current module &#39;modname&#39; is selected

When in interactive shell, some errors (e.g. invalid command arguments)
do not terminate yosys but return to the command prompt.

This command is the default action if nothing else has been specified
on the command line.

Press Ctrl-D or type &#39;exit&#39; to leave the interactive shell.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>show -- generate schematics using graphviz<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:show<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    show [options] [selection]

Create a graphviz DOT file for the selected part of the design and compile it
to a graphics file (usually SVG or PostScript).

    -viewer &lt;viewer&gt;
        Run the specified command with the graphics file as parameter.
        On Windows, this pauses yosys until the viewer exits.

    -format &lt;format&gt;
        Generate a graphics file in the specified format. Use &#39;dot&#39; to just
        generate a .dot file, or other &lt;format&gt; strings such as &#39;svg&#39; or &#39;ps&#39;
        to generate files in other formats (this calls the &#39;dot&#39; command).

    -lib &lt;verilog<span class="nb">_</span>or<span class="nb">_</span>ilang<span class="nb">_</span>file&gt;
        Use the specified library file for determining whether cell ports are
        inputs or outputs. This option can be used multiple times to specify
        more than one library.

        note: in most cases it is better to load the library before calling
        show with &#39;read<span class="nb">_</span>verilog -lib &lt;filename&gt;&#39;. it is also possible to
        load liberty files with &#39;read<span class="nb">_</span>liberty -lib &lt;filename&gt;&#39;.

    -prefix &lt;prefix&gt;
        generate &lt;prefix&gt;.* instead of ~/.yosys<span class="nb">_</span>show.*

    -color &lt;color&gt; &lt;object&gt;
        assign the specified color to the specified object. The object can be
        a single selection wildcard expressions or a saved set of objects in
        the @&lt;name&gt; syntax (see &quot;help select&quot; for details).

    -label &lt;text&gt; &lt;object&gt;
        assign the specified label text to the specified object. The object can
        be a single selection wildcard expressions or a saved set of objects in
        the @&lt;name&gt; syntax (see &quot;help select&quot; for details).

    -colors &lt;seed&gt;
        Randomly assign colors to the wires. The integer argument is the seed
        for the random number generator. Change the seed value if the colored
        graph still is ambiguous. A seed of zero deactivates the coloring.

    -colorattr &lt;attribute<span class="nb">_</span>name&gt;
        Use the specified attribute to assign colors. A unique color is
        assigned to each unique value of this attribute.

    -width
        annotate buses with a label indicating the width of the bus.

    -signed
        mark ports (A, B) that are declared as signed (using the [AB]<span class="nb">_</span>SIGNED
        cell parameter) with an asterisk next to the port name.

    -stretch
        stretch the graph so all inputs are on the left side and all outputs
        (including inout ports) are on the right side.

    -pause
        wait for the use to press enter to before returning

    -enum
        enumerate objects with internal (<span class="s">$</span><span class="o">-</span><span class="nb">prefixed</span><span class="o">)</span><span class="nb"> names</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">long</span>
<span class="nb">        do not abbreviate objects with internal </span><span class="o">(</span><span class="s">$</span>-prefixed) names

    -notitle
        do not add the module name as graph title to the dot file

    -nobg
        don&#39;t run viewer in the background, IE wait for the viewer tool to
        exit before returning

When no &lt;format&gt; is specified, &#39;dot&#39; is used. When no &lt;format&gt; and &lt;viewer&gt; is
specified, &#39;xdot&#39; is used to display the schematic (POSIX systems only).

The generated output files are &#39;~/.yosys<span class="nb">_</span>show.dot&#39; and &#39;~/.yosys<span class="nb">_</span>show.&lt;format&gt;&#39;,
unless another prefix is specified using -prefix &lt;prefix&gt;.

Yosys on Windows and YosysJS use different defaults: The output is written
to &#39;show.dot&#39; in the current directory and new viewer is launched each time
the &#39;show&#39; command is executed.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>shregmap -- map shift registers<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:shregmap<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    shregmap [options] [selection]

This pass converts chains of <span class="s">$</span><span class="nb">_DFF_</span><span class="o">[</span><span class="nb">NP</span><span class="o">]</span><span class="nb">_ gates to target specific shift register</span>
<span class="nb">primitives. The generated shift register will be of type </span><span class="s">$</span><span class="nb">__</span>SHREG<span class="nb">_</span>DFF<span class="nb">_</span>[NP]<span class="nb">_</span> and
will use the same interface as the original <span class="s">$</span><span class="nb">_DFF_</span><span class="o">*</span><span class="nb">_ cells. The cell parameter</span>
<span class="nb">&#39;DEPTH&#39; will contain the depth of the shift register. Use a target</span><span class="o">-</span><span class="nb">specific</span>
<span class="nb">&#39;techmap&#39; map file to convert those cells to the actual target cells.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">minlen N</span>
<span class="nb">        minimum length of shift register </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> </span><span class="m">2</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        </span><span class="o">(</span><span class="nb">this is the length after </span><span class="o">-</span><span class="nb">keep_before and </span><span class="o">-</span><span class="nb">keep_after</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">maxlen N</span>
<span class="nb">        maximum length of shift register </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> no limit</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        larger chains will be mapped to multiple shift register instances</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">keep_before N</span>
<span class="nb">        number of DFFs to keep before the shift register </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">keep_after N</span>
<span class="nb">        number of DFFs to keep after the shift register </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">clkpol pos|neg|any</span>
<span class="nb">        limit match to only positive or negative edge clocks. </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> any</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">enpol pos|neg|none|any_or_none|any</span>
<span class="nb">        limit match to FFs with the specified enable polarity. </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> none</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">match &lt;cell_type&gt;</span><span class="o">[</span><span class="nb">:&lt;d_port_name&gt;:&lt;q_port_name&gt;</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        match the specified cells instead of </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>N<span class="nb">_</span> and <span class="s">$</span><span class="nb">_DFF_P_. If</span>
<span class="nb">        &#39;:&lt;d_port_name&gt;:&lt;q_port_name&gt;&#39; is omitted then &#39;D&#39; and &#39;Q&#39; is used</span>
<span class="nb">        by default. E.g. the option &#39;</span><span class="o">-</span><span class="nb">clkpol pos&#39; is just an alias for</span>
<span class="nb">        &#39;</span><span class="o">-</span><span class="nb">match </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>P<span class="nb">_</span>&#39;, which is an alias for &#39;-match <span class="s">$</span><span class="nb">_DFF_P_:D:Q&#39;.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">params</span>
<span class="nb">        instead of encoding the clock and enable polarity in the cell name by</span>
<span class="nb">        deriving from the original cell name, simply name all generated cells</span>
<span class="nb">        </span><span class="s">$</span><span class="nb">__</span>SHREG<span class="nb">_</span> and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is
        used to denote cells without enable input. The ENPOL parameter is
        omitted when &#39;-enpol none&#39; (or no -enpol option) is passed.

    -zinit
        assume the shift register is automatically zero-initialized, so it
        becomes legal to merge zero initialized FFs into the shift register.

    -init
        map initialized registers to the shift reg, add an INIT parameter to
        generated cells with the initialization value. (first bit to shift out
        in LSB position)

    -tech greenpak4
        map to greenpak4 shift registers.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>sim -- simulate the circuit<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:sim<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    sim [options] [top-level]

This command simulates the circuit using the given top-level module.

    -vcd &lt;filename&gt;
        write the simulation results to the given VCD file

    -clock &lt;portname&gt;
        name of top-level clock input

    -clockn &lt;portname&gt;
        name of top-level clock input (inverse polarity)

    -reset &lt;portname&gt;
        name of top-level reset input (active high)

    -resetn &lt;portname&gt;
        name of top-level inverted reset input (active low)

    -rstlen &lt;integer&gt;
        number of cycles reset should stay active (default: 1)

    -zinit
        zero-initialize all uninitialized regs and memories

    -n &lt;integer&gt;
        number of cycles to simulate (default: 20)

    -a
        include all nets in VCD output, not just those with public names

    -w
        writeback mode: use final simulation state as new init state

    -d
        enable debug output
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>simplemap -- mapping simple coarse-grain cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:simplemap<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    simplemap [selection]

This pass maps a small selection of simple coarse-grain cells to yosys gate
primitives. The following internal cell types are mapped by this pass:

  <span class="s">$</span><span class="nb">not, </span><span class="s">$</span>pos, <span class="s">$</span><span class="nb">and, </span><span class="s">$</span>or, <span class="s">$</span><span class="nb">xor, </span><span class="s">$</span>xnor
  <span class="s">$</span><span class="nb">reduce_and, </span><span class="s">$</span>reduce<span class="nb">_</span>or, <span class="s">$</span><span class="nb">reduce_xor, </span><span class="s">$</span>reduce<span class="nb">_</span>xnor, <span class="s">$</span><span class="nb">reduce_bool</span>
<span class="nb">  </span><span class="s">$</span>logic<span class="nb">_</span>not, <span class="s">$</span><span class="nb">logic_and, </span><span class="s">$</span>logic<span class="nb">_</span>or, <span class="s">$</span><span class="nb">mux, </span><span class="s">$</span>tribuf
  <span class="s">$</span><span class="nb">sr, </span><span class="s">$</span>ff, <span class="s">$</span><span class="nb">dff, </span><span class="s">$</span>dffsr, <span class="s">$</span><span class="nb">adff, </span><span class="s">$</span>dlatch
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>splice -- create explicit splicing cells<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:splice<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    splice [options] [selection]

This command adds <span class="s">$</span><span class="nb">slice and </span><span class="s">$</span>concat cells to the design to make the splicing
of multi-bit signals explicit. This for example is useful for coarse grain
synthesis, where dedicated hardware is needed to splice signals.

    -sel<span class="nb">_</span>by<span class="nb">_</span>cell
        only select the cell ports to rewire by the cell. if the selection
        contains a cell, than all cell inputs are rewired, if necessary.

    -sel<span class="nb">_</span>by<span class="nb">_</span>wire
        only select the cell ports to rewire by the wire. if the selection
        contains a wire, than all cell ports driven by this wire are wired,
        if necessary.

    -sel<span class="nb">_</span>any<span class="nb">_</span>bit
        it is sufficient if the driver of any bit of a cell port is selected.
        by default all bits must be selected.

    -wires
        also add <span class="s">$</span><span class="nb">slice and </span><span class="s">$</span>concat cells to drive otherwise unused wires.

    -no<span class="nb">_</span>outputs
        do not rewire selected module outputs.

    -port &lt;name&gt;
        only rewire cell ports with the specified name. can be used multiple
        times. implies -no<span class="nb">_</span>output.

    -no<span class="nb">_</span>port &lt;name&gt;
        do not rewire cell ports with the specified name. can be used multiple
        times. can not be combined with -port &lt;name&gt;.

By default selected output wires and all cell ports of selected cells driven
by selected wires are rewired.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>splitnets -- split up multi-bit nets<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:splitnets<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    splitnets [options] [selection]

This command splits multi-bit nets into single-bit nets.

    -format char1[char2[char3]]
        the first char is inserted between the net name and the bit index, the
        second char is appended to the netname. e.g. -format () creates net
        names like &#39;mysignal(42)&#39;. the 3rd character is the range separation
        character when creating multi-bit wires. the default is &#39;[]:&#39;.

    -ports
        also split module ports. per default only internal signals are split.

    -driver
        don&#39;t blindly split nets in individual bits. instead look at the driver
        and split nets so that no driver drives only part of a net.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>stat -- print some statistics<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:stat<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    stat [options] [selection]

Print some statistics (number of objects) on the selected portion of the
design.

    -top &lt;module&gt;
        print design hierarchy with this module as top. if the design is fully
        selected and a module has the &#39;top&#39; attribute set, this module is used
        default value for this option.

    -liberty &lt;liberty<span class="nb">_</span>file&gt;
        use cell area information from the provided liberty file

    -tech &lt;technology&gt;
        print area estemate for the specified technology. Currently supported
        values for &lt;technology&gt;: xilinx, cmos

    -width
        annotate internal cell types with their word width.
        e.g. <span class="s">$</span><span class="nb">add_</span><span class="m">8</span><span class="nb"> for an </span><span class="m">8</span><span class="nb"> bit wide </span><span class="s">$</span>add cell.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>submod -- moving part of a module to a new submodule<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:submod<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    submod [options] [selection]

This pass identifies all cells with the &#39;submod&#39; attribute and moves them to
a newly created module. The value of the attribute is used as name for the
cell that replaces the group of cells with the same attribute value.

This pass can be used to create a design hierarchy in flat design. This can
be useful for analyzing or reverse-engineering a design.

This pass only operates on completely selected modules with no processes
or memories.

    -copy
        by default the cells are &#39;moved&#39; from the source module and the source
        module will use an instance of the new module after this command is
        finished. call with -copy to not modify the source module.

    -name &lt;name&gt;
        don&#39;t use the &#39;submod&#39; attribute but instead use the selection. only
        objects from one module might be selected. the value of the -name option
        is used as the value of the &#39;submod&#39; attribute instead.

    -hidden
        instead of creating submodule ports with public names, create ports with
        private names so that a subsequent &#39;flatten; clean&#39; call will restore the
        original module with original public names.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>supercover -- add hi/lo cover cells for each wire bit<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:supercover<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    supercover [options] [selection]

This command adds two cover cells for each bit of each selected wire, one
checking for a hi signal level and one checking for lo level.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth -- generic synthesis script<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth [options]

This command runs the default synthesis script. This command does not operate
on partly selected designs.

    -top &lt;module&gt;
        use the specified module as top module (default=&#39;top&#39;)

    -auto-top
        automatically determine the top of the design hierarchy

    -flatten
        flatten the design before synthesis. this will pass &#39;-auto-top&#39; to
        &#39;hierarchy&#39; if no top module is specified.

    -encfile &lt;file&gt;
        passed to &#39;fsm<span class="nb">_</span>recode&#39; via &#39;fsm&#39;

    -lut &lt;k&gt;
        perform synthesis for a k-LUT architecture.

    -nofsm
        do not run FSM optimization

    -noabc
        do not run abc (as if yosys was compiled without ABC support)

    -noalumacc
        do not run &#39;alumacc&#39; pass. i.e. keep arithmetic operators in
        their direct form (<span class="s">$</span><span class="nb">add, </span><span class="s">$</span>sub, etc.).

    -nordff
        passed to &#39;memory&#39;. prohibits merging of FFs into memory read ports

    -noshare
        do not run SAT-based resource sharing

    -run &lt;from<span class="nb">_</span>label&gt;[:&lt;to<span class="nb">_</span>label&gt;]
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -abc9
        use new ABC9 flow (EXPERIMENTAL)

    -flowmap
        use FlowMap LUT techmapping instead of ABC


The following commands are executed by this synthesis command:

    begin:
        hierarchy -check [-top &lt;top&gt; | -auto-top]

    coarse:
        proc
        flatten      (if -flatten)
        opt<span class="nb">_</span>expr
        opt<span class="nb">_</span>clean
        check
        opt
        wreduce
        peepopt
        opt<span class="nb">_</span>clean
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v     (if -lut)
        alumacc      (unless -noalumacc)
        share        (unless -noshare)
        opt
        fsm          (unless -nofsm)
        opt -fast
        memory -nomap
        opt<span class="nb">_</span>clean

    fine:
        opt -fast -full
        memory<span class="nb">_</span>map
        opt -full
        techmap
        techmap -map +/gate2lut.v    (if -noabc and -lut)
        clean; opt<span class="nb">_</span>lut               (if -noabc and -lut)
        flowmap -maxlut K            (if -flowmap and -lut)
        opt -fast
        abc -fast           (unless -noabc, unless -lut)
        abc -fast -lut k    (unless -noabc, if -lut)
        opt -fast           (unless -noabc)

    check:
        hierarchy -check
        stat
        check
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth<span class="k">\_</span>achronix -- synthesis for Acrhonix Speedster22i FPGAs.<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">_</span>achronix<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth<span class="nb">_</span>achronix [options]

This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.

    -top &lt;module&gt;
        use the specified module as top module (default=&#39;top&#39;)

    -vout &lt;file&gt;
        write the design to the specified Verilog netlist file. writing of an
        output file is omitted if this parameter is not specified.

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run &#39;abc&#39; with &#39;-dff -D 1&#39; options


The following commands are executed by this synthesis command:

    begin:
        read<span class="nb">_</span>verilog -sv -lib +/achronix/speedster22i/cells<span class="nb">_</span>sim.v
        hierarchy -check -top &lt;top&gt;

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    fine:
        opt -fast -mux<span class="nb">_</span>undef -undriven -fine -full
        memory<span class="nb">_</span>map
        opt -undriven -fine
        dff2dffe -direct-match <span class="s">$</span><span class="nb">_DFF_</span><span class="o">*</span><span class="nb"></span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fine</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">techmap.v</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">full</span>
<span class="nb">        clean </span><span class="o">-</span><span class="nb">purge</span>
<span class="nb">        setundef </span><span class="o">-</span><span class="nb">undriven </span><span class="o">-</span><span class="nb">zero</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">markgroups </span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">    </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">retime</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    map_luts:</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">lut </span><span class="m">4</span><span class="nb"></span>
<span class="nb">        clean</span>

<span class="nb">    map_cells:</span>
<span class="nb">        iopadmap </span><span class="o">-</span><span class="nb">bits </span><span class="o">-</span><span class="nb">outpad </span><span class="s">$</span><span class="nb">__</span>outpad I:O -inpad <span class="s">$</span><span class="nb">__inpad O:I</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">achronix</span><span class="o">/</span><span class="nb">speedster</span><span class="m">22</span><span class="nb">i</span><span class="o">/</span><span class="nb">cells_map.v</span>
<span class="nb">        clean </span><span class="o">-</span><span class="nb">purge</span>

<span class="nb">    check:</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        stat</span>
<span class="nb">        check </span><span class="o">-</span><span class="nb">noinit</span>

<span class="nb">    vout:</span>
<span class="nb">        write_verilog </span><span class="o">-</span><span class="nb">nodec </span><span class="o">-</span><span class="nb">attr</span><span class="m">2</span><span class="nb">comment </span><span class="o">-</span><span class="nb">defparam </span><span class="o">-</span><span class="nb">renameprefix syn_ &lt;file</span><span class="o">-</span><span class="nb">name&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{synth</span><span class="nv">\_</span><span class="nb">anlogic </span><span class="o">--</span><span class="nb"> synthesis for Anlogic FPGAs}</span>
<span class="nv">\label</span><span class="nb">{cmd:synth_anlogic}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    synth_anlogic </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command runs synthesis for Anlogic FPGAs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top &lt;module&gt;</span>
<span class="nb">        use the specified module as top module</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">edif &lt;file&gt;</span>
<span class="nb">        write the design to the specified EDIF file. writing of an output file</span>
<span class="nb">        is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">json &lt;file&gt;</span>
<span class="nb">        write the design to the specified JSON file. writing of an output file</span>
<span class="nb">        is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">run &lt;from_label&gt;:&lt;to_label&gt;</span>
<span class="nb">        only run the commands between the labels </span><span class="o">(</span><span class="nb">see below</span><span class="o">)</span><span class="nb">. an empty</span>
<span class="nb">        from label is synonymous to &#39;begin&#39;, and empty to label is</span>
<span class="nb">        synonymous to the end of the command list.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noflatten</span>
<span class="nb">        do not flatten design before synthesis</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">retime</span>
<span class="nb">        run &#39;abc&#39; with &#39;</span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">&#39; options</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nolutram</span>
<span class="nb">        do not use EG_LOGIC_DRAM</span><span class="m">16</span><span class="nb">X</span><span class="m">4</span><span class="nb"> cells in output netlist</span>


<span class="nb">The following commands are executed by this synthesis command:</span>

<span class="nb">    begin:</span>
<span class="nb">        read_verilog </span><span class="o">-</span><span class="nb">lib </span><span class="o">+/</span><span class="nb">anlogic</span><span class="o">/</span><span class="nb">cells_sim.v </span><span class="o">+/</span><span class="nb">anlogic</span><span class="o">/</span><span class="nb">eagle_bb.v</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top &lt;top&gt;</span>

<span class="nb">    flatten:    </span><span class="o">(</span><span class="nb">unless </span><span class="o">-</span><span class="nb">noflatten</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        proc</span>
<span class="nb">        flatten</span>
<span class="nb">        tribuf </span><span class="o">-</span><span class="nb">logic</span>
<span class="nb">        deminout</span>

<span class="nb">    coarse:</span>
<span class="nb">        synth </span><span class="o">-</span><span class="nb">run coarse</span>

<span class="nb">    map_lutram:    </span><span class="o">(</span><span class="nb">skip if </span><span class="o">-</span><span class="nb">nolutram</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        memory_bram </span><span class="o">-</span><span class="nb">rules </span><span class="o">+/</span><span class="nb">anlogic</span><span class="o">/</span><span class="nb">lutrams.txt</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">anlogic</span><span class="o">/</span><span class="nb">lutrams_map.v</span>
<span class="nb">        setundef </span><span class="o">-</span><span class="nb">zero </span><span class="o">-</span><span class="nb">params t:EG_LOGIC_DRAM</span><span class="m">16</span><span class="nb">X</span><span class="m">4</span><span class="nb"></span>

<span class="nb">    map_ffram:</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast </span><span class="o">-</span><span class="nb">mux_undef </span><span class="o">-</span><span class="nb">undriven </span><span class="o">-</span><span class="nb">fine</span>
<span class="nb">        memory_map</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">undriven </span><span class="o">-</span><span class="nb">fine</span>

<span class="nb">    map_gates:</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">techmap.v </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">anlogic</span><span class="o">/</span><span class="nb">arith_map.v</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">    </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">retime</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    map_ffs:</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">D NO_LUT </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">anlogic</span><span class="o">/</span><span class="nb">cells_map.v</span>
<span class="nb">        dffinit </span><span class="o">-</span><span class="nb">strinit SET RESET </span><span class="o">-</span><span class="nb">ff AL_MAP_SEQ q REGSET </span><span class="o">-</span><span class="nb">noreinit</span>
<span class="nb">        opt_expr </span><span class="o">-</span><span class="nb">mux_undef</span>
<span class="nb">        simplemap</span>

<span class="nb">    map_luts:</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">lut </span><span class="m">4</span><span class="nb">:</span><span class="m">6</span><span class="nb"></span>
<span class="nb">        clean</span>

<span class="nb">    map_cells:</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">anlogic</span><span class="o">/</span><span class="nb">cells_map.v</span>
<span class="nb">        clean</span>

<span class="nb">    map_anlogic:</span>
<span class="nb">        anlogic_fixcarry</span>
<span class="nb">        anlogic_eqn</span>

<span class="nb">    check:</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        stat</span>
<span class="nb">        check </span><span class="o">-</span><span class="nb">noinit</span>

<span class="nb">    edif:</span>
<span class="nb">        write_edif &lt;file</span><span class="o">-</span><span class="nb">name&gt;</span>

<span class="nb">    json:</span>
<span class="nb">        write_json &lt;file</span><span class="o">-</span><span class="nb">name&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{synth</span><span class="nv">\_</span><span class="nb">coolrunner</span><span class="m">2</span><span class="nb"> </span><span class="o">--</span><span class="nb"> synthesis for Xilinx Coolrunner</span><span class="o">-</span><span class="nb">II CPLDs}</span>
<span class="nv">\label</span><span class="nb">{cmd:synth_coolrunner</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    synth_coolrunner</span><span class="m">2</span><span class="nb"> </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command runs synthesis for Coolrunner</span><span class="o">-</span><span class="nb">II CPLDs. This work is experimental.</span>
<span class="nb">It is intended to be used with https:</span><span class="o">//</span><span class="nb">github.com</span><span class="o">/</span><span class="nb">azonenberg</span><span class="o">/</span><span class="nb">openfpga as the</span>
<span class="nb">place</span><span class="o">-</span><span class="nb">and</span><span class="o">-</span><span class="nb">route.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top &lt;module&gt;</span>
<span class="nb">        use the specified module as top module </span><span class="o">(</span><span class="nb">default</span><span class="o">=</span><span class="nb">&#39;top&#39;</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">json &lt;file&gt;</span>
<span class="nb">        write the design to the specified JSON file. writing of an output file</span>
<span class="nb">        is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">run &lt;from_label&gt;:&lt;to_label&gt;</span>
<span class="nb">        only run the commands between the labels </span><span class="o">(</span><span class="nb">see below</span><span class="o">)</span><span class="nb">. an empty</span>
<span class="nb">        from label is synonymous to &#39;begin&#39;, and empty to label is</span>
<span class="nb">        synonymous to the end of the command list.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noflatten</span>
<span class="nb">        do not flatten design before synthesis</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">retime</span>
<span class="nb">        run &#39;abc&#39; with &#39;</span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">&#39; options</span>


<span class="nb">The following commands are executed by this synthesis command:</span>

<span class="nb">    begin:</span>
<span class="nb">        read_verilog </span><span class="o">-</span><span class="nb">lib </span><span class="o">+/</span><span class="nb">coolrunner</span><span class="m">2</span><span class="o">/</span><span class="nb">cells_sim.v</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top &lt;top&gt;</span>

<span class="nb">    flatten:    </span><span class="o">(</span><span class="nb">unless </span><span class="o">-</span><span class="nb">noflatten</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        proc</span>
<span class="nb">        flatten</span>
<span class="nb">        tribuf </span><span class="o">-</span><span class="nb">logic</span>

<span class="nb">    coarse:</span>
<span class="nb">        synth </span><span class="o">-</span><span class="nb">run coarse</span>

<span class="nb">    fine:</span>
<span class="nb">        extract_counter </span><span class="o">-</span><span class="nb">dir up </span><span class="o">-</span><span class="nb">allow_arst no</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">coolrunner</span><span class="m">2</span><span class="o">/</span><span class="nb">cells_counter_map.v</span>
<span class="nb">        clean</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast </span><span class="o">-</span><span class="nb">full</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">techmap.v </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">coolrunner</span><span class="m">2</span><span class="o">/</span><span class="nb">cells_latch.v</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast</span>
<span class="nb">        dfflibmap </span><span class="o">-</span><span class="nb">prepare </span><span class="o">-</span><span class="nb">liberty </span><span class="o">+/</span><span class="nb">coolrunner</span><span class="m">2</span><span class="o">/</span><span class="nb">xc</span><span class="m">2</span><span class="nb">_dff.lib</span>

<span class="nb">    map_tff:</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">g AND,XOR</span>
<span class="nb">        clean</span>
<span class="nb">        extract </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">coolrunner</span><span class="m">2</span><span class="o">/</span><span class="nb">tff_extract.v</span>

<span class="nb">    map_pla:</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">sop </span><span class="o">-</span><span class="nb">I </span><span class="m">40</span><span class="nb"> </span><span class="o">-</span><span class="nb">P </span><span class="m">56</span><span class="nb"></span>
<span class="nb">        clean</span>

<span class="nb">    map_cells:</span>
<span class="nb">        dfflibmap </span><span class="o">-</span><span class="nb">liberty </span><span class="o">+/</span><span class="nb">coolrunner</span><span class="m">2</span><span class="o">/</span><span class="nb">xc</span><span class="m">2</span><span class="nb">_dff.lib</span>
<span class="nb">        dffinit </span><span class="o">-</span><span class="nb">ff FDCP Q INIT</span>
<span class="nb">        dffinit </span><span class="o">-</span><span class="nb">ff FDCP_N Q INIT</span>
<span class="nb">        dffinit </span><span class="o">-</span><span class="nb">ff FTCP Q INIT</span>
<span class="nb">        dffinit </span><span class="o">-</span><span class="nb">ff FTCP_N Q INIT</span>
<span class="nb">        dffinit </span><span class="o">-</span><span class="nb">ff LDCP Q INIT</span>
<span class="nb">        dffinit </span><span class="o">-</span><span class="nb">ff LDCP_N Q INIT</span>
<span class="nb">        coolrunner</span><span class="m">2</span><span class="nb">_sop</span>
<span class="nb">        clean</span>
<span class="nb">        iopadmap </span><span class="o">-</span><span class="nb">bits </span><span class="o">-</span><span class="nb">inpad IBUF O:I </span><span class="o">-</span><span class="nb">outpad IOBUFE I:IO </span><span class="o">-</span><span class="nb">inoutpad IOBUFE O:IO </span><span class="o">-</span><span class="nb">toutpad IOBUFE E:I:IO </span><span class="o">-</span><span class="nb">tinoutpad IOBUFE E:O:I:IO</span>
<span class="nb">        attrmvcp </span><span class="o">-</span><span class="nb">attr src </span><span class="o">-</span><span class="nb">attr LOC t:IOBUFE n:</span><span class="o">*</span><span class="nb"></span>
<span class="nb">        attrmvcp </span><span class="o">-</span><span class="nb">attr src </span><span class="o">-</span><span class="nb">attr LOC </span><span class="o">-</span><span class="nb">driven t:IBUF n:</span><span class="o">*</span><span class="nb"></span>
<span class="nb">        coolrunner</span><span class="m">2</span><span class="nb">_fixup</span>
<span class="nb">        splitnets</span>
<span class="nb">        clean</span>

<span class="nb">    check:</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        stat</span>
<span class="nb">        check </span><span class="o">-</span><span class="nb">noinit</span>

<span class="nb">    json:</span>
<span class="nb">        write_json &lt;file</span><span class="o">-</span><span class="nb">name&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{synth</span><span class="nv">\_</span><span class="nb">easic </span><span class="o">--</span><span class="nb"> synthesis for eASIC platform}</span>
<span class="nv">\label</span><span class="nb">{cmd:synth_easic}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    synth_easic </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command runs synthesis for eASIC platform.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top &lt;module&gt;</span>
<span class="nb">        use the specified module as top module</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">vlog &lt;file&gt;</span>
<span class="nb">        write the design to the specified structural Verilog file. writing of</span>
<span class="nb">        an output file is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">etools &lt;path&gt;</span>
<span class="nb">        set path to the eTools installation. </span><span class="o">(</span><span class="nb">default</span><span class="o">=/</span><span class="nb">opt</span><span class="o">/</span><span class="nb">eTools</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">run &lt;from_label&gt;:&lt;to_label&gt;</span>
<span class="nb">        only run the commands between the labels </span><span class="o">(</span><span class="nb">see below</span><span class="o">)</span><span class="nb">. an empty</span>
<span class="nb">        from label is synonymous to &#39;begin&#39;, and empty to label is</span>
<span class="nb">        synonymous to the end of the command list.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noflatten</span>
<span class="nb">        do not flatten design before synthesis</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">retime</span>
<span class="nb">        run &#39;abc&#39; with &#39;</span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">&#39; options</span>


<span class="nb">The following commands are executed by this synthesis command:</span>

<span class="nb">    begin:</span>
<span class="nb">        read_liberty </span><span class="o">-</span><span class="nb">lib &lt;etools_phys_clk_lib&gt;</span>
<span class="nb">        read_liberty </span><span class="o">-</span><span class="nb">lib &lt;etools_logic_lut_lib&gt;</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top &lt;top&gt;</span>

<span class="nb">    flatten:    </span><span class="o">(</span><span class="nb">unless </span><span class="o">-</span><span class="nb">noflatten</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        proc</span>
<span class="nb">        flatten</span>

<span class="nb">    coarse:</span>
<span class="nb">        synth </span><span class="o">-</span><span class="nb">run coarse</span>

<span class="nb">    fine:</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast </span><span class="o">-</span><span class="nb">mux_undef </span><span class="o">-</span><span class="nb">undriven </span><span class="o">-</span><span class="nb">fine</span>
<span class="nb">        memory_map</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">undriven </span><span class="o">-</span><span class="nb">fine</span>
<span class="nb">        techmap</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">     </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">retime</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        opt_clean    </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">retime</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    map:</span>
<span class="nb">        dfflibmap </span><span class="o">-</span><span class="nb">liberty &lt;etools_phys_clk_lib&gt;</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">liberty &lt;etools_logic_lut_lib&gt;</span>
<span class="nb">        opt_clean</span>

<span class="nb">    check:</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        stat</span>
<span class="nb">        check </span><span class="o">-</span><span class="nb">noinit</span>

<span class="nb">    vlog:</span>
<span class="nb">        write_verilog </span><span class="o">-</span><span class="nb">noexpr </span><span class="o">-</span><span class="nb">attr</span><span class="m">2</span><span class="nb">comment &lt;file</span><span class="o">-</span><span class="nb">name&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{synth</span><span class="nv">\_</span><span class="nb">ecp</span><span class="m">5</span><span class="nb"> </span><span class="o">--</span><span class="nb"> synthesis for ECP</span><span class="m">5</span><span class="nb"> FPGAs}</span>
<span class="nv">\label</span><span class="nb">{cmd:synth_ecp</span><span class="m">5</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    synth_ecp</span><span class="m">5</span><span class="nb"> </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command runs synthesis for ECP</span><span class="m">5</span><span class="nb"> FPGAs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top &lt;module&gt;</span>
<span class="nb">        use the specified module as top module</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">blif &lt;file&gt;</span>
<span class="nb">        write the design to the specified BLIF file. writing of an output file</span>
<span class="nb">        is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">edif &lt;file&gt;</span>
<span class="nb">        write the design to the specified EDIF file. writing of an output file</span>
<span class="nb">        is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">json &lt;file&gt;</span>
<span class="nb">        write the design to the specified JSON file. writing of an output file</span>
<span class="nb">        is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">run &lt;from_label&gt;:&lt;to_label&gt;</span>
<span class="nb">        only run the commands between the labels </span><span class="o">(</span><span class="nb">see below</span><span class="o">)</span><span class="nb">. an empty</span>
<span class="nb">        from label is synonymous to &#39;begin&#39;, and empty to label is</span>
<span class="nb">        synonymous to the end of the command list.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noflatten</span>
<span class="nb">        do not flatten design before synthesis</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">retime</span>
<span class="nb">        run &#39;abc&#39; with &#39;</span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">&#39; options</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noccu</span><span class="m">2</span><span class="nb"></span>
<span class="nb">        do not use CCU</span><span class="m">2</span><span class="nb"> cells in output netlist</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nodffe</span>
<span class="nb">        do not use flipflops with CE in output netlist</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nobram</span>
<span class="nb">        do not use block RAM cells in output netlist</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nolutram</span>
<span class="nb">        do not use LUT RAM cells in output netlist</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nowidelut</span>
<span class="nb">        do not use PFU muxes to implement LUTs larger than LUT</span><span class="m">4</span><span class="nb">s</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">asyncprld</span>
<span class="nb">        use async PRLD mode to implement DLATCH and DFFSR </span><span class="o">(</span><span class="nb">EXPERIMENTAL</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">abc</span><span class="m">2</span><span class="nb"></span>
<span class="nb">        run two passes of &#39;abc&#39; for slightly improved logic density</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">abc</span><span class="m">9</span><span class="nb"></span>
<span class="nb">        use new ABC</span><span class="m">9</span><span class="nb"> flow </span><span class="o">(</span><span class="nb">EXPERIMENTAL</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">vpr</span>
<span class="nb">        generate an output netlist </span><span class="o">(</span><span class="nb">and BLIF file</span><span class="o">)</span><span class="nb"> suitable for VPR</span>
<span class="nb">        </span><span class="o">(</span><span class="nb">this feature is experimental and incomplete</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nodsp</span>
<span class="nb">        do not map multipliers to MULT</span><span class="m">18</span><span class="nb">X</span><span class="m">18</span><span class="nb">D</span>


<span class="nb">The following commands are executed by this synthesis command:</span>

<span class="nb">    begin:</span>
<span class="nb">        read_verilog </span><span class="o">-</span><span class="nb">lib </span><span class="o">-</span><span class="nb">specify </span><span class="o">+/</span><span class="nb">ecp</span><span class="m">5</span><span class="o">/</span><span class="nb">cells_sim.v </span><span class="o">+/</span><span class="nb">ecp</span><span class="m">5</span><span class="o">/</span><span class="nb">cells_bb.v</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top &lt;top&gt;</span>

<span class="nb">    coarse:</span>
<span class="nb">        proc</span>
<span class="nb">        flatten</span>
<span class="nb">        tribuf </span><span class="o">-</span><span class="nb">logic</span>
<span class="nb">        deminout</span>
<span class="nb">        opt_expr</span>
<span class="nb">        opt_clean</span>
<span class="nb">        check</span>
<span class="nb">        opt</span>
<span class="nb">        wreduce</span>
<span class="nb">        peepopt</span>
<span class="nb">        opt_clean</span>
<span class="nb">        share</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">cmp</span><span class="m">2</span><span class="nb">lut.v </span><span class="o">-</span><span class="nb">D LUT_WIDTH</span><span class="o">=</span><span class="m">4</span><span class="nb"></span>
<span class="nb">        opt_expr</span>
<span class="nb">        opt_clean</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">mul</span><span class="m">2</span><span class="nb">dsp.v </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">ecp</span><span class="m">5</span><span class="o">/</span><span class="nb">dsp_map.v </span><span class="o">-</span><span class="nb">D DSP_A_MAXWIDTH</span><span class="o">=</span><span class="m">18</span><span class="nb"> </span><span class="o">-</span><span class="nb">D DSP_B_MAXWIDTH</span><span class="o">=</span><span class="m">18</span><span class="nb">  </span><span class="o">-</span><span class="nb">D DSP_A_MINWIDTH</span><span class="o">=</span><span class="m">2</span><span class="nb"> </span><span class="o">-</span><span class="nb">D DSP_B_MINWIDTH</span><span class="o">=</span><span class="m">2</span><span class="nb">  </span><span class="o">-</span><span class="nb">D DSP_NAME</span><span class="o">=</span><span class="s">$</span><span class="nb">__</span>MUL18X18    (unless -nodsp)
        chtype -set <span class="s">$</span><span class="nb">mul t:</span><span class="s">$</span><span class="nb">__</span>soft<span class="nb">_</span>mul    (unless -nodsp)
        alumacc
        opt
        fsm
        opt -fast
        memory -nomap
        opt<span class="nb">_</span>clean

    map<span class="nb">_</span>bram:    (skip if -nobram)
        memory<span class="nb">_</span>bram -rules +/ecp5/brams.txt
        techmap -map +/ecp5/brams<span class="nb">_</span>map.v

    map<span class="nb">_</span>lutram:    (skip if -nolutram)
        memory<span class="nb">_</span>bram -rules +/ecp5/lutrams.txt
        techmap -map +/ecp5/lutrams<span class="nb">_</span>map.v

    map<span class="nb">_</span>ffram:
        opt -fast -mux<span class="nb">_</span>undef -undriven -fine
        memory<span class="nb">_</span>map -iattr -attr !ram<span class="nb">_</span>block -attr !rom<span class="nb">_</span>block -attr logic<span class="nb">_</span>block -attr syn<span class="nb">_</span>ramstyle=auto -attr syn<span class="nb">_</span>ramstyle=registers -attr syn<span class="nb">_</span>romstyle=auto -attr syn<span class="nb">_</span>romstyle=logic
        opt -undriven -fine

    map<span class="nb">_</span>gates:
        techmap -map +/techmap.v -map +/ecp5/arith<span class="nb">_</span>map.v
        opt -fast
        abc -dff -D 1    (only if -retime)

    map<span class="nb">_</span>ffs:
        dff2dffs
        opt<span class="nb">_</span>clean
        dff2dffe -direct-match <span class="s">$</span><span class="nb">_DFF_</span><span class="o">*</span><span class="nb"> </span><span class="o">-</span><span class="nb">direct</span><span class="o">-</span><span class="nb">match </span><span class="s">$</span><span class="nb">__</span>DFFS<span class="nb">_</span>*
        techmap -D NO<span class="nb">_</span>LUT [-D ASYNC<span class="nb">_</span>PRLD] -map +/ecp5/cells<span class="nb">_</span>map.v
        opt<span class="nb">_</span>expr -undriven -mux<span class="nb">_</span>undef
        simplemap
        ecp5<span class="nb">_</span>ffinit
        ecp5<span class="nb">_</span>gsr
        attrmvcp -copy -attr syn<span class="nb">_</span>useioff
        opt<span class="nb">_</span>clean

    map<span class="nb">_</span>luts:
        abc          (only if -abc2)
        techmap -map +/ecp5/latches<span class="nb">_</span>map.v
        abc -lut 4:7 -dress
        clean

    map<span class="nb">_</span>cells:
        techmap -map +/ecp5/cells<span class="nb">_</span>map.v    (with -D NO<span class="nb">_</span>LUT in vpr mode)
        opt<span class="nb">_</span>lut<span class="nb">_</span>ins -tech ecp5
        clean

    check:
        autoname
        hierarchy -check
        stat
        check -noinit

    blif:
        opt<span class="nb">_</span>clean -purge                                     (vpr mode)
        write<span class="nb">_</span>blif -attr -cname -conn -param &lt;file-name&gt;     (vpr mode)
        write<span class="nb">_</span>blif -gates -attr -param &lt;file-name&gt;           (non-vpr mode)

    edif:
        write<span class="nb">_</span>edif &lt;file-name&gt;

    json:
        write<span class="nb">_</span>json &lt;file-name&gt;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth<span class="k">\_</span>efinix -- synthesis for Efinix FPGAs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">_</span>efinix<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth<span class="nb">_</span>efinix [options]

This command runs synthesis for Efinix FPGAs.

    -top &lt;module&gt;
        use the specified module as top module

    -edif &lt;file&gt;
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json &lt;file&gt;
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run &#39;abc&#39; with &#39;-dff -D 1&#39; options

    -nobram
        do not use EFX<span class="nb">_</span>RAM<span class="nb">_</span>5K cells in output netlist


The following commands are executed by this synthesis command:

    begin:
        read<span class="nb">_</span>verilog -lib +/efinix/cells<span class="nb">_</span>sim.v
        hierarchy -check -top &lt;top&gt;

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse
        memory<span class="nb">_</span>bram -rules +/efinix/brams.txt
        techmap -map +/efinix/brams<span class="nb">_</span>map.v
        setundef -zero -params t:EFX<span class="nb">_</span>RAM<span class="nb">_</span>5K

    map<span class="nb">_</span>ffram:
        opt -fast -mux<span class="nb">_</span>undef -undriven -fine
        memory<span class="nb">_</span>map
        opt -undriven -fine

    map<span class="nb">_</span>gates:
        techmap -map +/techmap.v -map +/efinix/arith<span class="nb">_</span>map.v
        opt -fast
        abc -dff -D 1    (only if -retime)

    map<span class="nb">_</span>ffs:
        techmap -D NO<span class="nb">_</span>LUT -map +/efinix/cells<span class="nb">_</span>map.v
        dffinit -strinit SET RESET -ff AL<span class="nb">_</span>MAP<span class="nb">_</span>SEQ q REGSET -noreinit
        opt<span class="nb">_</span>expr -mux<span class="nb">_</span>undef
        simplemap

    map<span class="nb">_</span>luts:
        abc -lut 4
        clean

    map<span class="nb">_</span>cells:
        techmap -map +/efinix/cells<span class="nb">_</span>map.v
        clean

    map<span class="nb">_</span>gbuf:
        efinix<span class="nb">_</span>gbuf
        efinix<span class="nb">_</span>fixcarry
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    edif:
        write<span class="nb">_</span>edif &lt;file-name&gt;

    json:
        write<span class="nb">_</span>json &lt;file-name&gt;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth<span class="k">\_</span>gowin -- synthesis for Gowin FPGAs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">_</span>gowin<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth<span class="nb">_</span>gowin [options]

This command runs synthesis for Gowin FPGAs. This work is experimental.

    -top &lt;module&gt;
        use the specified module as top module (default=&#39;top&#39;)

    -vout &lt;file&gt;
        write the design to the specified Verilog netlist file. writing of an
        output file is omitted if this parameter is not specified.

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -nodffe
        do not use flipflops with CE in output netlist

    -nobram
        do not use BRAM cells in output netlist

    -nolutram
        do not use distributed RAM cells in output netlist

    -noflatten
        do not flatten design before synthesis

    -retime
        run &#39;abc&#39; with &#39;-dff -D 1&#39; options

    -nowidelut
        do not use muxes to implement LUTs larger than LUT4s

    -noiopads
        do not emit IOB at top level ports


The following commands are executed by this synthesis command:

    begin:
        read<span class="nb">_</span>verilog -lib +/gowin/cells<span class="nb">_</span>sim.v
        hierarchy -check -top &lt;top&gt;

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    map<span class="nb">_</span>bram:    (skip if -nobram)
        memory<span class="nb">_</span>bram -rules +/gowin/brams.txt
        techmap -map +/gowin/brams<span class="nb">_</span>map.v

    map<span class="nb">_</span>lutram:    (skip if -nolutram)
        memory<span class="nb">_</span>bram -rules +/gowin/lutrams.txt
        techmap -map +/gowin/lutrams<span class="nb">_</span>map.v
        determine<span class="nb">_</span>init

    map<span class="nb">_</span>ffram:
        opt -fast -mux<span class="nb">_</span>undef -undriven -fine
        memory<span class="nb">_</span>map
        opt -undriven -fine

    map<span class="nb">_</span>gates:
        techmap -map +/techmap.v -map +/gowin/arith<span class="nb">_</span>map.v
        opt -fast
        abc -dff -D 1    (only if -retime)
        splitnets

    map<span class="nb">_</span>ffs:
        dff2dffs -match-init
        opt<span class="nb">_</span>clean
        dff2dffe -direct-match <span class="s">$</span><span class="nb">_DFF_</span><span class="o">*</span><span class="nb"> </span><span class="o">-</span><span class="nb">direct</span><span class="o">-</span><span class="nb">match </span><span class="s">$</span><span class="nb">__</span>DFFS<span class="nb">_</span>*
        techmap -map +/gowin/cells<span class="nb">_</span>map.v
        opt<span class="nb">_</span>expr -mux<span class="nb">_</span>undef
        simplemap

    map<span class="nb">_</span>luts:
        abc -lut 4:8
        clean

    map<span class="nb">_</span>cells:
        techmap -map +/gowin/cells<span class="nb">_</span>map.v
        opt<span class="nb">_</span>lut<span class="nb">_</span>ins -tech gowin
        setundef -undriven -params -zero
        hilomap -singleton -hicell VCC V -locell GND G
        iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO    (unless -noiopads)
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    vout:
        write<span class="nb">_</span>verilog -decimal -attr2comment -defparam -renameprefix gen &lt;file-name&gt;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth<span class="k">\_</span>greenpak4 -- synthesis for GreenPAK4 FPGAs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">_</span>greenpak4<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth<span class="nb">_</span>greenpak4 [options]

This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.
It is intended to be used with https://github.com/azonenberg/openfpga as the
place-and-route.

    -top &lt;module&gt;
        use the specified module as top module (default=&#39;top&#39;)

    -part &lt;part&gt;
        synthesize for the specified part. Valid values are SLG46140V,
        SLG46620V, and SLG46621V (default).

    -json &lt;file&gt;
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run &#39;abc&#39; with &#39;-dff -D 1&#39; options


The following commands are executed by this synthesis command:

    begin:
        read<span class="nb">_</span>verilog -lib +/greenpak4/cells<span class="nb">_</span>sim.v
        hierarchy -check -top &lt;top&gt;

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic

    coarse:
        synth -run coarse

    fine:
        extract<span class="nb">_</span>counter -pout GP<span class="nb">_</span>DCMP,GP<span class="nb">_</span>DAC -maxwidth 14
        clean
        opt -fast -mux<span class="nb">_</span>undef -undriven -fine
        memory<span class="nb">_</span>map
        opt -undriven -fine
        techmap -map +/techmap.v -map +/greenpak4/cells<span class="nb">_</span>latch.v
        dfflibmap -prepare -liberty +/greenpak4/gp<span class="nb">_</span>dff.lib
        opt -fast
        abc -dff -D 1    (only if -retime)

    map<span class="nb">_</span>luts:
        nlutmap -assert -luts 0,6,8,2     (for -part SLG46140V)
        nlutmap -assert -luts 2,8,16,2    (for -part SLG46620V)
        nlutmap -assert -luts 2,8,16,2    (for -part SLG46621V)
        clean

    map<span class="nb">_</span>cells:
        shregmap -tech greenpak4
        dfflibmap -liberty +/greenpak4/gp<span class="nb">_</span>dff.lib
        dffinit -ff GP<span class="nb">_</span>DFF Q INIT
        dffinit -ff GP<span class="nb">_</span>DFFR Q INIT
        dffinit -ff GP<span class="nb">_</span>DFFS Q INIT
        dffinit -ff GP<span class="nb">_</span>DFFSR Q INIT
        iopadmap -bits -inpad GP<span class="nb">_</span>IBUF OUT:IN -outpad GP<span class="nb">_</span>OBUF IN:OUT -inoutpad GP<span class="nb">_</span>OBUF OUT:IN -toutpad GP<span class="nb">_</span>OBUFT OE:IN:OUT -tinoutpad GP<span class="nb">_</span>IOBUF OE:OUT:IN:IO
        attrmvcp -attr src -attr LOC t:GP<span class="nb">_</span>OBUF t:GP<span class="nb">_</span>OBUFT t:GP<span class="nb">_</span>IOBUF n:*
        attrmvcp -attr src -attr LOC -driven t:GP<span class="nb">_</span>IBUF n:*
        techmap -map +/greenpak4/cells<span class="nb">_</span>map.v
        greenpak4<span class="nb">_</span>dffinv
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    json:
        write<span class="nb">_</span>json &lt;file-name&gt;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth<span class="k">\_</span>ice40 -- synthesis for iCE40 FPGAs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">_</span>ice40<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth<span class="nb">_</span>ice40 [options]

This command runs synthesis for iCE40 FPGAs.

    -device &lt; hx | lp | u &gt;
        relevant only for &#39;-abc9&#39; flow, optimise timing for the specified device.
        default: hx

    -top &lt;module&gt;
        use the specified module as top module

    -blif &lt;file&gt;
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -edif &lt;file&gt;
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json &lt;file&gt;
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run &#39;abc&#39; with &#39;-dff -D 1&#39; options

    -nocarry
        do not use SB<span class="nb">_</span>CARRY cells in output netlist

    -nodffe
        do not use SB<span class="nb">_</span>DFFE* cells in output netlist

    -dffe<span class="nb">_</span>min<span class="nb">_</span>ce<span class="nb">_</span>use &lt;min<span class="nb">_</span>ce<span class="nb">_</span>use&gt;
        do not use SB<span class="nb">_</span>DFFE* cells if the resulting CE line would go to less
        than min<span class="nb">_</span>ce<span class="nb">_</span>use SB<span class="nb">_</span>DFFE* in output netlist

    -nobram
        do not use SB<span class="nb">_</span>RAM40<span class="nb">_</span>4K* cells in output netlist

    -dsp
        use iCE40 UltraPlus DSP cells for large arithmetic

    -noabc
        use built-in Yosys LUT techmapping instead of abc

    -abc2
        run two passes of &#39;abc&#39; for slightly improved logic density

    -vpr
        generate an output netlist (and BLIF file) suitable for VPR
        (this feature is experimental and incomplete)

    -abc9
        use new ABC9 flow (EXPERIMENTAL)

    -flowmap
        use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)


The following commands are executed by this synthesis command:

    begin:
        read<span class="nb">_</span>verilog -D ICE40<span class="nb">_</span>HX -lib -specify +/ice40/cells<span class="nb">_</span>sim.v
        hierarchy -check -top &lt;top&gt;
        proc

    flatten:    (unless -noflatten)
        flatten
        tribuf -logic
        deminout

    coarse:
        opt<span class="nb">_</span>expr
        opt<span class="nb">_</span>clean
        check
        opt
        wreduce
        peepopt
        opt<span class="nb">_</span>clean
        share
        techmap -map +/cmp2lut.v -D LUT<span class="nb">_</span>WIDTH=4
        opt<span class="nb">_</span>expr
        opt<span class="nb">_</span>clean
        memory<span class="nb">_</span>dff
        wreduce t:<span class="s">$</span><span class="nb">mul</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">mul</span><span class="m">2</span><span class="nb">dsp.v </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">ice</span><span class="m">40</span><span class="o">/</span><span class="nb">dsp_map.v </span><span class="o">-</span><span class="nb">D DSP_A_MAXWIDTH</span><span class="o">=</span><span class="m">16</span><span class="nb"> </span><span class="o">-</span><span class="nb">D DSP_B_MAXWIDTH</span><span class="o">=</span><span class="m">16</span><span class="nb"> </span><span class="o">-</span><span class="nb">D DSP_A_MINWIDTH</span><span class="o">=</span><span class="m">2</span><span class="nb"> </span><span class="o">-</span><span class="nb">D DSP_B_MINWIDTH</span><span class="o">=</span><span class="m">2</span><span class="nb"> </span><span class="o">-</span><span class="nb">D DSP_Y_MINWIDTH</span><span class="o">=</span><span class="m">11</span><span class="nb"> </span><span class="o">-</span><span class="nb">D DSP_NAME</span><span class="o">=</span><span class="s">$</span><span class="nb">__</span>MUL16X16    (if -dsp)
        select a:mul2dsp                  (if -dsp)
        setattr -unset mul2dsp            (if -dsp)
        opt<span class="nb">_</span>expr -fine                    (if -dsp)
        wreduce                           (if -dsp)
        select -clear                     (if -dsp)
        ice40<span class="nb">_</span>dsp                         (if -dsp)
        chtype -set <span class="s">$</span><span class="nb">mul t:</span><span class="s">$</span><span class="nb">__</span>soft<span class="nb">_</span>mul    (if -dsp)
        alumacc
        opt
        fsm
        opt -fast
        memory -nomap
        opt<span class="nb">_</span>clean

    map<span class="nb">_</span>bram:    (skip if -nobram)
        memory<span class="nb">_</span>bram -rules +/ice40/brams.txt
        techmap -map +/ice40/brams<span class="nb">_</span>map.v
        ice40<span class="nb">_</span>braminit

    map<span class="nb">_</span>ffram:
        opt -fast -mux<span class="nb">_</span>undef -undriven -fine
        memory<span class="nb">_</span>map -iattr -attr !ram<span class="nb">_</span>block -attr !rom<span class="nb">_</span>block -attr logic<span class="nb">_</span>block -attr syn<span class="nb">_</span>ramstyle=auto -attr syn<span class="nb">_</span>ramstyle=registers -attr syn<span class="nb">_</span>romstyle=auto -attr syn<span class="nb">_</span>romstyle=logic
        opt -undriven -fine

    map<span class="nb">_</span>gates:
        ice40<span class="nb">_</span>wrapcarry
        techmap -map +/techmap.v -map +/ice40/arith<span class="nb">_</span>map.v
        opt -fast
        abc -dff -D 1    (only if -retime)
        ice40<span class="nb">_</span>opt

    map<span class="nb">_</span>ffs:
        dff2dffe -direct-match <span class="s">$</span><span class="nb">_DFF_</span><span class="o">*</span><span class="nb"></span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">D NO_LUT </span><span class="o">-</span><span class="nb">D NO_ADDER </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">ice</span><span class="m">40</span><span class="o">/</span><span class="nb">cells_map.v</span>
<span class="nb">        opt_expr </span><span class="o">-</span><span class="nb">mux_undef</span>
<span class="nb">        simplemap</span>
<span class="nb">        ice</span><span class="m">40</span><span class="nb">_ffinit</span>
<span class="nb">        ice</span><span class="m">40</span><span class="nb">_ffssr</span>
<span class="nb">        ice</span><span class="m">40</span><span class="nb">_opt </span><span class="o">-</span><span class="nb">full</span>

<span class="nb">    map_luts:</span>
<span class="nb">        abc          </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">abc</span><span class="m">2</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        ice</span><span class="m">40</span><span class="nb">_opt    </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">abc</span><span class="m">2</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">ice</span><span class="m">40</span><span class="o">/</span><span class="nb">latches_map.v</span>
<span class="nb">        simplemap                                   </span><span class="o">(</span><span class="nb">if </span><span class="o">-</span><span class="nb">noabc or </span><span class="o">-</span><span class="nb">flowmap</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">gate</span><span class="m">2</span><span class="nb">lut.v </span><span class="o">-</span><span class="nb">D LUT_WIDTH</span><span class="o">=</span><span class="m">4</span><span class="nb">    </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">noabc</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        flowmap </span><span class="o">-</span><span class="nb">maxlut </span><span class="m">4</span><span class="nb">    </span><span class="o">(</span><span class="nb">only if </span><span class="o">-</span><span class="nb">flowmap</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">dress </span><span class="o">-</span><span class="nb">lut </span><span class="m">4</span><span class="nb">    </span><span class="o">(</span><span class="nb">skip if </span><span class="o">-</span><span class="nb">noabc</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        ice</span><span class="m">40</span><span class="nb">_wrapcarry </span><span class="o">-</span><span class="nb">unwrap</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">D NO_LUT </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">ice</span><span class="m">40</span><span class="o">/</span><span class="nb">cells_map.v</span>
<span class="nb">        clean</span>
<span class="nb">        opt_lut </span><span class="o">-</span><span class="nb">dlogic SB_CARRY:I</span><span class="m">0</span><span class="o">=</span><span class="m">2</span><span class="nb">:I</span><span class="m">1</span><span class="o">=</span><span class="m">1</span><span class="nb">:CI</span><span class="o">=</span><span class="m">0</span><span class="nb"></span>

<span class="nb">    map_cells:</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">ice</span><span class="m">40</span><span class="o">/</span><span class="nb">cells_map.v    </span><span class="o">(</span><span class="nb">with </span><span class="o">-</span><span class="nb">D NO_LUT in vpr mode</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        clean</span>

<span class="nb">    check:</span>
<span class="nb">        autoname</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        stat</span>
<span class="nb">        check </span><span class="o">-</span><span class="nb">noinit</span>

<span class="nb">    blif:</span>
<span class="nb">        opt_clean </span><span class="o">-</span><span class="nb">purge                                     </span><span class="o">(</span><span class="nb">vpr mode</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        write_blif </span><span class="o">-</span><span class="nb">attr </span><span class="o">-</span><span class="nb">cname </span><span class="o">-</span><span class="nb">conn </span><span class="o">-</span><span class="nb">param &lt;file</span><span class="o">-</span><span class="nb">name&gt;     </span><span class="o">(</span><span class="nb">vpr mode</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        write_blif </span><span class="o">-</span><span class="nb">gates </span><span class="o">-</span><span class="nb">attr </span><span class="o">-</span><span class="nb">param &lt;file</span><span class="o">-</span><span class="nb">name&gt;           </span><span class="o">(</span><span class="nb">non</span><span class="o">-</span><span class="nb">vpr mode</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    edif:</span>
<span class="nb">        write_edif &lt;file</span><span class="o">-</span><span class="nb">name&gt;</span>

<span class="nb">    json:</span>
<span class="nb">        write_json &lt;file</span><span class="o">-</span><span class="nb">name&gt;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{synth</span><span class="nv">\_</span><span class="nb">intel </span><span class="o">--</span><span class="nb"> synthesis for Intel </span><span class="o">(</span><span class="nb">Altera</span><span class="o">)</span><span class="nb"> FPGAs.}</span>
<span class="nv">\label</span><span class="nb">{cmd:synth_intel}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    synth_intel </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command runs synthesis for Intel FPGAs.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">family &lt;max</span><span class="m">10</span><span class="nb"> | arria</span><span class="m">10</span><span class="nb">gx | cyclone</span><span class="m">10</span><span class="nb">lp | cyclonev | cycloneiv | cycloneive&gt;</span>
<span class="nb">        generate the synthesis netlist for the specified family.</span>
<span class="nb">        MAX</span><span class="m">10</span><span class="nb"> is the default target if no family argument specified.</span>
<span class="nb">        For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.</span>
<span class="nb">        Cyclone V and Arria </span><span class="m">10</span><span class="nb"> GX devices are experimental.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top &lt;module&gt;</span>
<span class="nb">        use the specified module as top module </span><span class="o">(</span><span class="nb">default</span><span class="o">=</span><span class="nb">&#39;top&#39;</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">vqm &lt;file&gt;</span>
<span class="nb">        write the design to the specified Verilog Quartus Mapping File. Writing of an</span>
<span class="nb">        output file is omitted if this parameter is not specified.</span>
<span class="nb">        Note that this backend has not been tested and is likely incompatible</span>
<span class="nb">        with recent versions of Quartus.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">vpr &lt;file&gt;</span>
<span class="nb">        write BLIF files for VPR flow experiments. The synthesized BLIF output file is not</span>
<span class="nb">        compatible with the Quartus flow. Writing of an</span>
<span class="nb">        output file is omitted if this parameter is not specified.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">run &lt;from_label&gt;:&lt;to_label&gt;</span>
<span class="nb">        only run the commands between the labels </span><span class="o">(</span><span class="nb">see below</span><span class="o">)</span><span class="nb">. an empty</span>
<span class="nb">        from label is synonymous to &#39;begin&#39;, and empty to label is</span>
<span class="nb">        synonymous to the end of the command list.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">iopads</span>
<span class="nb">        use IO pad cells in output netlist</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nobram</span>
<span class="nb">        do not use block RAM cells in output netlist</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noflatten</span>
<span class="nb">        do not flatten design before synthesis</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">retime</span>
<span class="nb">        run &#39;abc&#39; with &#39;</span><span class="o">-</span><span class="nb">dff </span><span class="o">-</span><span class="nb">D </span><span class="m">1</span><span class="nb">&#39; options</span>

<span class="nb">The following commands are executed by this synthesis command:</span>

<span class="nb">    begin:</span>

<span class="nb">    family:</span>
<span class="nb">        read_verilog </span><span class="o">-</span><span class="nb">sv </span><span class="o">-</span><span class="nb">lib </span><span class="o">+/</span><span class="nb">intel</span><span class="o">/</span><span class="nb">max</span><span class="m">10</span><span class="o">/</span><span class="nb">cells_sim.v</span>
<span class="nb">        read_verilog </span><span class="o">-</span><span class="nb">sv </span><span class="o">-</span><span class="nb">lib </span><span class="o">+/</span><span class="nb">intel</span><span class="o">/</span><span class="nb">common</span><span class="o">/</span><span class="nb">m</span><span class="m">9</span><span class="nb">k_bb.v</span>
<span class="nb">        read_verilog </span><span class="o">-</span><span class="nb">sv </span><span class="o">-</span><span class="nb">lib </span><span class="o">+/</span><span class="nb">intel</span><span class="o">/</span><span class="nb">common</span><span class="o">/</span><span class="nb">altpll_bb.v</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top &lt;top&gt;</span>

<span class="nb">    flatten:    </span><span class="o">(</span><span class="nb">unless </span><span class="o">-</span><span class="nb">noflatten</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        proc</span>
<span class="nb">        flatten</span>
<span class="nb">        tribuf </span><span class="o">-</span><span class="nb">logic</span>
<span class="nb">        deminout</span>

<span class="nb">    coarse:</span>
<span class="nb">        synth </span><span class="o">-</span><span class="nb">run coarse</span>

<span class="nb">    map_bram:    </span><span class="o">(</span><span class="nb">skip if </span><span class="o">-</span><span class="nb">nobram</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        memory_bram </span><span class="o">-</span><span class="nb">rules </span><span class="o">+/</span><span class="nb">intel</span><span class="o">/</span><span class="nb">common</span><span class="o">/</span><span class="nb">brams_m</span><span class="m">9</span><span class="nb">k.txt    </span><span class="o">(</span><span class="nb">if applicable for family</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">intel</span><span class="o">/</span><span class="nb">common</span><span class="o">/</span><span class="nb">brams_map_m</span><span class="m">9</span><span class="nb">k.v    </span><span class="o">(</span><span class="nb">if applicable for family</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    map_ffram:</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast </span><span class="o">-</span><span class="nb">mux_undef </span><span class="o">-</span><span class="nb">undriven </span><span class="o">-</span><span class="nb">fine </span><span class="o">-</span><span class="nb">full</span>
<span class="nb">        memory_map</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">undriven </span><span class="o">-</span><span class="nb">fine</span>
<span class="nb">        dff</span><span class="m">2</span><span class="nb">dffe </span><span class="o">-</span><span class="nb">direct</span><span class="o">-</span><span class="nb">match </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>*
        opt -fine
        techmap -map +/techmap.v
        opt -full
        clean -purge
        setundef -undriven -zero
        abc -markgroups -dff -D 1    (only if -retime)

    map<span class="nb">_</span>luts:
        abc -lut 4
        clean

    map<span class="nb">_</span>cells:
        iopadmap -bits -outpad <span class="s">$</span><span class="nb">__outpad I:O </span><span class="o">-</span><span class="nb">inpad </span><span class="s">$</span><span class="nb">__</span>inpad O:I    (if -iopads)
        techmap -map +/intel/max10/cells<span class="nb">_</span>map.v
        dffinit -highlow -ff dffeas q power<span class="nb">_</span>up
        clean -purge

    check:
        hierarchy -check
        stat
        check -noinit

    vqm:
        write<span class="nb">_</span>verilog -attr2comment -defparam -nohex -decimal -renameprefix syn<span class="nb">_</span> &lt;file-name&gt;

    vpr:
        opt<span class="nb">_</span>clean -purge
        write<span class="nb">_</span>blif &lt;file-name&gt;


WARNING: THE &#39;synth<span class="nb">_</span>intel&#39; COMMAND IS EXPERIMENTAL.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth<span class="k">\_</span>sf2 -- synthesis for SmartFusion2 and IGLOO2 FPGAs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">_</span>sf2<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth<span class="nb">_</span>sf2 [options]

This command runs synthesis for SmartFusion2 and IGLOO2 FPGAs.

    -top &lt;module&gt;
        use the specified module as top module

    -edif &lt;file&gt;
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -vlog &lt;file&gt;
        write the design to the specified Verilog file. writing of an output file
        is omitted if this parameter is not specified.

    -json &lt;file&gt;
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -noiobs
        run synthesis in &quot;block mode&quot;, i.e. do not insert IO buffers

    -clkbuf
        insert direct PAD-&gt;global<span class="nb">_</span>net buffers

    -retime
        run &#39;abc&#39; with &#39;-dff -D 1&#39; options


The following commands are executed by this synthesis command:

    begin:
        read<span class="nb">_</span>verilog -lib +/sf2/cells<span class="nb">_</span>sim.v
        hierarchy -check -top &lt;top&gt;

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    fine:
        opt -fast -mux<span class="nb">_</span>undef -undriven -fine
        memory<span class="nb">_</span>map
        opt -undriven -fine
        techmap -map +/techmap.v -map +/sf2/arith<span class="nb">_</span>map.v
        opt -fast
        abc -dff -D 1    (only if -retime)

    map<span class="nb">_</span>ffs:
        techmap -D NO<span class="nb">_</span>LUT -map +/sf2/cells<span class="nb">_</span>map.v
        opt<span class="nb">_</span>expr -mux<span class="nb">_</span>undef
        simplemap

    map<span class="nb">_</span>luts:
        abc -lut 4
        clean

    map<span class="nb">_</span>cells:
        techmap -map +/sf2/cells<span class="nb">_</span>map.v
        clean

    map<span class="nb">_</span>iobs:
        sf2<span class="nb">_</span>iobs [-clkbuf]    (unless -noiobs)
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    edif:
        write<span class="nb">_</span>edif -gndvccy &lt;file-name&gt;

    vlog:
        write<span class="nb">_</span>verilog &lt;file-name&gt;

    json:
        write<span class="nb">_</span>json &lt;file-name&gt;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>synth<span class="k">\_</span>xilinx -- synthesis for Xilinx FPGAs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:synth<span class="nb">_</span>xilinx<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    synth<span class="nb">_</span>xilinx [options]

This command runs synthesis for Xilinx FPGAs. This command does not operate on
partly selected designs. At the moment this command creates netlists that are
compatible with 7-Series Xilinx devices.

    -top &lt;module&gt;
        use the specified module as top module

    -family &lt;family&gt;
        run synthesis for the specified Xilinx architecture
        generate the synthesis netlist for the specified family.
        supported values:
        - xcup: Ultrascale Plus
        - xcu: Ultrascale
        - xc7: Series 7 (default)
        - xc6s: Spartan 6
        - xc6v: Virtex 6
        - xc5v: Virtex 5 (EXPERIMENTAL)
        - xc4v: Virtex 4 (EXPERIMENTAL)
        - xc3sda: Spartan 3A DSP (EXPERIMENTAL)
        - xc3sa: Spartan 3A (EXPERIMENTAL)
        - xc3se: Spartan 3E (EXPERIMENTAL)
        - xc3s: Spartan 3 (EXPERIMENTAL)
        - xc2vp: Virtex 2 Pro (EXPERIMENTAL)
        - xc2v: Virtex 2 (EXPERIMENTAL)
        - xcve: Virtex E, Spartan 2E (EXPERIMENTAL)
        - xcv: Virtex, Spartan 2 (EXPERIMENTAL)

    -edif &lt;file&gt;
        write the design to the specified edif file. writing of an output file
        is omitted if this parameter is not specified.

    -blif &lt;file&gt;
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -vpr
        generate an output netlist (and BLIF file) suitable for VPR
        (this feature is experimental and incomplete)

    -ise
        generate an output netlist suitable for ISE

    -nobram
        do not use block RAM cells in output netlist

    -nolutram
        do not use distributed RAM cells in output netlist

    -nosrl
        do not use distributed SRL cells in output netlist

    -nocarry
        do not use XORCY/MUXCY/CARRY4 cells in output netlist

    -nowidelut
        do not use MUXF[5-9] resources to implement LUTs larger than native for the target

    -nodsp
        do not use DSP48*s to implement multipliers and associated logic

    -noiopad
        disable I/O buffer insertion (useful for hierarchical or 
        out-of-context flows)

    -noclkbuf
        disable automatic clock buffer insertion

    -uram
        infer URAM288s for large memories (xcup only)

    -widemux &lt;int&gt;
        enable inference of hard multiplexer resources (MUXF[78]) for muxes at or
        above this number of inputs (minimum value 2, recommended value &gt;= 5).
        default: 0 (no inference)

    -run &lt;from<span class="nb">_</span>label&gt;:&lt;to<span class="nb">_</span>label&gt;
        only run the commands between the labels (see below). an empty
        from label is synonymous to &#39;begin&#39;, and empty to label is
        synonymous to the end of the command list.

    -flatten
        flatten design before synthesis

    -dff
        run &#39;abc&#39;/&#39;abc9&#39; with -dff option

    -retime
        run &#39;abc&#39; with &#39;-D 1&#39; option to enable flip-flop retiming.
        implies -dff.

    -abc9
        use new ABC9 flow (EXPERIMENTAL)


The following commands are executed by this synthesis command:

    begin:
        read<span class="nb">_</span>verilog -lib -specify +/xilinx/cells<span class="nb">_</span>sim.v
        read<span class="nb">_</span>verilog -lib +/xilinx/cells<span class="nb">_</span>xtra.v
        hierarchy -check -auto-top

    prepare:
        proc
        flatten    (with &#39;-flatten&#39;)
        tribuf -logic
        deminout
        opt<span class="nb">_</span>expr
        opt<span class="nb">_</span>clean
        check
        opt
        wreduce [-keepdc]    (option for &#39;-widemux&#39;)
        peepopt
        opt<span class="nb">_</span>clean
        muxpack        (&#39;-widemux&#39; only)
        pmux2shiftx    (skip if &#39;-nosrl&#39; and &#39;-widemux=0&#39;)
        clean          (skip if &#39;-nosrl&#39; and &#39;-widemux=0&#39;)

    map<span class="nb">_</span>dsp:    (skip if &#39;-nodsp&#39;)
        memory<span class="nb">_</span>dff
        techmap -map +/mul2dsp.v -map +/xilinx/<span class="nb">{</span>family<span class="nb">}_</span>dsp<span class="nb">_</span>map.v <span class="nb">{</span>options<span class="nb">}</span>
        select a:mul2dsp
        setattr -unset mul2dsp
        opt<span class="nb">_</span>expr -fine
        wreduce
        select -clear
        xilinx<span class="nb">_</span>dsp -family &lt;family&gt;
        chtype -set <span class="s">$</span><span class="nb">mul t:</span><span class="s">$</span><span class="nb">__</span>soft<span class="nb">_</span>mul

    coarse:
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT<span class="nb">_</span>WIDTH=[46]
        alumacc
        share
        opt
        fsm
        opt -fast
        memory -nomap
        opt<span class="nb">_</span>clean

    map<span class="nb">_</span>uram:    (only if &#39;-uram&#39;)
        memory<span class="nb">_</span>bram -rules +/xilinx/<span class="nb">{</span>family<span class="nb">}_</span>urams.txt
        techmap -map +/xilinx/<span class="nb">{</span>family<span class="nb">}_</span>urams<span class="nb">_</span>map.v

    map<span class="nb">_</span>bram:    (skip if &#39;-nobram&#39;)
        memory<span class="nb">_</span>bram -rules +/xilinx/<span class="nb">{</span>family<span class="nb">}_</span>brams.txt
        techmap -map +/xilinx/<span class="nb">{</span>family<span class="nb">}_</span>brams<span class="nb">_</span>map.v

    map<span class="nb">_</span>lutram:    (skip if &#39;-nolutram&#39;)
        memory<span class="nb">_</span>bram -rules +/xilinx/lut[46]<span class="nb">_</span>lutrams.txt
        techmap -map +/xilinx/lutrams<span class="nb">_</span>map.v

    map<span class="nb">_</span>ffram:
        simplemap t:<span class="s">$</span><span class="nb">dff t:</span><span class="s">$</span>adff t:<span class="s">$</span><span class="nb">mux</span>
<span class="nb">        dff</span><span class="m">2</span><span class="nb">dffs </span><span class="o">[-</span><span class="nb">match</span><span class="o">-</span><span class="nb">init</span><span class="o">]</span><span class="nb">    </span><span class="o">(-</span><span class="nb">match</span><span class="o">-</span><span class="nb">init for xc</span><span class="m">6</span><span class="nb">s only</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast </span><span class="o">-</span><span class="nb">full</span>
<span class="nb">        memory_map</span>

<span class="nb">    fine:</span>
<span class="nb">        dff</span><span class="m">2</span><span class="nb">dffe </span><span class="o">-</span><span class="nb">direct</span><span class="o">-</span><span class="nb">match </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>* -direct-match <span class="s">$</span><span class="nb">__DFFS_</span><span class="o">*</span><span class="nb"></span>
<span class="nb">        muxcover &lt;internal options&gt; </span><span class="o">(</span><span class="nb">&#39;</span><span class="o">-</span><span class="nb">widemux&#39; only</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">full</span>
<span class="nb">        xilinx_srl </span><span class="o">-</span><span class="nb">variable </span><span class="o">-</span><span class="nb">minlen </span><span class="m">3</span><span class="nb">    </span><span class="o">(</span><span class="nb">skip if &#39;</span><span class="o">-</span><span class="nb">nosrl&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        techmap  </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">techmap.v </span><span class="o">-</span><span class="nb">D LUT_SIZE</span><span class="o">=[</span><span class="m">46</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">xilinx</span><span class="o">/</span><span class="nb">mux_map.v</span><span class="o">]</span><span class="nb"> </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">xilinx</span><span class="o">/</span><span class="nb">arith_map.v</span>
<span class="nb">        opt </span><span class="o">-</span><span class="nb">fast</span>

<span class="nb">    map_cells:</span>
<span class="nb">        iopadmap </span><span class="o">-</span><span class="nb">bits </span><span class="o">-</span><span class="nb">outpad OBUF I:O </span><span class="o">-</span><span class="nb">inpad IBUF O:I </span><span class="o">-</span><span class="nb">toutpad </span><span class="s">$</span><span class="nb">__</span>XILINX<span class="nb">_</span>TOUTPAD OE:I:O -tinoutpad <span class="s">$</span><span class="nb">__XILINX_TINOUTPAD OE:O:I:IO A:top    </span><span class="o">(</span><span class="nb">skip if &#39;</span><span class="o">-</span><span class="nb">noiopad&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">techmap.v </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">xilinx</span><span class="o">/</span><span class="nb">cells_map.v</span>
<span class="nb">        clean</span>

<span class="nb">    map_ffs:</span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">xilinx</span><span class="o">/</span><span class="nb">{family}_ff_map.v    </span><span class="o">(</span><span class="nb">&#39;</span><span class="o">-</span><span class="nb">abc</span><span class="m">9</span><span class="nb">&#39; only</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    map_luts:</span>
<span class="nb">        opt_expr </span><span class="o">-</span><span class="nb">mux_undef</span>
<span class="nb">        abc </span><span class="o">-</span><span class="nb">luts </span><span class="m">2</span><span class="nb">:</span><span class="m">2</span><span class="nb">,</span><span class="m">3</span><span class="nb">,</span><span class="m">6</span><span class="nb">:</span><span class="m">5</span><span class="o">[</span><span class="nb">,</span><span class="m">10</span><span class="nb">,</span><span class="m">20</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">dff</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">D </span><span class="m">1</span><span class="o">]</span><span class="nb">    </span><span class="o">(</span><span class="nb">option for &#39;nowidelut&#39;, &#39;</span><span class="o">-</span><span class="nb">dff&#39;, &#39;</span><span class="o">-</span><span class="nb">retime&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        clean</span>
<span class="nb">        xilinx_srl </span><span class="o">-</span><span class="nb">fixed </span><span class="o">-</span><span class="nb">minlen </span><span class="m">3</span><span class="nb">    </span><span class="o">(</span><span class="nb">skip if &#39;</span><span class="o">-</span><span class="nb">nosrl&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        techmap </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">xilinx</span><span class="o">/</span><span class="nb">lut_map.v </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">xilinx</span><span class="o">/</span><span class="nb">cells_map.v </span><span class="o">-</span><span class="nb">map </span><span class="o">+/</span><span class="nb">xilinx</span><span class="o">/</span><span class="nb">{family}_ff_map.v </span><span class="o">-</span><span class="nb">D LUT_WIDTH</span><span class="o">=[</span><span class="m">46</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        xilinx_dffopt </span><span class="o">[-</span><span class="nb">lut</span><span class="m">4</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        opt_lut_ins </span><span class="o">-</span><span class="nb">tech xilinx</span>

<span class="nb">    finalize:</span>
<span class="nb">        clkbufmap </span><span class="o">-</span><span class="nb">buf BUFG O:I    </span><span class="o">(</span><span class="nb">skip if &#39;</span><span class="o">-</span><span class="nb">noclkbuf&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        extractinv </span><span class="o">-</span><span class="nb">inv INV O:I    </span><span class="o">(</span><span class="nb">only if &#39;</span><span class="o">-</span><span class="nb">ise&#39;</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        clean</span>

<span class="nb">    check:</span>
<span class="nb">        hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nb">        stat </span><span class="o">-</span><span class="nb">tech xilinx</span>
<span class="nb">        check </span><span class="o">-</span><span class="nb">noinit</span>

<span class="nb">    edif:</span>
<span class="nb">        write_edif </span><span class="o">-</span><span class="nb">pvector bra </span>

<span class="nb">    blif:</span>
<span class="nb">        write_blif </span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{tcl </span><span class="o">--</span><span class="nb"> execute a TCL script file}</span>
<span class="nv">\label</span><span class="nb">{cmd:tcl}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    tcl &lt;filename&gt; </span><span class="o">[</span><span class="nb">args</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command executes the tcl commands in the specified file.</span>
<span class="nb">Use &#39;yosys cmd&#39; to run the yosys command &#39;cmd&#39; from tcl.</span>

<span class="nb">The tcl command &#39;yosys </span><span class="o">-</span><span class="nb">import&#39; can be used to import all yosys</span>
<span class="nb">commands directly as tcl commands to the tcl shell. Yosys commands</span>
<span class="nb">&#39;proc&#39; and &#39;rename&#39; are wrapped to tcl commands &#39;procs&#39; and &#39;renames&#39;</span>
<span class="nb">in order to avoid a name collision with the built in commands.</span>

<span class="nb">If any arguments are specified, these arguments are provided to the script via</span>
<span class="nb">the standard </span><span class="s">$</span>argc and <span class="s">$</span><span class="nb">argv variables.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{techmap </span><span class="o">--</span><span class="nb"> generic technology mapper}</span>
<span class="nv">\label</span><span class="nb">{cmd:techmap}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    techmap </span><span class="o">[-</span><span class="nb">map filename</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass implements a very simple technology mapper that replaces cells in</span>
<span class="nb">the design with implementations given in form of a Verilog or ilang source</span>
<span class="nb">file.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">map filename</span>
<span class="nb">        the library of cell implementations to be used.</span>
<span class="nb">        without this parameter a builtin library is used that</span>
<span class="nb">        transforms the internal RTL cells to the internal gate</span>
<span class="nb">        library.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">map </span><span class="c">%&lt;design-name&gt;</span>
<span class="nb">        like </span><span class="o">-</span><span class="nb">map above, but with an in</span><span class="o">-</span><span class="nb">memory design instead of a file.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">extern</span>
<span class="nb">        load the cell implementations as separate modules into the design</span>
<span class="nb">        instead of inlining them.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">max_iter &lt;number&gt;</span>
<span class="nb">        only run the specified number of iterations on each module.</span>
<span class="nb">        default: unlimited</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">recursive</span>
<span class="nb">        instead of the iterative breadth</span><span class="o">-</span><span class="nb">first algorithm use a recursive</span>
<span class="nb">        depth</span><span class="o">-</span><span class="nb">first algorithm. both methods should yield equivalent results,</span>
<span class="nb">        but may differ in performance.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">autoproc</span>
<span class="nb">        Automatically call &quot;proc&quot; on implementations that contain processes.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">wb</span>
<span class="nb">        Ignore the &#39;whitebox&#39; attribute on cell implementations.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">assert</span>
<span class="nb">        this option will cause techmap to exit with an error if it can&#39;t map</span>
<span class="nb">        a selected cell. only cell types that end on an underscore are accepted</span>
<span class="nb">        as final cell types by this mode.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">D &lt;define&gt;, </span><span class="o">-</span><span class="nb">I &lt;incdir&gt;</span>
<span class="nb">        this options are passed as</span><span class="o">-</span><span class="nb">is to the Verilog frontend for loading the</span>
<span class="nb">        map file. Note that the Verilog frontend is also called with the</span>
<span class="nb">        &#39;</span><span class="o">-</span><span class="nb">nooverwrite&#39; option set.</span>

<span class="nb">When a module in the map file has the &#39;techmap_celltype&#39; attribute set, it will</span>
<span class="nb">match cells with a type that match the text value of this attribute. Otherwise</span>
<span class="nb">the module name will be used to match the cell.</span>

<span class="nb">When a module in the map file has the &#39;techmap_simplemap&#39; attribute set, techmap</span>
<span class="nb">will use &#39;simplemap&#39; </span><span class="o">(</span><span class="nb">see &#39;help simplemap&#39;</span><span class="o">)</span><span class="nb"> to map cells matching the module.</span>

<span class="nb">When a module in the map file has the &#39;techmap_maccmap&#39; attribute set, techmap</span>
<span class="nb">will use &#39;maccmap&#39; </span><span class="o">(</span><span class="nb">see &#39;help maccmap&#39;</span><span class="o">)</span><span class="nb"> to map cells matching the module.</span>

<span class="nb">When a module in the map file has the &#39;techmap_wrap&#39; attribute set, techmap</span>
<span class="nb">will create a wrapper for the cell and then run the command string that the</span>
<span class="nb">attribute is set to on the wrapper module.</span>

<span class="nb">When a port on a module in the map file has the &#39;techmap_autopurge&#39; attribute</span>
<span class="nb">set, and that port is not connected in the instantiation that is mapped, then</span>
<span class="nb">then a cell port connected only to such wires will be omitted in the mapped</span>
<span class="nb">version of the circuit.</span>

<span class="nb">All wires in the modules from the map file matching the pattern _TECHMAP_</span><span class="o">*</span><span class="nb"></span>
<span class="nb">or </span><span class="o">*</span><span class="nb">._TECHMAP_</span><span class="o">*</span><span class="nb"> are special wires that are used to pass instructions from</span>
<span class="nb">the mapping module to the techmap command. At the moment the following special</span>
<span class="nb">wires are supported:</span>

<span class="nb">    _TECHMAP_FAIL_</span>
<span class="nb">        When this wire is set to a non</span><span class="o">-</span><span class="nb">zero constant value, techmap will not</span>
<span class="nb">        use this module and instead try the next module with a matching</span>
<span class="nb">        &#39;techmap_celltype&#39; attribute.</span>

<span class="nb">        When such a wire exists but does not have a constant value after all</span>
<span class="nb">        _TECHMAP_DO_</span><span class="o">*</span><span class="nb"> commands have been executed, an error is generated.</span>

<span class="nb">    _TECHMAP_DO_</span><span class="o">*</span><span class="nb"></span>
<span class="nb">        This wires are evaluated in alphabetical order. The constant text value</span>
<span class="nb">        of this wire is a yosys command </span><span class="o">(</span><span class="nb">or sequence of commands</span><span class="o">)</span><span class="nb"> that is run</span>
<span class="nb">        by techmap on the module. A common use case is to run &#39;proc&#39; on modules</span>
<span class="nb">        that are written using always</span><span class="o">-</span><span class="nb">statements.</span>

<span class="nb">        When such a wire has a non</span><span class="o">-</span><span class="nb">constant value at the time it is to be</span>
<span class="nb">        evaluated, an error is produced. That means it is possible for such a</span>
<span class="nb">        wire to start out as non</span><span class="o">-</span><span class="nb">constant and evaluate to a constant value</span>
<span class="nb">        during processing of other _TECHMAP_DO_</span><span class="o">*</span><span class="nb"> commands.</span>

<span class="nb">        A _TECHMAP_DO_</span><span class="o">*</span><span class="nb"> command may start with the special token &#39;CONSTMAP; &#39;.</span>
<span class="nb">        in this case techmap will create a copy for each distinct configuration</span>
<span class="nb">        of constant inputs and shorted inputs at this point and import the</span>
<span class="nb">        constant and connected bits into the map module. All further commands</span>
<span class="nb">        are executed in this copy. This is a very convenient way of creating</span>
<span class="nb">        optimized specializations of techmap modules without using the special</span>
<span class="nb">        parameters described below.</span>

<span class="nb">        A _TECHMAP_DO_</span><span class="o">*</span><span class="nb"> command may start with the special token &#39;RECURSION; &#39;.</span>
<span class="nb">        then techmap will recursively replace the cells in the module with their</span>
<span class="nb">        implementation. This is not affected by the </span><span class="o">-</span><span class="nb">max_iter option.</span>

<span class="nb">        It is possible to combine both prefixes to &#39;RECURSION; CONSTMAP; &#39;.</span>

<span class="nb">    _TECHMAP_REMOVEINIT_&lt;port</span><span class="o">-</span><span class="nb">name&gt;_</span>
<span class="nb">        When this wire is set to a constant value, the init attribute of the wire</span><span class="o">(</span><span class="nb">s</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        connected to this port will be consumed.  This wire must have the same</span>
<span class="nb">        width as the given port, and for every bit that is set to </span><span class="m">1</span><span class="nb"> in the value,</span>
<span class="nb">        the corresponding init attribute bit will be changed to </span><span class="m">1</span><span class="nb">&#39;bx.  If all</span>
<span class="nb">        bits of an init attribute are left as x, it will be removed.</span>

<span class="nb">In addition to this special wires, techmap also supports special parameters in</span>
<span class="nb">modules in the map file:</span>

<span class="nb">    _TECHMAP_CELLTYPE_</span>
<span class="nb">        When a parameter with this name exists, it will be set to the type name</span>
<span class="nb">        of the cell that matches the module.</span>

<span class="nb">    _TECHMAP_CONSTMSK_&lt;port</span><span class="o">-</span><span class="nb">name&gt;_</span>
<span class="nb">    _TECHMAP_CONSTVAL_&lt;port</span><span class="o">-</span><span class="nb">name&gt;_</span>
<span class="nb">        When this pair of parameters is available in a module for a port, then</span>
<span class="nb">        former has a </span><span class="m">1</span><span class="o">-</span><span class="nb">bit for each constant input bit and the latter has the</span>
<span class="nb">        value for this bit. The unused bits of the latter are set to undef </span><span class="o">(</span><span class="nb">x</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">    _TECHMAP_WIREINIT_&lt;port</span><span class="o">-</span><span class="nb">name&gt;_</span>
<span class="nb">        When a parameter with this name exists, it will be set to the initial</span>
<span class="nb">        value of the wire</span><span class="o">(</span><span class="nb">s</span><span class="o">)</span><span class="nb"> connected to the given port, as specified by the init</span>
<span class="nb">        attribute. If the attribute doesn&#39;t exist, x will be filled for the</span>
<span class="nb">        missing bits.  To remove the init attribute bits used, use the</span>
<span class="nb">        _TECHMAP_REMOVEINIT_</span><span class="o">*</span><span class="nb">_ wires.</span>

<span class="nb">    _TECHMAP_BITS_CONNMAP_</span>
<span class="nb">    _TECHMAP_CONNMAP_&lt;port</span><span class="o">-</span><span class="nb">name&gt;_</span>
<span class="nb">        For an N</span><span class="o">-</span><span class="nb">bit port, the _TECHMAP_CONNMAP_&lt;port</span><span class="o">-</span><span class="nb">name&gt;_ parameter, if it</span>
<span class="nb">        exists, will be set to an N</span><span class="o">*</span><span class="nb">_TECHMAP_BITS_CONNMAP_ bit vector containing</span>
<span class="nb">        N words </span><span class="o">(</span><span class="nb">of _TECHMAP_BITS_CONNMAP_ bits each</span><span class="o">)</span><span class="nb"> that assign each single</span>
<span class="nb">        bit driver a unique id. The values </span><span class="m">0</span><span class="o">-</span><span class="m">3</span><span class="nb"> are reserved for </span><span class="m">0</span><span class="nb">, </span><span class="m">1</span><span class="nb">, x, and z.</span>
<span class="nb">        This can be used to detect shorted inputs.</span>

<span class="nb">When a module in the map file has a parameter where the according cell in the</span>
<span class="nb">design has a port, the module from the map file is only used if the port in</span>
<span class="nb">the design is connected to a constant value. The parameter is then set to the</span>
<span class="nb">constant value.</span>

<span class="nb">A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name</span>
<span class="nb">and attributes of the cell that is being replaced.</span>
<span class="nb">A cell with a name of the form `_TECHMAP_REPLACE_.&lt;suffix&gt;` in the map file will</span>
<span class="nb">be named thus but with the `_TECHMAP_REPLACE_&#39; prefix substituted with the name</span>
<span class="nb">of the cell being replaced.</span>
<span class="nb">Similarly, a wire named in the form `_TECHMAP_REPLACE_.&lt;suffix&gt;` will cause a</span>
<span class="nb">new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_&#39;</span>
<span class="nb">prefix also substituted.</span>

<span class="nb">See &#39;help extract&#39; for a pass that does the opposite thing.</span>

<span class="nb">See &#39;help flatten&#39; for a pass that does flatten the design </span><span class="o">(</span><span class="nb">which is</span>
<span class="nb">essentially techmap but using the design itself as map library</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{tee </span><span class="o">--</span><span class="nb"> redirect command output to file}</span>
<span class="nv">\label</span><span class="nb">{cmd:tee}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    tee </span><span class="o">[-</span><span class="nb">q</span><span class="o">]</span><span class="nb"> </span><span class="o">[-</span><span class="nb">o logfile|</span><span class="o">-</span><span class="nb">a logfile</span><span class="o">]</span><span class="nb"> cmd</span>

<span class="nb">Execute the specified command, optionally writing the commands output to the</span>
<span class="nb">specified logfile</span><span class="o">(</span><span class="nb">s</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">q</span>
<span class="nb">        Do not print output to the normal destination </span><span class="o">(</span><span class="nb">console and</span><span class="o">/</span><span class="nb">or log file</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">o logfile</span>
<span class="nb">        Write output to this file, truncate if exists.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">a logfile</span>
<span class="nb">        Write output to this file, append if exists.</span>

<span class="nb">    </span><span class="o">+</span><span class="nb">INT, </span><span class="o">-</span><span class="nb">INT</span>
<span class="nb">        Add</span><span class="o">/</span><span class="nb">subtract INT from the </span><span class="o">-</span><span class="nb">v setting for this command.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{test</span><span class="nv">\_</span><span class="nb">abcloop </span><span class="o">--</span><span class="nb"> automatically test handling of loops in abc command}</span>
<span class="nv">\label</span><span class="nb">{cmd:test_abcloop}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    test_abcloop </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Test handling of logic loops in ABC.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">n {integer}</span>
<span class="nb">        create this number of circuits and test them </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> </span><span class="m">100</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">s {positive_integer}</span>
<span class="nb">        use this value as rng seed value </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> unix time</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{test</span><span class="nv">\_</span><span class="nb">autotb </span><span class="o">--</span><span class="nb"> generate simple test benches}</span>
<span class="nv">\label</span><span class="nb">{cmd:test_autotb}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    test_autotb </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Automatically create primitive Verilog test benches for all modules in the</span>
<span class="nb">design. The generated testbenches toggle the input pins of the module in</span>
<span class="nb">a semi</span><span class="o">-</span><span class="nb">random manner and dumps the resulting output signals.</span>

<span class="nb">This can be used to check the synthesis results for simple circuits by</span>
<span class="nb">comparing the testbench output for the input files and the synthesis results.</span>

<span class="nb">The backend automatically detects clock signals. Additionally a signal can</span>
<span class="nb">be forced to be interpreted as clock signal by setting the attribute</span>
<span class="nb">&#39;gentb_clock&#39; on the signal.</span>

<span class="nb">The attribute &#39;gentb_constant&#39; can be used to force a signal to a constant</span>
<span class="nb">value after initialization. This can e.g. be used to force a reset signal</span>
<span class="nb">low in order to explore more inner states in a state machine.</span>

<span class="nb">The attribute &#39;gentb_skip&#39; can be attached to modules to suppress testbench</span>
<span class="nb">generation.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">n &lt;int&gt;</span>
<span class="nb">        number of iterations the test bench should run </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> </span><span class="m">1000</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">seed &lt;int&gt;</span>
<span class="nb">        seed used for pseudo</span><span class="o">-</span><span class="nb">random number generation </span><span class="o">(</span><span class="nb">default </span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="o">)</span><span class="nb">.</span>
<span class="nb">        a value of </span><span class="m">0</span><span class="nb"> will cause an arbitrary seed to be chosen, based on</span>
<span class="nb">        the current system time.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{test</span><span class="nv">\_</span><span class="nb">cell </span><span class="o">--</span><span class="nb"> automatically test the implementation of a cell type}</span>
<span class="nv">\label</span><span class="nb">{cmd:test_cell}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    test_cell </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> {cell</span><span class="o">-</span><span class="nb">types}</span>

<span class="nb">Tests the internal implementation of the given cell type </span><span class="o">(</span><span class="nb">for example &#39;</span><span class="s">$</span>add&#39;)
by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..

Run with &#39;all&#39; instead of a cell type to run the test on all supported
cell types. Use for example &#39;all /<span class="s">$</span><span class="nb">add&#39; for all cell types except </span><span class="s">$</span>add.

    -n <span class="nb">{</span>integer<span class="nb">}</span>
        create this number of cell instances and test them (default = 100).

    -s <span class="nb">{</span>positive<span class="nb">_</span>integer<span class="nb">}</span>
        use this value as rng seed value (default = unix time).

    -f <span class="nb">{</span>ilang<span class="nb">_</span>file<span class="nb">}</span>
        don&#39;t generate circuits. instead load the specified ilang file.

    -w <span class="nb">{</span>filename<span class="nb">_</span>prefix<span class="nb">}</span>
        don&#39;t test anything. just generate the circuits and write them
        to ilang files with the specified prefix

    -map <span class="nb">{</span>filename<span class="nb">}</span>
        pass this option to techmap.

    -simlib
        use &quot;techmap -D SIMLIB<span class="nb">_</span>NOCHECKS -map +/simlib.v -max<span class="nb">_</span>iter 2 -autoproc&quot;

    -aigmap
        instead of calling &quot;techmap&quot;, call &quot;aigmap&quot;

    -muxdiv
        when creating test benches with dividers, create an additional mux
        to mask out the division-by-zero case

    -script <span class="nb">{</span>script<span class="nb">_</span>file<span class="nb">}</span>
        instead of calling &quot;techmap&quot;, call &quot;script <span class="nb">{</span>script<span class="nb">_</span>file<span class="nb">}</span>&quot;.

    -const
        set some input bits to random constant values

    -nosat
        do not check SAT model or run SAT equivalence checking

    -noeval
        do not check const-eval models

    -edges
        test cell edges db creator against sat-based implementation

    -v
        print additional debug information to the console

    -vlog <span class="nb">{</span>filename<span class="nb">}</span>
        create a Verilog test bench to test simlib and write<span class="nb">_</span>verilog
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>test<span class="k">\_</span>pmgen -- test pass for pmgen<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:test<span class="nb">_</span>pmgen<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    test<span class="nb">_</span>pmgen -reduce<span class="nb">_</span>chain [options] [selection]

Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to <span class="s">$</span><span class="nb">reduce_</span><span class="o">*</span><span class="nb">.</span>


<span class="nb">    test_pmgen </span><span class="o">-</span><span class="nb">reduce_tree </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Demo for recursive pmgen patterns. Map trees of AND</span><span class="o">/</span><span class="nb">OR</span><span class="o">/</span><span class="nb">XOR to </span><span class="s">$</span>reduce<span class="nb">_</span>*.


    test<span class="nb">_</span>pmgen -eqpmux [options] [selection]

Demo for recursive pmgen patterns. Optimize EQ/NE/PMUX circuits.


    test<span class="nb">_</span>pmgen -generate [options] &lt;pattern<span class="nb">_</span>name&gt;

Create modules that match the specified pattern.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>torder -- print cells in topological order<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:torder<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    torder [options] [selection]

This command prints the selected cells in topological order.

    -stop &lt;cell<span class="nb">_</span>type&gt; &lt;cell<span class="nb">_</span>port&gt;
        do not use the specified cell port in topological sorting

    -noautostop
        by default Q outputs of internal FF cells and memory read port outputs
        are not used in topological sorting. this option deactivates that.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>trace -- redirect command output to file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:trace<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    trace cmd

Execute the specified command, logging all changes the command performs on
the design in real time.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>tribuf -- infer tri-state buffers<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:tribuf<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    tribuf [options] [selection]

This pass transforms <span class="s">$</span><span class="nb">mux cells with &#39;z&#39; inputs to tristate buffers.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">merge</span>
<span class="nb">        merge multiple tri</span><span class="o">-</span><span class="nb">state buffers driving the same net</span>
<span class="nb">        into a single buffer.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">logic</span>
<span class="nb">        convert tri</span><span class="o">-</span><span class="nb">state buffers that do not drive output ports</span>
<span class="nb">        to non</span><span class="o">-</span><span class="nb">tristate logic. this option implies </span><span class="o">-</span><span class="nb">merge.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{uniquify </span><span class="o">--</span><span class="nb"> create unique copies of modules}</span>
<span class="nv">\label</span><span class="nb">{cmd:uniquify}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    uniquify </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">By default, a module that is instantiated by several other modules is only</span>
<span class="nb">kept once in the design. This preserves the original modularity of the design</span>
<span class="nb">and reduces the overall size of the design in memory. But it prevents certain</span>
<span class="nb">optimizations and other operations on the design. This pass creates unique</span>
<span class="nb">modules for all selected cells. The created modules are marked with the</span>
<span class="nb">&#39;unique&#39; attribute.</span>

<span class="nb">This commands only operates on modules that by themself have the &#39;unique&#39;</span>
<span class="nb">attribute set </span><span class="o">(</span><span class="nb">the &#39;top&#39; module is unique implicitly</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{verific </span><span class="o">--</span><span class="nb"> load Verilog and VHDL designs using Verific}</span>
<span class="nv">\label</span><span class="nb">{cmd:verific}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    verific {</span><span class="o">-</span><span class="nb">vlog</span><span class="m">95</span><span class="nb">|</span><span class="o">-</span><span class="nb">vlog</span><span class="m">2</span><span class="nb">k|</span><span class="o">-</span><span class="nb">sv</span><span class="m">2005</span><span class="nb">|</span><span class="o">-</span><span class="nb">sv</span><span class="m">2009</span><span class="nb">|</span><span class="o">-</span><span class="nb">sv</span><span class="m">2012</span><span class="nb">|</span><span class="o">-</span><span class="nb">sv} &lt;verilog</span><span class="o">-</span><span class="nb">file&gt;..</span>

<span class="nb">Load the specified Verilog</span><span class="o">/</span><span class="nb">SystemVerilog files into Verific.</span>

<span class="nb">All files specified in one call to this command are one compilation unit.</span>
<span class="nb">Files passed to different calls to this command are treated as belonging to</span>
<span class="nb">different compilation units.</span>

<span class="nb">Additional </span><span class="o">-</span><span class="nb">D&lt;macro&gt;</span><span class="o">[=</span><span class="nb">&lt;value&gt;</span><span class="o">]</span><span class="nb"> options may be added after the option indicating</span>
<span class="nb">the language version </span><span class="o">(</span><span class="nb">and before file names</span><span class="o">)</span><span class="nb"> to set additional verilog defines.</span>
<span class="nb">The macros SYNTHESIS and VERIFIC are defined implicitly.</span>


<span class="nb">    verific </span><span class="o">-</span><span class="nb">formal &lt;verilog</span><span class="o">-</span><span class="nb">file&gt;..</span>

<span class="nb">Like </span><span class="o">-</span><span class="nb">sv, but define FORMAL instead of SYNTHESIS.</span>


<span class="nb">    verific {</span><span class="o">-</span><span class="nb">vhdl</span><span class="m">87</span><span class="nb">|</span><span class="o">-</span><span class="nb">vhdl</span><span class="m">93</span><span class="nb">|</span><span class="o">-</span><span class="nb">vhdl</span><span class="m">2</span><span class="nb">k|</span><span class="o">-</span><span class="nb">vhdl</span><span class="m">2008</span><span class="nb">|</span><span class="o">-</span><span class="nb">vhdl} &lt;vhdl</span><span class="o">-</span><span class="nb">file&gt;..</span>

<span class="nb">Load the specified VHDL files into Verific.</span>


<span class="nb">    verific </span><span class="o">[-</span><span class="nb">work &lt;libname&gt;</span><span class="o">]</span><span class="nb"> {</span><span class="o">-</span><span class="nb">sv|</span><span class="o">-</span><span class="nb">vhdl|...} &lt;hdl</span><span class="o">-</span><span class="nb">file&gt;</span>

<span class="nb">Load the specified Verilog</span><span class="o">/</span><span class="nb">SystemVerilog</span><span class="o">/</span><span class="nb">VHDL file into the specified library.</span>
<span class="o">(</span><span class="nb">default library when </span><span class="o">-</span><span class="nb">work is not present: &quot;work&quot;</span><span class="o">)</span><span class="nb"></span>


<span class="nb">    verific </span><span class="o">[-</span><span class="nb">L &lt;libname&gt;</span><span class="o">]</span><span class="nb"> {</span><span class="o">-</span><span class="nb">sv|</span><span class="o">-</span><span class="nb">vhdl|...} &lt;hdl</span><span class="o">-</span><span class="nb">file&gt;</span>

<span class="nb">Look up external definitions in the specified library.</span>
<span class="o">(-</span><span class="nb">L may be used more than once</span><span class="o">)</span><span class="nb"></span>


<span class="nb">    verific </span><span class="o">-</span><span class="nb">vlog</span><span class="o">-</span><span class="nb">incdir &lt;directory&gt;..</span>

<span class="nb">Add Verilog include directories.</span>


<span class="nb">    verific </span><span class="o">-</span><span class="nb">vlog</span><span class="o">-</span><span class="nb">libdir &lt;directory&gt;..</span>

<span class="nb">Add Verilog library directories. Verific will search in this directories to</span>
<span class="nb">find undefined modules.</span>


<span class="nb">    verific </span><span class="o">-</span><span class="nb">vlog</span><span class="o">-</span><span class="nb">define &lt;macro&gt;</span><span class="o">[=</span><span class="nb">&lt;value&gt;</span><span class="o">]</span><span class="nb">..</span>

<span class="nb">Add Verilog defines.</span>


<span class="nb">    verific </span><span class="o">-</span><span class="nb">vlog</span><span class="o">-</span><span class="nb">undef &lt;macro&gt;..</span>

<span class="nb">Remove Verilog defines previously set with </span><span class="o">-</span><span class="nb">vlog</span><span class="o">-</span><span class="nb">define.</span>


<span class="nb">    verific </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">error &lt;msg_id&gt;..</span>
<span class="nb">    verific </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">warning &lt;msg_id&gt;..</span>
<span class="nb">    verific </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">info &lt;msg_id&gt;..</span>
<span class="nb">    verific </span><span class="o">-</span><span class="nb">set</span><span class="o">-</span><span class="nb">ignore &lt;msg_id&gt;..</span>

<span class="nb">Set message severity. &lt;msg_id&gt; is the string in square brackets when a message</span>
<span class="nb">is printed, such as VERI</span><span class="o">-</span><span class="m">1209</span><span class="nb">.</span>


<span class="nb">    verific </span><span class="o">-</span><span class="nb">import </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> &lt;top</span><span class="o">-</span><span class="nb">module&gt;..</span>

<span class="nb">Elaborate the design for the specified top modules, import to Yosys and</span>
<span class="nb">reset the internal state of Verific.</span>

<span class="nb">Import options:</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">all</span>
<span class="nb">    Elaborate all modules, not just the hierarchy below the given top</span>
<span class="nb">    modules. With this option the list of modules to import is optional.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">gates</span>
<span class="nb">    Create a gate</span><span class="o">-</span><span class="nb">level netlist.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">flatten</span>
<span class="nb">    Flatten the design in Verific before importing.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">extnets</span>
<span class="nb">    Resolve references to external nets by adding module ports as needed.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">autocover</span>
<span class="nb">    Generate automatic cover statements for all asserts</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">fullinit</span>
<span class="nb">    Keep all register initializations, even those for non</span><span class="o">-</span><span class="nb">FF registers.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">chparam name value </span>
<span class="nb">    Elaborate the specified top modules </span><span class="o">(</span><span class="nb">all modules when </span><span class="o">-</span><span class="nb">all given</span><span class="o">)</span><span class="nb"> using</span>
<span class="nb">    this parameter value. Modules on which this parameter does not exist will</span>
<span class="nb">    cause Verific to produce a VERI</span><span class="o">-</span><span class="m">1928</span><span class="nb"> or VHDL</span><span class="o">-</span><span class="m">1676</span><span class="nb"> message. This option</span>
<span class="nb">    can be specified multiple times to override multiple parameters.</span>
<span class="nb">    String values must be passed in double quotes </span><span class="o">(</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">v, </span><span class="o">-</span><span class="nb">vv</span>
<span class="nb">    Verbose log messages. </span><span class="o">(-</span><span class="nb">vv is even more verbose than </span><span class="o">-</span><span class="nb">v.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">The following additional import options are useful for debugging the Verific</span>
<span class="nb">bindings </span><span class="o">(</span><span class="nb">for Yosys and</span><span class="o">/</span><span class="nb">or Verific developers</span><span class="o">)</span><span class="nb">:</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">k</span>
<span class="nb">    Keep going after an unsupported verific primitive is found. The</span>
<span class="nb">    unsupported primitive is added as blockbox module to the design.</span>
<span class="nb">    This will also add all SVA related cells to the design parallel to</span>
<span class="nb">    the checker logic inferred by it.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">V</span>
<span class="nb">    Import Verific netlist as</span><span class="o">-</span><span class="nb">is without translating to Yosys cell types. </span>

<span class="nb">  </span><span class="o">-</span><span class="nb">nosva</span>
<span class="nb">    Ignore SVA properties, do not infer checker logic.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">L &lt;int&gt;</span>
<span class="nb">    Maximum number of ctrl bits for SVA checker FSMs </span><span class="o">(</span><span class="nb">default</span><span class="o">=</span><span class="m">16</span><span class="o">)</span><span class="nb">.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">n</span>
<span class="nb">    Keep all Verific names on instances and nets. By default only</span>
<span class="nb">    user</span><span class="o">-</span><span class="nb">declared names are preserved.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">d &lt;dump_file&gt;</span>
<span class="nb">    Dump the Verific netlist as a verilog file.</span>


<span class="nb">Use YosysHQ Tabby CAD Suite if you need Yosys</span><span class="o">+</span><span class="nb">Verific.</span>
<span class="nb">https:</span><span class="o">//</span><span class="nb">www.yosyshq.com</span><span class="o">/</span><span class="nv">\n</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">;</span>

<span class="nb">Contact office@yosyshq.com for free evaluation</span>
<span class="nb">binaries of YosysHQ Tabby CAD Suite.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{verilog</span><span class="nv">\_</span><span class="nb">defaults </span><span class="o">--</span><span class="nb"> set default options for read</span><span class="nv">\_</span><span class="nb">verilog}</span>
<span class="nv">\label</span><span class="nb">{cmd:verilog_defaults}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    verilog_defaults </span><span class="o">-</span><span class="nb">add </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Add the specified options to the list of default options to read_verilog.</span>


<span class="nb">    verilog_defaults </span><span class="o">-</span><span class="nb">clear</span>

<span class="nb">Clear the list of Verilog default options.</span>


<span class="nb">    verilog_defaults </span><span class="o">-</span><span class="nb">push</span>
<span class="nb">    verilog_defaults </span><span class="o">-</span><span class="nb">pop</span>

<span class="nb">Push or pop the list of default options to a stack. Note that </span><span class="o">-</span><span class="nb">push does</span>
<span class="nb">not imply </span><span class="o">-</span><span class="nb">clear.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{verilog</span><span class="nv">\_</span><span class="nb">defines </span><span class="o">--</span><span class="nb"> define and undefine verilog defines}</span>
<span class="nv">\label</span><span class="nb">{cmd:verilog_defines}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    verilog_defines </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Define and undefine verilog preprocessor macros.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">Dname</span><span class="o">[=</span><span class="nb">definition</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        define the preprocessor symbol &#39;name&#39; and set its optional value</span>
<span class="nb">        &#39;definition&#39;</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">Uname</span><span class="o">[=</span><span class="nb">definition</span><span class="o">]</span><span class="nb"></span>
<span class="nb">        undefine the preprocessor symbol &#39;name&#39;</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">reset</span>
<span class="nb">        clear list of defined preprocessor symbols</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">list</span>
<span class="nb">        list currently defined preprocessor symbols</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{wbflip </span><span class="o">--</span><span class="nb"> flip the whitebox attribute}</span>
<span class="nv">\label</span><span class="nb">{cmd:wbflip}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    wbflip </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Flip the whitebox attribute on selected cells. I.e. if it&#39;s set, unset it, and</span>
<span class="nb">vice</span><span class="o">-</span><span class="nb">versa. Blackbox cells are not effected by this command.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{wreduce </span><span class="o">--</span><span class="nb"> reduce the word size of operations if possible}</span>
<span class="nv">\label</span><span class="nb">{cmd:wreduce}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    wreduce </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This command reduces the word size of operations. For example it will replace</span>
<span class="nb">the </span><span class="m">32</span><span class="nb"> bit adders in the following code with adders of more appropriate widths:</span>

<span class="nb">    module test</span><span class="o">(</span><span class="nb">input </span><span class="o">[</span><span class="m">3</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> a, b, c, output </span><span class="o">[</span><span class="m">7</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> y</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">        assign y </span><span class="o">=</span><span class="nb"> a </span><span class="o">+</span><span class="nb"> b </span><span class="o">+</span><span class="nb"> c </span><span class="o">+</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">    endmodule</span>

<span class="nb">Options:</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">memx</span>
<span class="nb">        Do not change the width of memory address ports. Use this options in</span>
<span class="nb">        flows that use the &#39;memory_memx&#39; pass.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">keepdc</span>
<span class="nb">        Do not optimize explicit don&#39;t</span><span class="o">-</span><span class="nb">care values.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">aiger </span><span class="o">--</span><span class="nb"> write design to AIGER file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_aiger}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_aiger </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write the current design to an AIGER file. The design must be flattened and</span>
<span class="nb">must not contain any cell types except </span><span class="s">$</span><span class="nb">_</span>AND<span class="nb">_</span>, <span class="s">$</span><span class="nb">_NOT_, simple FF types,</span>
<span class="s">$</span>assert and <span class="s">$</span><span class="nb">assume cells, and </span><span class="s">$</span>initstate cells.

<span class="s">$</span><span class="nb">assert and </span><span class="s">$</span>assume cells are converted to AIGER bad state properties and
invariant constraints.

    -ascii
        write ASCII version of AIGER format

    -zinit
        convert FFs to zero-initialized FFs, adding additional inputs for
        uninitialized FFs.

    -miter
        design outputs are AIGER bad state properties

    -symbols
        include a symbol table in the generated AIGER file

    -map &lt;filename&gt;
        write an extra file with port and latch symbols

    -vmap &lt;filename&gt;
        like -map, but more verbose

    -I, -O, -B, -L
        If the design contains no input/output/assert/flip-flop then create one
        dummy input/output/bad<span class="nb">_</span>state-pin or latch to make the tools reading the
        AIGER file happy.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>write<span class="k">\_</span>blif -- write design to BLIF file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:write<span class="nb">_</span>blif<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    write<span class="nb">_</span>blif [options] [filename]

Write the current design to an BLIF file.

    -top top<span class="nb">_</span>module
        set the specified module as design top module

    -buf &lt;cell-type&gt; &lt;in-port&gt; &lt;out-port&gt;
        use cells of type &lt;cell-type&gt; with the specified port names for buffers

    -unbuf &lt;cell-type&gt; &lt;in-port&gt; &lt;out-port&gt;
        replace buffer cells with the specified name and port names with
        a .names statement that models a buffer

    -true &lt;cell-type&gt; &lt;out-port&gt;
    -false &lt;cell-type&gt; &lt;out-port&gt;
    -undef &lt;cell-type&gt; &lt;out-port&gt;
        use the specified cell types to drive nets that are constant 1, 0, or
        undefined. when &#39;-&#39; is used as &lt;cell-type&gt;, then &lt;out-port&gt; specifies
        the wire name to be used for the constant signal and no cell driving
        that wire is generated. when &#39;+&#39; is used as &lt;cell-type&gt;, then &lt;out-port&gt;
        specifies the wire name to be used for the constant signal and a .names
        statement is generated to drive the wire.

    -noalias
        if a net name is aliasing another net name, then by default a net
        without fanout is created that is driven by the other net. This option
        suppresses the generation of this nets without fanout.

The following options can be useful when the generated file is not going to be
read by a BLIF parser but a custom tool. It is recommended to not name the output
file *.blif when any of this options is used.

    -icells
        do not translate Yosys&#39;s internal gates to generic BLIF logic
        functions. Instead create .subckt or .gate lines for all cells.

    -gates
        print .gate instead of .subckt lines for all cells that are not
        instantiations of other modules from this design.

    -conn
        do not generate buffers for connected wires. instead use the
        non-standard .conn statement.

    -attr
        use the non-standard .attr statement to write cell attributes

    -param
        use the non-standard .param statement to write cell parameters

    -cname
        use the non-standard .cname statement to write cell names

    -iname, -iattr
        enable -cname and -attr functionality for .names statements
        (the .cname and .attr statements will be included in the BLIF
        output after the truth table for the .names statement)

    -blackbox
        write blackbox cells with .blackbox statement.

    -impltf
        do not write definitions for the <span class="s">$</span><span class="nb">true, </span><span class="s">$</span>false and <span class="s">$</span><span class="nb">undef wires.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">btor </span><span class="o">--</span><span class="nb"> write design to BTOR file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_btor}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_btor </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write a BTOR description of the current design.</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">v</span>
<span class="nb">    Add comments and indentation to BTOR output file</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">s</span>
<span class="nb">    Output only a single bad property for all asserts</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">c</span>
<span class="nb">    Output cover properties using &#39;bad&#39; statements instead of asserts</span>

<span class="nb">  </span><span class="o">-</span><span class="nb">i &lt;filename&gt;</span>
<span class="nb">    Create additional info file with auxiliary information</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">cxxrtl </span><span class="o">--</span><span class="nb"> convert design to C</span><span class="o">++</span><span class="nb"> RTL simulation}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_cxxrtl}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_cxxrtl </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write C</span><span class="o">++</span><span class="nb"> code for simulating the design. The generated code requires a driver;</span>
<span class="nb">the following simple driver is provided as an example:</span>

<span class="nb">    #include &quot;top.cc&quot;</span>

<span class="nb">    int main</span><span class="o">()</span><span class="nb"> {</span>
<span class="nb">      cxxrtl_design::p_top top;</span>
<span class="nb">      while </span><span class="o">(</span><span class="m">1</span><span class="o">)</span><span class="nb"> {</span>
<span class="nb">        top.p_clk.next </span><span class="o">=</span><span class="nb"> value&lt;</span><span class="m">1</span><span class="nb">&gt; {</span><span class="m">1</span><span class="nb">u};</span>
<span class="nb">        top.step</span><span class="o">()</span><span class="nb">;</span>
<span class="nb">        top.p_clk.next </span><span class="o">=</span><span class="nb"> value&lt;</span><span class="m">1</span><span class="nb">&gt; {</span><span class="m">0</span><span class="nb">u};</span>
<span class="nb">        top.step</span><span class="o">()</span><span class="nb">;</span>
<span class="nb">      }</span>
<span class="nb">    }</span>

<span class="nb">The following options are supported by this backend:</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">O &lt;level&gt;</span>
<span class="nb">        set the optimization level. the default is </span><span class="o">-</span><span class="nb">O</span><span class="m">5</span><span class="nb">. higher optimization</span>
<span class="nb">        levels dramatically decrease compile and run time, and highest level</span>
<span class="nb">        possible for a design should be used.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">O</span><span class="m">0</span><span class="nb"></span>
<span class="nb">        no optimization.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">O</span><span class="m">1</span><span class="nb"></span>
<span class="nb">        elide internal wires if possible.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">O</span><span class="m">2</span><span class="nb"></span>
<span class="nb">        like </span><span class="o">-</span><span class="nb">O</span><span class="m">1</span><span class="nb">, and localize internal wires if possible.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">O</span><span class="m">3</span><span class="nb"></span>
<span class="nb">        like </span><span class="o">-</span><span class="nb">O</span><span class="m">2</span><span class="nb">, and elide public wires not marked </span><span class="o">(*</span><span class="nb">keep</span><span class="o">*)</span><span class="nb"> if possible.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">O</span><span class="m">4</span><span class="nb"></span>
<span class="nb">        like </span><span class="o">-</span><span class="nb">O</span><span class="m">3</span><span class="nb">, and localize public wires not marked </span><span class="o">(*</span><span class="nb">keep</span><span class="o">*)</span><span class="nb"> if possible.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">O</span><span class="m">5</span><span class="nb"></span>
<span class="nb">        like </span><span class="o">-</span><span class="nb">O</span><span class="m">4</span><span class="nb">, and run `splitnets </span><span class="o">-</span><span class="nb">driver; opt_clean </span><span class="o">-</span><span class="nb">purge` first.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">edif </span><span class="o">--</span><span class="nb"> write design to EDIF netlist file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_edif}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_edif </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write the current design to an EDIF netlist file.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top top_module</span>
<span class="nb">        set the specified module as design top module</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nogndvcc</span>
<span class="nb">        do not create &quot;GND&quot; and &quot;VCC&quot; cells. </span><span class="o">(</span><span class="nb">this will produce an error</span>
<span class="nb">        if the design contains constant nets. use &quot;hilomap&quot; to map to custom</span>
<span class="nb">        constant drivers first</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">gndvccy</span>
<span class="nb">        create &quot;GND&quot; and &quot;VCC&quot; cells with &quot;Y&quot; outputs. </span><span class="o">(</span><span class="nb">the default is &quot;G&quot;</span>
<span class="nb">        for &quot;GND&quot; and &quot;P&quot; for &quot;VCC&quot;.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">attrprop</span>
<span class="nb">        create EDIF properties for cell attributes</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">pvector {par|bra|ang}</span>
<span class="nb">        sets the delimiting character for module port rename clauses to</span>
<span class="nb">        parentheses, square brackets, or angle brackets.</span>

<span class="nb">Unfortunately there are different &quot;flavors&quot; of the EDIF file format. This</span>
<span class="nb">command generates EDIF files for the Xilinx place&amp;route tools. It might be</span>
<span class="nb">necessary to make small modifications to this command when a different tool</span>
<span class="nb">is targeted.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">file </span><span class="o">--</span><span class="nb"> write a text to a file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_file}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_file </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> output_file </span><span class="o">[</span><span class="nb">input_file</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write the text from the input file to the output file.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">a</span>
<span class="nb">        Append to output file </span><span class="o">(</span><span class="nb">instead of overwriting</span><span class="o">)</span><span class="nb"></span>


<span class="nb">Inside a script the input file can also can a here</span><span class="o">-</span><span class="nb">document:</span>

<span class="nb">    write_file hello.txt &lt;&lt;EOT</span>
<span class="nb">    Hello World</span><span class="o">!</span><span class="nb"></span>
<span class="nb">    EOT</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">firrtl </span><span class="o">--</span><span class="nb"> write design to a FIRRTL file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_firrtl}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_firrtl </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write a FIRRTL netlist of the current design.</span>
<span class="nb">The following commands are executed by this command:</span>
<span class="nb">        pmuxtree</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">ilang </span><span class="o">--</span><span class="nb"> write design to ilang file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_ilang}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_ilang </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write the current design to an &#39;ilang&#39; file. </span><span class="o">(</span><span class="nb">ilang is a text representation</span>
<span class="nb">of a design in yosys&#39;s internal format.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">selected</span>
<span class="nb">        only write selected parts of the design.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">intersynth </span><span class="o">--</span><span class="nb"> write design to InterSynth netlist file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_intersynth}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_intersynth </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write the current design to an &#39;intersynth&#39; netlist file. InterSynth is</span>
<span class="nb">a tool for Coarse</span><span class="o">-</span><span class="nb">Grain Example</span><span class="o">-</span><span class="nb">Driven Interconnect Synthesis.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">notypes</span>
<span class="nb">        do not generate celltypes and conntypes commands. i.e. just output</span>
<span class="nb">        the netlists. this is used for postsilicon synthesis.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">lib &lt;verilog_or_ilang_file&gt;</span>
<span class="nb">        Use the specified library file for determining whether cell ports are</span>
<span class="nb">        inputs or outputs. This option can be used multiple times to specify</span>
<span class="nb">        more than one library.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">selected</span>
<span class="nb">        only write selected modules. modules must be selected entirely or</span>
<span class="nb">        not at all.</span>

<span class="nb">http:</span><span class="o">//</span><span class="nb">www.clifford.at</span><span class="o">/</span><span class="nb">intersynth</span><span class="o">/</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">json </span><span class="o">--</span><span class="nb"> write design to a JSON file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_json}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_json </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write a JSON netlist of the current design.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">aig</span>
<span class="nb">        include AIG models for the different gate types</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">compat</span><span class="o">-</span><span class="nb">int</span>
<span class="nb">        emit </span><span class="m">32</span><span class="o">-</span><span class="nb">bit or smaller fully</span><span class="o">-</span><span class="nb">defined parameter values directly</span>
<span class="nb">        as JSON numbers </span><span class="o">(</span><span class="nb">for compatibility with old parsers</span><span class="o">)</span><span class="nb"></span>


<span class="nb">The general syntax of the JSON output created by this command is as follows:</span>

<span class="nb">    {</span>
<span class="nb">      &quot;modules&quot;: {</span>
<span class="nb">        &lt;module_name&gt;: {</span>
<span class="nb">          &quot;ports&quot;: {</span>
<span class="nb">            &lt;port_name&gt;: &lt;port_details&gt;,</span>
<span class="nb">            ...</span>
<span class="nb">          },</span>
<span class="nb">          &quot;cells&quot;: {</span>
<span class="nb">            &lt;cell_name&gt;: &lt;cell_details&gt;,</span>
<span class="nb">            ...</span>
<span class="nb">          },</span>
<span class="nb">          &quot;netnames&quot;: {</span>
<span class="nb">            &lt;net_name&gt;: &lt;net_details&gt;,</span>
<span class="nb">            ...</span>
<span class="nb">          }</span>
<span class="nb">        }</span>
<span class="nb">      },</span>
<span class="nb">      &quot;models&quot;: {</span>
<span class="nb">        ...</span>
<span class="nb">      },</span>
<span class="nb">    }</span>

<span class="nb">Where &lt;port_details&gt; is:</span>

<span class="nb">    {</span>
<span class="nb">      &quot;direction&quot;: &lt;&quot;input&quot; | &quot;output&quot; | &quot;inout&quot;&gt;,</span>
<span class="nb">      &quot;bits&quot;: &lt;bit_vector&gt;</span>
<span class="nb">    }</span>

<span class="nb">And &lt;cell_details&gt; is:</span>

<span class="nb">    {</span>
<span class="nb">      &quot;hide_name&quot;: &lt;</span><span class="m">1</span><span class="nb"> | </span><span class="m">0</span><span class="nb">&gt;,</span>
<span class="nb">      &quot;type&quot;: &lt;cell_type&gt;,</span>
<span class="nb">      &quot;parameters&quot;: {</span>
<span class="nb">        &lt;parameter_name&gt;: &lt;parameter_value&gt;,</span>
<span class="nb">        ...</span>
<span class="nb">      },</span>
<span class="nb">      &quot;attributes&quot;: {</span>
<span class="nb">        &lt;attribute_name&gt;: &lt;attribute_value&gt;,</span>
<span class="nb">        ...</span>
<span class="nb">      },</span>
<span class="nb">      &quot;port_directions&quot;: {</span>
<span class="nb">        &lt;port_name&gt;: &lt;&quot;input&quot; | &quot;output&quot; | &quot;inout&quot;&gt;,</span>
<span class="nb">        ...</span>
<span class="nb">      },</span>
<span class="nb">      &quot;connections&quot;: {</span>
<span class="nb">        &lt;port_name&gt;: &lt;bit_vector&gt;,</span>
<span class="nb">        ...</span>
<span class="nb">      },</span>
<span class="nb">    }</span>

<span class="nb">And &lt;net_details&gt; is:</span>

<span class="nb">    {</span>
<span class="nb">      &quot;hide_name&quot;: &lt;</span><span class="m">1</span><span class="nb"> | </span><span class="m">0</span><span class="nb">&gt;,</span>
<span class="nb">      &quot;bits&quot;: &lt;bit_vector&gt;</span>
<span class="nb">    }</span>

<span class="nb">The &quot;hide_name&quot; fields are set to </span><span class="m">1</span><span class="nb"> when the name of this cell or net is</span>
<span class="nb">automatically created and is likely not of interest for a regular user.</span>

<span class="nb">The &quot;port_directions&quot; section is only included for cells for which the</span>
<span class="nb">interface is known.</span>

<span class="nb">Module and cell ports and nets can be single bit wide or vectors of multiple</span>
<span class="nb">bits. Each individual signal bit is assigned a unique integer. The &lt;bit_vector&gt;</span>
<span class="nb">values referenced above are vectors of this integers. Signal bits that are</span>
<span class="nb">connected to a constant driver are denoted as string &quot;</span><span class="m">0</span><span class="nb">&quot;, &quot;</span><span class="m">1</span><span class="nb">&quot;, &quot;x&quot;, or</span>
<span class="nb">&quot;z&quot; instead of a number.</span>

<span class="nb">Bit vectors </span><span class="o">(</span><span class="nb">including integers</span><span class="o">)</span><span class="nb"> are written as string holding the binaryrepresentation of the value. Strings are written as strings, with an appendedblank in cases of strings of the form </span><span class="o">/[</span><span class="m">01</span><span class="nb">xz</span><span class="o">]*</span><span class="nb"> </span><span class="o">*/</span><span class="nb">.</span>

<span class="nb">For example the following Verilog code:</span>

<span class="nb">    module test</span><span class="o">(</span><span class="nb">input x, y</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">      </span><span class="o">(*</span><span class="nb"> keep </span><span class="o">*)</span><span class="nb"> foo #</span><span class="o">(</span><span class="nb">.P</span><span class="o">(</span><span class="m">42</span><span class="o">)</span><span class="nb">, .Q</span><span class="o">(</span><span class="m">1337</span><span class="o">))</span><span class="nb"></span>
<span class="nb">          foo_inst </span><span class="o">(</span><span class="nb">.A</span><span class="o">(</span><span class="nb">{x, y}</span><span class="o">)</span><span class="nb">, .B</span><span class="o">(</span><span class="nb">{y, x}</span><span class="o">)</span><span class="nb">, .C</span><span class="o">(</span><span class="nb">{</span><span class="m">4</span><span class="nb">&#39;d</span><span class="m">10</span><span class="nb">, {</span><span class="m">4</span><span class="nb">{x}}}</span><span class="o">))</span><span class="nb">;</span>
<span class="nb">    endmodule</span>

<span class="nb">Translates to the following JSON output:</span>

<span class="nb">    {</span>
<span class="nb">      &quot;modules&quot;: {</span>
<span class="nb">        &quot;test&quot;: {</span>
<span class="nb">          &quot;ports&quot;: {</span>
<span class="nb">            &quot;x&quot;: {</span>
<span class="nb">              &quot;direction&quot;: &quot;input&quot;,</span>
<span class="nb">              &quot;bits&quot;: </span><span class="o">[</span><span class="nb"> </span><span class="m">2</span><span class="nb"> </span><span class="o">]</span><span class="nb"></span>
<span class="nb">            },</span>
<span class="nb">            &quot;y&quot;: {</span>
<span class="nb">              &quot;direction&quot;: &quot;input&quot;,</span>
<span class="nb">              &quot;bits&quot;: </span><span class="o">[</span><span class="nb"> </span><span class="m">3</span><span class="nb"> </span><span class="o">]</span><span class="nb"></span>
<span class="nb">            }</span>
<span class="nb">          },</span>
<span class="nb">          &quot;cells&quot;: {</span>
<span class="nb">            &quot;foo_inst&quot;: {</span>
<span class="nb">              &quot;hide_name&quot;: </span><span class="m">0</span><span class="nb">,</span>
<span class="nb">              &quot;type&quot;: &quot;foo&quot;,</span>
<span class="nb">              &quot;parameters&quot;: {</span>
<span class="nb">                &quot;Q&quot;: </span><span class="m">1337</span><span class="nb">,</span>
<span class="nb">                &quot;P&quot;: </span><span class="m">42</span><span class="nb"></span>
<span class="nb">              },</span>
<span class="nb">              &quot;attributes&quot;: {</span>
<span class="nb">                &quot;keep&quot;: </span><span class="m">1</span><span class="nb">,</span>
<span class="nb">                &quot;src&quot;: &quot;test.v:</span><span class="m">2</span><span class="nb">&quot;</span>
<span class="nb">              },</span>
<span class="nb">              &quot;connections&quot;: {</span>
<span class="nb">                &quot;C&quot;: </span><span class="o">[</span><span class="nb"> </span><span class="m">2</span><span class="nb">, </span><span class="m">2</span><span class="nb">, </span><span class="m">2</span><span class="nb">, </span><span class="m">2</span><span class="nb">, &quot;</span><span class="m">0</span><span class="nb">&quot;, &quot;</span><span class="m">1</span><span class="nb">&quot;, &quot;</span><span class="m">0</span><span class="nb">&quot;, &quot;</span><span class="m">1</span><span class="nb">&quot; </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">                &quot;B&quot;: </span><span class="o">[</span><span class="nb"> </span><span class="m">2</span><span class="nb">, </span><span class="m">3</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">                &quot;A&quot;: </span><span class="o">[</span><span class="nb"> </span><span class="m">3</span><span class="nb">, </span><span class="m">2</span><span class="nb"> </span><span class="o">]</span><span class="nb"></span>
<span class="nb">              }</span>
<span class="nb">            }</span>
<span class="nb">          },</span>
<span class="nb">          &quot;netnames&quot;: {</span>
<span class="nb">            &quot;y&quot;: {</span>
<span class="nb">              &quot;hide_name&quot;: </span><span class="m">0</span><span class="nb">,</span>
<span class="nb">              &quot;bits&quot;: </span><span class="o">[</span><span class="nb"> </span><span class="m">3</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">              &quot;attributes&quot;: {</span>
<span class="nb">                &quot;src&quot;: &quot;test.v:</span><span class="m">1</span><span class="nb">&quot;</span>
<span class="nb">              }</span>
<span class="nb">            },</span>
<span class="nb">            &quot;x&quot;: {</span>
<span class="nb">              &quot;hide_name&quot;: </span><span class="m">0</span><span class="nb">,</span>
<span class="nb">              &quot;bits&quot;: </span><span class="o">[</span><span class="nb"> </span><span class="m">2</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">              &quot;attributes&quot;: {</span>
<span class="nb">                &quot;src&quot;: &quot;test.v:</span><span class="m">1</span><span class="nb">&quot;</span>
<span class="nb">              }</span>
<span class="nb">            }</span>
<span class="nb">          }</span>
<span class="nb">        }</span>
<span class="nb">      }</span>
<span class="nb">    }</span>

<span class="nb">The models are given as And</span><span class="o">-</span><span class="nb">Inverter</span><span class="o">-</span><span class="nb">Graphs </span><span class="o">(</span><span class="nb">AIGs</span><span class="o">)</span><span class="nb"> in the following form:</span>

<span class="nb">    &quot;models&quot;: {</span>
<span class="nb">      &lt;model_name&gt;: </span><span class="o">[</span><span class="nb"></span>
<span class="nb">        </span><span class="o">/*</span><span class="nb">   </span><span class="m">0</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &lt;node</span><span class="o">-</span><span class="nb">spec&gt; </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">        </span><span class="o">/*</span><span class="nb">   </span><span class="m">1</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &lt;node</span><span class="o">-</span><span class="nb">spec&gt; </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">        </span><span class="o">/*</span><span class="nb">   </span><span class="m">2</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &lt;node</span><span class="o">-</span><span class="nb">spec&gt; </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">        ...</span>
<span class="nb">      </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">      ...</span>
<span class="nb">    },</span>

<span class="nb">The following node</span><span class="o">-</span><span class="nb">types may be used:</span>

<span class="nb">    </span><span class="o">[</span><span class="nb"> &quot;port&quot;, &lt;portname&gt;, &lt;bitindex&gt;, &lt;out</span><span class="o">-</span><span class="nb">list&gt; </span><span class="o">]</span><span class="nb"></span>
<span class="nb">      </span><span class="o">-</span><span class="nb"> the value of the specified input port bit</span>

<span class="nb">    </span><span class="o">[</span><span class="nb"> &quot;nport&quot;, &lt;portname&gt;, &lt;bitindex&gt;, &lt;out</span><span class="o">-</span><span class="nb">list&gt; </span><span class="o">]</span><span class="nb"></span>
<span class="nb">      </span><span class="o">-</span><span class="nb"> the inverted value of the specified input port bit</span>

<span class="nb">    </span><span class="o">[</span><span class="nb"> &quot;and&quot;, &lt;node</span><span class="o">-</span><span class="nb">index&gt;, &lt;node</span><span class="o">-</span><span class="nb">index&gt;, &lt;out</span><span class="o">-</span><span class="nb">list&gt; </span><span class="o">]</span><span class="nb"></span>
<span class="nb">      </span><span class="o">-</span><span class="nb"> the ANDed value of the specified nodes</span>

<span class="nb">    </span><span class="o">[</span><span class="nb"> &quot;nand&quot;, &lt;node</span><span class="o">-</span><span class="nb">index&gt;, &lt;node</span><span class="o">-</span><span class="nb">index&gt;, &lt;out</span><span class="o">-</span><span class="nb">list&gt; </span><span class="o">]</span><span class="nb"></span>
<span class="nb">      </span><span class="o">-</span><span class="nb"> the inverted ANDed value of the specified nodes</span>

<span class="nb">    </span><span class="o">[</span><span class="nb"> &quot;true&quot;, &lt;out</span><span class="o">-</span><span class="nb">list&gt; </span><span class="o">]</span><span class="nb"></span>
<span class="nb">      </span><span class="o">-</span><span class="nb"> the constant value </span><span class="m">1</span><span class="nb"></span>

<span class="nb">    </span><span class="o">[</span><span class="nb"> &quot;false&quot;, &lt;out</span><span class="o">-</span><span class="nb">list&gt; </span><span class="o">]</span><span class="nb"></span>
<span class="nb">      </span><span class="o">-</span><span class="nb"> the constant value </span><span class="m">0</span><span class="nb"></span>

<span class="nb">All nodes appear in topological order. I.e. only nodes with smaller indices</span>
<span class="nb">are referenced by &quot;and&quot; and &quot;nand&quot; nodes.</span>

<span class="nb">The optional &lt;out</span><span class="o">-</span><span class="nb">list&gt; at the end of a node specification is a list of</span>
<span class="nb">output portname and bitindex pairs, specifying the outputs driven by this node.</span>

<span class="nb">For example, the following is the model for a </span><span class="m">3</span><span class="o">-</span><span class="nb">input </span><span class="m">3</span><span class="o">-</span><span class="nb">output </span><span class="s">$</span>reduce<span class="nb">_</span>and cell
inferred by the following code:

    module test(input [2:0] in, output [2:0] out);
      assign in = <span class="nb">&amp;</span>out;
    endmodule

    &quot;<span class="s">$</span><span class="nb">reduce_and:</span><span class="m">3</span><span class="nb">U:</span><span class="m">3</span><span class="nb">&quot;: </span><span class="o">[</span><span class="nb"></span>
<span class="nb">      </span><span class="o">/*</span><span class="nb">   </span><span class="m">0</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &quot;port&quot;, &quot;A&quot;, </span><span class="m">0</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">      </span><span class="o">/*</span><span class="nb">   </span><span class="m">1</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &quot;port&quot;, &quot;A&quot;, </span><span class="m">1</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">      </span><span class="o">/*</span><span class="nb">   </span><span class="m">2</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &quot;and&quot;, </span><span class="m">0</span><span class="nb">, </span><span class="m">1</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">      </span><span class="o">/*</span><span class="nb">   </span><span class="m">3</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &quot;port&quot;, &quot;A&quot;, </span><span class="m">2</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">      </span><span class="o">/*</span><span class="nb">   </span><span class="m">4</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &quot;and&quot;, </span><span class="m">2</span><span class="nb">, </span><span class="m">3</span><span class="nb">, &quot;Y&quot;, </span><span class="m">0</span><span class="nb"> </span><span class="o">]</span><span class="nb">,</span>
<span class="nb">      </span><span class="o">/*</span><span class="nb">   </span><span class="m">5</span><span class="nb"> </span><span class="o">*/</span><span class="nb"> </span><span class="o">[</span><span class="nb"> &quot;false&quot;, &quot;Y&quot;, </span><span class="m">1</span><span class="nb">, &quot;Y&quot;, </span><span class="m">2</span><span class="nb"> </span><span class="o">]</span><span class="nb"></span>
<span class="nb">    </span><span class="o">]</span><span class="nb"></span>

<span class="nb">Future version of Yosys might add support for additional fields in the JSON</span>
<span class="nb">format. A program processing this format must ignore all unknown fields.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">simplec </span><span class="o">--</span><span class="nb"> convert design to simple C code}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_simplec}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_simplec </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write simple C code for simulating the design. The C code written can be used to</span>
<span class="nb">simulate the design in a C environment, but the purpose of this command is to</span>
<span class="nb">generate code that works well with C</span><span class="o">-</span><span class="nb">based formal verification.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">verbose</span>
<span class="nb">        this will print the recursive walk used to export the modules.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">i</span><span class="m">8</span><span class="nb">, </span><span class="o">-</span><span class="nb">i</span><span class="m">16</span><span class="nb">, </span><span class="o">-</span><span class="nb">i</span><span class="m">32</span><span class="nb">, </span><span class="o">-</span><span class="nb">i</span><span class="m">64</span><span class="nb"></span>
<span class="nb">        set the maximum integer bit width to use in the generated code.</span>

<span class="nb">THIS COMMAND IS UNDER CONSTRUCTION</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">smt</span><span class="m">2</span><span class="nb"> </span><span class="o">--</span><span class="nb"> write design to SMT</span><span class="o">-</span><span class="nb">LIBv</span><span class="m">2</span><span class="nb"> file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_smt</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_smt</span><span class="m">2</span><span class="nb"> </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write a SMT</span><span class="o">-</span><span class="nb">LIBv</span><span class="m">2</span><span class="nb"> </span><span class="o">[</span><span class="m">1</span><span class="o">]</span><span class="nb"> description of the current design. For a module with name</span>
<span class="nb">&#39;&lt;mod&gt;&#39; this will declare the sort &#39;&lt;mod&gt;_s&#39; </span><span class="o">(</span><span class="nb">state of the module</span><span class="o">)</span><span class="nb"> and will</span>
<span class="nb">define and declare functions operating on that state.</span>

<span class="nb">The following SMT</span><span class="m">2</span><span class="nb"> functions are generated for a module with name &#39;&lt;mod&gt;&#39;.</span>
<span class="nb">Some declarations</span><span class="o">/</span><span class="nb">definitions are printed with a special comment. A prover</span>
<span class="nb">using the SMT</span><span class="m">2</span><span class="nb"> files can use those comments to collect all relevant metadata</span>
<span class="nb">about the design.</span>

<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">module &lt;mod&gt;</span>
<span class="nb">    </span><span class="o">(</span><span class="nb">declare</span><span class="o">-</span><span class="nb">sort |&lt;mod&gt;_s| </span><span class="m">0</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        The sort representing a state of module &lt;mod&gt;.</span>

<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_h| </span><span class="o">((</span><span class="nb">state |&lt;mod&gt;_s|</span><span class="o">))</span><span class="nb"> Bool </span><span class="o">(</span><span class="nb">...</span><span class="o">))</span><span class="nb"></span>
<span class="nb">        This function must be asserted for each state to establish the</span>
<span class="nb">        design hierarchy.</span>

<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">input &lt;wirename&gt; &lt;width&gt;</span>
<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">output &lt;wirename&gt; &lt;width&gt;</span>
<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">register &lt;wirename&gt; &lt;width&gt;</span>
<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">wire &lt;wirename&gt; &lt;width&gt;</span>
<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_n &lt;wirename&gt;| </span><span class="o">(</span><span class="nb">|&lt;mod&gt;_s|</span><span class="o">)</span><span class="nb"> </span><span class="o">(</span><span class="nb">_ BitVec &lt;width&gt;</span><span class="o">))</span><span class="nb"></span>
<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_n &lt;wirename&gt;| </span><span class="o">(</span><span class="nb">|&lt;mod&gt;_s|</span><span class="o">)</span><span class="nb"> Bool</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        For each port, register, and wire with the &#39;keep&#39; attribute set an</span>
<span class="nb">        accessor function is generated. Single</span><span class="o">-</span><span class="nb">bit wires are returned as Bool,</span>
<span class="nb">        multi</span><span class="o">-</span><span class="nb">bit wires as BitVec.</span>

<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">cell &lt;submod&gt; &lt;instancename&gt;</span>
<span class="nb">    </span><span class="o">(</span><span class="nb">declare</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_h &lt;instancename&gt;| </span><span class="o">(</span><span class="nb">|&lt;mod&gt;_s|</span><span class="o">)</span><span class="nb"> |&lt;submod&gt;_s|</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        There is a function like that for each hierarchical instance. It</span>
<span class="nb">        returns the sort that represents the state of the sub</span><span class="o">-</span><span class="nb">module that</span>
<span class="nb">        implements the instance.</span>

<span class="nb">    </span><span class="o">(</span><span class="nb">declare</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_is| </span><span class="o">(</span><span class="nb">|&lt;mod&gt;_s|</span><span class="o">)</span><span class="nb"> Bool</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        This function must be asserted &#39;true&#39; for initial states, and &#39;false&#39;</span>
<span class="nb">        otherwise.</span>

<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_i| </span><span class="o">((</span><span class="nb">state |&lt;mod&gt;_s|</span><span class="o">))</span><span class="nb"> Bool </span><span class="o">(</span><span class="nb">...</span><span class="o">))</span><span class="nb"></span>
<span class="nb">        This function must be asserted &#39;true&#39; for initial states. For</span>
<span class="nb">        non</span><span class="o">-</span><span class="nb">initial states it must be left unconstrained.</span>

<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_t| </span><span class="o">((</span><span class="nb">state |&lt;mod&gt;_s|</span><span class="o">)</span><span class="nb"> </span><span class="o">(</span><span class="nb">next_state |&lt;mod&gt;_s|</span><span class="o">))</span><span class="nb"> Bool </span><span class="o">(</span><span class="nb">...</span><span class="o">))</span><span class="nb"></span>
<span class="nb">        This function evaluates to &#39;true&#39; if the states &#39;state&#39; and</span>
<span class="nb">        &#39;next_state&#39; form a valid state transition.</span>

<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_a| </span><span class="o">((</span><span class="nb">state |&lt;mod&gt;_s|</span><span class="o">))</span><span class="nb"> Bool </span><span class="o">(</span><span class="nb">...</span><span class="o">))</span><span class="nb"></span>
<span class="nb">        This function evaluates to &#39;true&#39; if all assertions hold in the state.</span>

<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_u| </span><span class="o">((</span><span class="nb">state |&lt;mod&gt;_s|</span><span class="o">))</span><span class="nb"> Bool </span><span class="o">(</span><span class="nb">...</span><span class="o">))</span><span class="nb"></span>
<span class="nb">        This function evaluates to &#39;true&#39; if all assumptions hold in the state.</span>

<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">assert &lt;id&gt; &lt;filename:linenum&gt;</span>
<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_a &lt;id&gt;| </span><span class="o">((</span><span class="nb">state |&lt;mod&gt;_s|</span><span class="o">))</span><span class="nb"> Bool </span><span class="o">(</span><span class="nb">...</span><span class="o">))</span><span class="nb"></span>
<span class="nb">        Each </span><span class="s">$</span>assert cell is converted into one of this functions. The function
        evaluates to &#39;true&#39; if the assert statement holds in the state.

    ; yosys-smt2-assume &lt;id&gt; &lt;filename:linenum&gt;
    (define-fun |&lt;mod&gt;<span class="nb">_</span>u &lt;id&gt;| ((state |&lt;mod&gt;<span class="nb">_</span>s|)) Bool (...))
        Each <span class="s">$</span><span class="nb">assume cell is converted into one of this functions. The function</span>
<span class="nb">        evaluates to &#39;true&#39; if the assume statement holds in the state.</span>

<span class="nb">    ; yosys</span><span class="o">-</span><span class="nb">smt</span><span class="m">2</span><span class="o">-</span><span class="nb">cover &lt;id&gt; &lt;filename:linenum&gt;</span>
<span class="nb">    </span><span class="o">(</span><span class="nb">define</span><span class="o">-</span><span class="nb">fun |&lt;mod&gt;_c &lt;id&gt;| </span><span class="o">((</span><span class="nb">state |&lt;mod&gt;_s|</span><span class="o">))</span><span class="nb"> Bool </span><span class="o">(</span><span class="nb">...</span><span class="o">))</span><span class="nb"></span>
<span class="nb">        Each </span><span class="s">$</span>cover cell is converted into one of this functions. The function
        evaluates to &#39;true&#39; if the cover statement is activated in the state.

Options:

    -verbose
        this will print the recursive walk used to export the modules.

    -stbv
        Use a BitVec sort to represent a state instead of an uninterpreted
        sort. As a side-effect this will prevent use of arrays to model
        memories.

    -stdt
        Use SMT-LIB 2.6 style datatypes to represent a state instead of an
        uninterpreted sort.

    -nobv
        disable support for BitVec (FixedSizeBitVectors theory). without this
        option multi-bit wires are represented using the BitVec sort and
        support for coarse grain cells (incl. arithmetic) is enabled.

    -nomem
        disable support for memories (via ArraysEx theory). this option is
        implied by -nobv. only <span class="s">$</span><span class="nb">mem cells without merged registers in</span>
<span class="nb">        read ports are supported. call &quot;memory&quot; with </span><span class="o">-</span><span class="nb">nordff to make sure</span>
<span class="nb">        that no registers are merged into </span><span class="s">$</span>mem read ports. &#39;&lt;mod&gt;<span class="nb">_</span>m&#39; functions
        will be generated for accessing the arrays that are used to represent
        memories.

    -wires
        create &#39;&lt;mod&gt;<span class="nb">_</span>n&#39; functions for all public wires. by default only ports,
        registers, and wires with the &#39;keep&#39; attribute are exported.

    -tpl &lt;template<span class="nb">_</span>file&gt;
        use the given template file. the line containing only the token &#39;<span class="c">%%&#39;</span>
        is replaced with the regular output of this command.

[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
R. Cok&#39;s tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf

---------------------------------------------------------------------------

Example:

Consider the following module (test.v). We want to prove that the output can
never transition from a non-zero value to a zero value.

        module test(input clk, output reg [3:0] y);
          always @(posedge clk)
            y &lt;= (y &lt;&lt; 1) | <span class="nb">^</span>y;
        endmodule

For this proof we create the following template (test.tpl).

        ; we need QF<span class="nb">_</span>UFBV for this proof
        (set-logic QF<span class="nb">_</span>UFBV)

        ; insert the auto-generated code here
        <span class="c">%%</span>

        ; declare two state variables s1 and s2
        (declare-fun s1 () test<span class="nb">_</span>s)
        (declare-fun s2 () test<span class="nb">_</span>s)

        ; state s2 is the successor of state s1
        (assert (test<span class="nb">_</span>t s1 s2))

        ; we are looking for a model with y non-zero in s1
        (assert (distinct (|test<span class="nb">_</span>n y| s1) #b0000))

        ; we are looking for a model with y zero in s2
        (assert (= (|test<span class="nb">_</span>n y| s2) #b0000))

        ; is there such a model?
        (check-sat)

The following yosys script will create a &#39;test.smt2&#39; file for our proof:

        read<span class="nb">_</span>verilog test.v
        hierarchy -check; proc; opt; check -assert
        write<span class="nb">_</span>smt2 -bv -tpl test.tpl test.smt2

Running &#39;cvc4 test.smt2&#39; will print &#39;unsat&#39; because y can never transition
from non-zero to zero in the test design.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>write<span class="k">\_</span>smv -- write design to SMV file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:write<span class="nb">_</span>smv<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    write<span class="nb">_</span>smv [options] [filename]

Write an SMV description of the current design.

    -verbose
        this will print the recursive walk used to export the modules.

    -tpl &lt;template<span class="nb">_</span>file&gt;
        use the given template file. the line containing only the token &#39;<span class="c">%%&#39;</span>
        is replaced with the regular output of this command.

THIS COMMAND IS UNDER CONSTRUCTION
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>write<span class="k">\_</span>spice -- write design to SPICE netlist file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:write<span class="nb">_</span>spice<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    write<span class="nb">_</span>spice [options] [filename]

Write the current design to an SPICE netlist file.

    -big<span class="nb">_</span>endian
        generate multi-bit ports in MSB first order
        (default is LSB first)

    -neg net<span class="nb">_</span>name
        set the net name for constant 0 (default: Vss)

    -pos net<span class="nb">_</span>name
        set the net name for constant 1 (default: Vdd)

    -nc<span class="nb">_</span>prefix
        prefix for not-connected nets (default: <span class="nb">_</span>NC)

    -inames
        include names of internal (<span class="s">$</span><span class="o">-</span><span class="nb">prefixed</span><span class="o">)</span><span class="nb"> nets in outputs</span>
<span class="nb">        </span><span class="o">(</span><span class="nb">default is to use net numbers instead</span><span class="o">)</span><span class="nb"></span>

<span class="nb">    </span><span class="o">-</span><span class="nb">top top_module</span>
<span class="nb">        set the specified module as design top module</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">table </span><span class="o">--</span><span class="nb"> write design as connectivity table}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_table}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_table </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write the current design as connectivity table. The output is a tab</span><span class="o">-</span><span class="nb">separated</span>
<span class="nb">ASCII table with the following columns:</span>

<span class="nb">  module name</span>
<span class="nb">  cell name</span>
<span class="nb">  cell type</span>
<span class="nb">  cell port</span>
<span class="nb">  direction</span>
<span class="nb">  signal</span>

<span class="nb">module inputs and outputs are output using cell type and port &#39;</span><span class="o">-</span><span class="nb">&#39; and with</span>
<span class="nb">&#39;pi&#39; </span><span class="o">(</span><span class="nb">primary input</span><span class="o">)</span><span class="nb"> or &#39;po&#39; </span><span class="o">(</span><span class="nb">primary output</span><span class="o">)</span><span class="nb"> or &#39;pio&#39; as direction.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{write</span><span class="nv">\_</span><span class="nb">verilog </span><span class="o">--</span><span class="nb"> write design to Verilog file}</span>
<span class="nv">\label</span><span class="nb">{cmd:write_verilog}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    write_verilog </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">filename</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Write the current design to a Verilog file.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">norename</span>
<span class="nb">        without this option all internal object names </span><span class="o">(</span><span class="nb">the ones with a dollar</span>
<span class="nb">        instead of a backslash prefix</span><span class="o">)</span><span class="nb"> are changed to short names in the</span>
<span class="nb">        format &#39;_&lt;number&gt;_&#39;.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">renameprefix &lt;prefix&gt;</span>
<span class="nb">        insert this prefix in front of auto</span><span class="o">-</span><span class="nb">generated instance names</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noattr</span>
<span class="nb">        with this option no attributes are included in the output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">attr</span><span class="m">2</span><span class="nb">comment</span>
<span class="nb">        with this option attributes are included as comments in the output</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">noexpr</span>
<span class="nb">        without this option all internal cells are converted to Verilog</span>
<span class="nb">        expressions.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">siminit</span>
<span class="nb">        add initial statements with hierarchical refs to initialize FFs when</span>
<span class="nb">        in </span><span class="o">-</span><span class="nb">noexpr mode.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nodec</span>
<span class="nb">        </span><span class="m">32</span><span class="o">-</span><span class="nb">bit constant values are by default dumped as decimal numbers,</span>
<span class="nb">        not bit pattern. This option deactivates this feature and instead</span>
<span class="nb">        will write out all constants in binary.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">decimal</span>
<span class="nb">        dump </span><span class="m">32</span><span class="o">-</span><span class="nb">bit constants in decimal and without size and radix</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nohex</span>
<span class="nb">        constant values that are compatible with hex output are usually</span>
<span class="nb">        dumped as hex values. This option deactivates this feature and</span>
<span class="nb">        instead will write out all constants in binary.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">nostr</span>
<span class="nb">        Parameters and attributes that are specified as strings in the</span>
<span class="nb">        original input will be output as strings by this back</span><span class="o">-</span><span class="nb">end. This</span>
<span class="nb">        deactivates this feature and instead will write string constants</span>
<span class="nb">        as binary numbers.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">extmem</span>
<span class="nb">        instead of initializing memories using assignments to individual</span>
<span class="nb">        elements, use the &#39;</span><span class="s">$</span>readmemh&#39; function to read initialization data
        from a file. This data is written to a file named by appending
        a sequential index to the Verilog filename and replacing the extension
        with &#39;.mem&#39;, e.g. &#39;write<span class="nb">_</span>verilog -extmem foo.v&#39; writes &#39;foo-1.mem&#39;,
        &#39;foo-2.mem&#39; and so on.

    -defparam
        use &#39;defparam&#39; statements instead of the Verilog-2001 syntax for
        cell parameters.

    -blackboxes
        usually modules with the &#39;blackbox&#39; attribute are ignored. with
        this option set only the modules with the &#39;blackbox&#39; attribute
        are written to the output file.

    -selected
        only write selected modules. modules must be selected entirely or
        not at all.

    -v
        verbose output (print new names of all renamed wires and cells)

Note that RTLIL processes can&#39;t always be mapped directly to Verilog
always blocks. This frontend should only be used to export an RTLIL
netlist, i.e. after the &quot;proc&quot; pass has been used to convert all
processes to logic networks and registers. A warning is generated when
this command is called on a design with RTLIL processes.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>write<span class="k">\_</span>xaiger -- write design to XAIGER file<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:write<span class="nb">_</span>xaiger<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    write<span class="nb">_</span>xaiger [options] [filename]

Write the top module (according to the (* top *) attribute or if only one module
is currently selected) to an XAIGER file. Any non <span class="s">$</span><span class="nb">_NOT_, </span><span class="s">$</span><span class="nb">_</span>AND<span class="nb">_</span>, <span class="s">$</span><span class="nb">_ABC</span><span class="m">9</span><span class="nb">_FF_, ornon </span><span class="o">(*</span><span class="nb"> abc</span><span class="m">9</span><span class="nb">_box_id </span><span class="o">*)</span><span class="nb"> cells will be converted into psuedo</span><span class="o">-</span><span class="nb">inputs and</span>
<span class="nb">pseudo</span><span class="o">-</span><span class="nb">outputs. Whitebox contents will be taken from the &#39;&lt;module</span><span class="o">-</span><span class="nb">name&gt;</span><span class="s">$</span>holes&#39;
module, if it exists.

    -ascii
        write ASCII version of AIGER format

    -map &lt;filename&gt;
        write an extra file with port and box symbols
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>xilinx<span class="k">\_</span>dffopt -- Xilinx: optimize FF control signal usage<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:xilinx<span class="nb">_</span>dffopt<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    xilinx<span class="nb">_</span>dffopt [options] [selection]

Converts hardware clock enable and set/reset signals on FFs to emulation
using LUTs, if doing so would improve area.  Operates on post-techmap Xilinx
cells (LUT*, FD*).

    -lut4
        Assume a LUT4-based device (instead of a LUT6-based device).
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>xilinx<span class="k">\_</span>dsp -- Xilinx: pack resources into DSPs<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>cmd:xilinx<span class="nb">_</span>dsp<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
    xilinx<span class="nb">_</span>dsp [options] [selection]

Pack input registers (A2, A1, B2, B1, C, D, AD; with optional enable/reset),
pipeline registers (M; with optional enable/reset), output registers (P; with
optional enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.

Multiply-accumulate operations using the post-adder with feedback on the &#39;C&#39;
input will be folded into the DSP. In this scenario only, the &#39;C&#39; input can be
used to override the current accumulation result with a new value, which will
be added to the multiplier result to form the next accumulation result.

Use of the dedicated &#39;PCOUT&#39; -&gt; &#39;PCIN&#39; cascade path is detected for &#39;P&#39; -&gt; &#39;C&#39;
connections (optionally, where &#39;P&#39; is right-shifted by 17-bits and used as an
input to the post-adder -- a pattern common for summing partial products to
implement wide multipliers). Limited support also exists for similar cascading
for A and B using &#39;[AB]COUT&#39; -&gt; &#39;[AB]CIN&#39;. Currently, cascade chains are limited
to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series
device.

This pass is a no-op if the scratchpad variable &#39;xilinx<span class="nb">_</span>dsp.multonly&#39; is set
to 1.


Experimental feature: addition/subtractions less than 12 or 24 bits with the
&#39;(* use<span class="nb">_</span>dsp=&quot;simd&quot; *)&#39; attribute attached to the output wire or attached to
the add/subtract operator will cause those operations to be implemented using
the &#39;SIMD&#39; feature of DSPs.

Experimental feature: the presence of a `<span class="s">$</span><span class="nb">ge&#39; cell attached to the registered</span>
<span class="nb">P output implementing the operation &quot;</span><span class="o">(</span><span class="nb">P &gt;</span><span class="o">=</span><span class="nb"> &lt;power</span><span class="o">-</span><span class="nb">of</span><span class="o">-</span><span class="m">2</span><span class="nb">&gt;</span><span class="o">)</span><span class="nb">&quot; will be transformed</span>
<span class="nb">into using the DSP</span><span class="m">48</span><span class="nb">E</span><span class="m">1</span><span class="nb">&#39;s pattern detector feature for overflow detection.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">family {xcup|xcu|xc</span><span class="m">7</span><span class="nb">|xc</span><span class="m">6</span><span class="nb">v|xc</span><span class="m">5</span><span class="nb">v|xc</span><span class="m">4</span><span class="nb">v|xc</span><span class="m">6</span><span class="nb">s|xc</span><span class="m">3</span><span class="nb">sda}</span>
<span class="nb">        select the family to target</span>
<span class="nb">        default: xc</span><span class="m">7</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{xilinx</span><span class="nv">\_</span><span class="nb">srl </span><span class="o">--</span><span class="nb"> Xilinx shift register extraction}</span>
<span class="nv">\label</span><span class="nb">{cmd:xilinx_srl}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    xilinx_srl </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">This pass converts chains of built</span><span class="o">-</span><span class="nb">in flops </span><span class="o">(</span><span class="nb">bit</span><span class="o">-</span><span class="nb">level: </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>[NP]<span class="nb">_</span>, <span class="s">$</span><span class="nb">_DFFE_</span><span class="o">*</span><span class="nb"></span>
<span class="nb">and word</span><span class="o">-</span><span class="nb">level: </span><span class="s">$</span>dff, <span class="s">$</span><span class="nb">dffe</span><span class="o">)</span><span class="nb"> as well as Xilinx flops </span><span class="o">(</span><span class="nb">FDRE, FDRE_</span><span class="m">1</span><span class="o">)</span><span class="nb"> into a</span>
<span class="s">$</span><span class="nb">__</span>XILINX<span class="nb">_</span>SHREG cell. Chains must be of the same cell type, clock, clock polarity,
enable, and enable polarity (where relevant).
Flops with resets cannot be mapped to Xilinx devices and will not be inferred.
    -minlen N
        min length of shift register (default = 3)

    -fixed
        infer fixed-length shift registers.

    -variable
        infer variable-length shift registers (i.e. fixed-length shifts where
        each element also fans-out to a <span class="s">$</span><span class="nb">shiftx cell</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\section</span><span class="nb">{zinit </span><span class="o">--</span><span class="nb"> add inverters so all FF are zero</span><span class="o">-</span><span class="nb">initialized}</span>
<span class="nv">\label</span><span class="nb">{cmd:zinit}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    zinit </span><span class="o">[</span><span class="nb">options</span><span class="o">]</span><span class="nb"> </span><span class="o">[</span><span class="nb">selection</span><span class="o">]</span><span class="nb"></span>

<span class="nb">Add inverters as needed to make all FFs zero</span><span class="o">-</span><span class="nb">initialized.</span>

<span class="nb">    </span><span class="o">-</span><span class="nb">all</span>
<span class="nb">        also add zero initialization to uninitialized FFs</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
</pre></div>
</code></pre></td></tr></table>
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