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Please do not open any NEW issue here - we will be closing the Github issues
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<div id='cgit'><table id='header'>
<tr>
<td class='logo' rowspan='2'><a href='/cgit/'><img src='/cgit.png' alt='cgit logo'/></a></td>
<td class='main'><a href='/cgit/'>index</a> : <a title='iCE40/yosys' href='/cgit/iCE40/yosys/'>iCE40/yosys</a></td><td class='form'><form method='get'>
<input type='hidden' name='id' value='02973474df5b0b88b1744baa9cec703d089ff007'/><select name='h' onchange='this.form.submit();'>
<option value='master' selected='selected'>master</option>
</select> <input type='submit' value='switch'/></form></td></tr>
<tr><td class='sub'>clone of https://github.com/YosysHQ/yosys</td><td class='sub right'></td></tr></table>
<table class='tabs'><tr><td>
<a href='/cgit/iCE40/yosys/about/'>about</a><a href='/cgit/iCE40/yosys/'>summary</a><a href='/cgit/iCE40/yosys/refs/?id=02973474df5b0b88b1744baa9cec703d089ff007'>refs</a><a href='/cgit/iCE40/yosys/log/manual/PRESENTATION_ExSyn.tex'>log</a><a class='active' href='/cgit/iCE40/yosys/tree/manual/PRESENTATION_ExSyn.tex?id=02973474df5b0b88b1744baa9cec703d089ff007'>tree</a><a href='/cgit/iCE40/yosys/commit/manual/PRESENTATION_ExSyn.tex?id=02973474df5b0b88b1744baa9cec703d089ff007'>commit</a><a href='/cgit/iCE40/yosys/diff/manual/PRESENTATION_ExSyn.tex?id=02973474df5b0b88b1744baa9cec703d089ff007'>diff</a><a href='/cgit/iCE40/yosys/stats/manual/PRESENTATION_ExSyn.tex'>stats</a></td><td class='form'><form class='right' method='get' action='/cgit/iCE40/yosys/log/manual/PRESENTATION_ExSyn.tex'>
<input type='hidden' name='id' value='02973474df5b0b88b1744baa9cec703d089ff007'/><select name='qt'>
<option value='grep'>log msg</option>
<option value='author'>author</option>
<option value='committer'>committer</option>
<option value='range'>range</option>
</select>
<input class='txt' type='search' size='10' name='q' value=''/>
<input type='submit' value='search'/>
</form>
</td></tr></table>
<div class='path'>path: <a href='/cgit/iCE40/yosys/tree/?id=02973474df5b0b88b1744baa9cec703d089ff007'>root</a>/<a href='/cgit/iCE40/yosys/tree/manual?id=02973474df5b0b88b1744baa9cec703d089ff007'>manual</a>/<a href='/cgit/iCE40/yosys/tree/manual/PRESENTATION_ExSyn.tex?id=02973474df5b0b88b1744baa9cec703d089ff007'>PRESENTATION_ExSyn.tex</a></div><div class='content'>blob: 655720ebc6482331f8b0e8460382be679bd4e32d (<a href='/cgit/iCE40/yosys/plain/manual/PRESENTATION_ExSyn.tex?id=02973474df5b0b88b1744baa9cec703d089ff007'>plain</a>)
<table summary='blob content' class='blob'>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\section</span><span class="nb">{</span>Yosys by example -- Synthesis<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\sectionpage</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Typical Phases of a Synthesis Flow<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Reading and elaborating the design
<span class="k">\item</span> Higher-level synthesis and optimization
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Converting <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span>-blocks to logic and registers
<span class="k">\item</span> Perform coarse-grain optimizations (resource sharing, const folding, ...)
<span class="k">\item</span> Handling of memories and other coarse-grain blocks
<span class="k">\item</span> Extracting and optimizing finite state machines
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Convert remaining logic to bit-level logic functions
<span class="k">\item</span> Perform optimizations on bit-level logic functions
<span class="k">\item</span> Map bit-level logic gates and registers to cell library
<span class="k">\item</span> Write results to output file
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Reading the design<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
read<span class="nb">_</span>verilog file1.v
read<span class="nb">_</span>verilog -I include<span class="nb">_</span>dir -D enable<span class="nb">_</span>foo -D WIDTH=12 file2.v
read<span class="nb">_</span>verilog -lib cell<span class="nb">_</span>library.v

verilog<span class="nb">_</span>defaults -add -I include<span class="nb">_</span>dir
read<span class="nb">_</span>verilog file3.v
read<span class="nb">_</span>verilog file4.v
verilog<span class="nb">_</span>defaults -clear

verilog<span class="nb">_</span>defaults -push
verilog<span class="nb">_</span>defaults -add -I include<span class="nb">_</span>dir
read<span class="nb">_</span>verilog file5.v
read<span class="nb">_</span>verilog file6.v
verilog<span class="nb">_</span>defaults -pop
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Design elaboration<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
During design elaboration Yosys figures out how the modules are hierarchically
connected. It also re-runs the AST parts of the Verilog frontend to create
all needed variations of parametric modules.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
# simplest form. at least this version should be used after reading all input files
#
hierarchy

# recommended form. fails if parts of the design hierarchy are missing, removes
# everything that is unreachable from the top module, and marks the top module.
#
hierarchy -check -top top<span class="nb">_</span>module
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
The Verilog frontend converts <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span>-blocks to RTL netlists for the
expressions and ``processes&#39;&#39; for the control- and memory elements.

<span class="k">\medskip</span>
The <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> command transforms this ``processes&#39;&#39; to netlists of RTL
multiplexer and register cells.

<span class="k">\medskip</span>
The <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> command is actually a macro-command that calls the following
other commands:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
proc<span class="nb">_</span>clean      # remove empty branches and processes
proc<span class="nb">_</span>rmdead     # remove unreachable branches
proc<span class="nb">_</span>init       # special handling of &quot;initial&quot; blocks
proc<span class="nb">_</span>arst       # identify modeling of async resets
proc<span class="nb">_</span>mux        # convert decision trees to multiplexer networks
proc<span class="nb">_</span>dff        # extract registers from processes
proc<span class="nb">_</span>clean      # if all went fine, this should remove all the processes
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\medskip</span>
Many commands can not operate on modules with ``processes&#39;&#39; in them. Usually
a call to <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> is the first command in the actual synthesis procedure
after design elaboration.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 1/3<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>01.v<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>01.ys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\hfil\includegraphics</span><span class="na">[width=8cm,trim=0 0cm 0 0cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>01.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 2/3<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>02.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>02.v<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>02.ys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 3/3<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>03.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>03.ys<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/proc<span class="nb">_</span>03.v<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> command implements a series of simple optimizations. It also
is a macro command that calls other commands:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
opt<span class="nb">_</span>expr                # const folding and simple expression rewriting
opt<span class="nb">_</span>merge -nomux        # merging identical cells

do
    opt<span class="nb">_</span>muxtree         # remove never-active branches from multiplexer tree
    opt<span class="nb">_</span>reduce          # consolidate trees of boolean ops to reduce functions
    opt<span class="nb">_</span>merge           # merging identical cells
    opt<span class="nb">_</span>rmdff           # remove/simplify registers with constant inputs
    opt<span class="nb">_</span>clean           # remove unused objects (cells, wires) from design
    opt<span class="nb">_</span>expr            # const folding and simple expression rewriting
while [changed design]
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

The command <span class="nb">{</span><span class="k">\tt</span> clean<span class="nb">}</span> can be used as alias for <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>clean<span class="nb">}</span>. And <span class="nb">{</span><span class="k">\tt</span> ;;<span class="nb">}</span>
can be used as shortcut for <span class="nb">{</span><span class="k">\tt</span> clean<span class="nb">}</span>. For example:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
proc; opt; memory; opt<span class="nb">_</span>expr;; fsm;;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 1/4<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0cm 0cm 0cm -0.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>01.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>01.ys<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>01.v<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 2/4<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0cm 0cm 0cm 0cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>02.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>02.ys<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>02.v<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 3/4<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0cm 0cm 0cm -2cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>03.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>03.ys<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>03.v<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 4/4<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\hskip</span>6cm<span class="k">\includegraphics</span><span class="na">[width=6cm,trim=0cm 0cm 0cm -3cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>04.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>04.v<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/opt<span class="nb">_</span>04.ys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>When to use <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> clean<span class="nb">}}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
Usually it does not hurt to call <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> after each regular command in the
synthesis script. But it increases the synthesis time, so it is favourable
to only call <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> when an improvement can be achieved.

<span class="k">\bigskip</span>
The designs in <span class="nb">{</span><span class="k">\tt</span> yosys-bigsim<span class="nb">}</span> are a good playground for experimenting with
the effects of calling <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> in various places of the flow.

<span class="k">\bigskip</span>
It generally is a good idea to call <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> before inherently expensive
commands such as <span class="nb">{</span><span class="k">\tt</span> sat<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> freduce<span class="nb">}</span>, as the possible gain is much
higher in this cases as the possible loss.

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> clean<span class="nb">}</span> command on the other hand is very fast and many commands leave
a mess (dangling signal wires, etc). For example, most commands do not remove
any wires or cells. They just change the connections and depend on a later
call to clean to get rid of the now unused objects. So the occasional <span class="nb">{</span><span class="k">\tt</span> ;;<span class="nb">}</span>
is a good idea in every synthesis script.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span> command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
In the RTL netlist, memory reads and writes are individual cells. This makes
consolidating the number of ports for a memory easier. The <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span>
transforms memories to an implementation. Per default that is logic for address
decoders and registers. It also is a macro command that calls other commands:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
# this merges registers into the memory read- and write cells.
memory<span class="nb">_</span>dff

# this collects all read and write cells for a memory and transforms them
# into one multi-port memory cell.
memory<span class="nb">_</span>collect

# this takes the multi-port memory cell and transforms it to address decoder
# logic and registers. This step is skipped if &quot;memory&quot; is called with -nomap.
memory<span class="nb">_</span>map
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Usually it is preferred to use architecture-specific RAM resources for memory.
For example:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
memory -nomap; techmap -map my<span class="nb">_</span>memory<span class="nb">_</span>map.v; memory<span class="nb">_</span>map
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 1/2<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=0.7\linewidth,trim=0cm 0cm 0cm -10cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/memory<span class="nb">_</span>01.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/memory<span class="nb">_</span>01.ys<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/memory<span class="nb">_</span>01.v<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example 2/2<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\hfill\includegraphics</span><span class="na">[width=7.5cm,trim=0cm 0cm 0cm -5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/memory<span class="nb">_</span>02.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{6pt}{8pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/memory<span class="nb">_</span>02.v<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/memory<span class="nb">_</span>02.ys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="nb">}</span> command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}}</span>
The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="nb">}</span> command identifies, extracts, optimizes (re-encodes), and
re-synthesizes finite state machines. It again is a macro that calls
a series of other commands:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
fsm<span class="nb">_</span>detect          # unless got option -nodetect
fsm<span class="nb">_</span>extract

fsm<span class="nb">_</span>opt
clean
fsm<span class="nb">_</span>opt

fsm<span class="nb">_</span>expand          # if got option -expand
clean               # if got option -expand
fsm<span class="nb">_</span>opt             # if got option -expand

fsm<span class="nb">_</span>recode          # unless got option -norecode

fsm<span class="nb">_</span>info

fsm<span class="nb">_</span>export          # if got option -export
fsm<span class="nb">_</span>map             # unless got option -nomap
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- details<span class="nb">}</span>
Some details on the most important commands from the <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_*</span><span class="nb">}</span> group:

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>detect<span class="nb">}</span> command identifies FSM state registers and marks them
with the <span class="nb">{</span><span class="k">\tt</span> (* fsm<span class="k">\_</span>encoding = &quot;auto&quot; *)<span class="nb">}</span> attribute, if they do not have the
<span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>encoding<span class="nb">}</span> set already. Mark registers with <span class="nb">{</span><span class="k">\tt</span> (* fsm<span class="k">\_</span>encoding =
&quot;none&quot; *)<span class="nb">}</span> to disable FSM optimization for a register.

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>extract<span class="nb">}</span> command replaces the entire FSM (logic and state
registers) with a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cell.

<span class="k">\bigskip</span>
The commands <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>opt<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>recode<span class="nb">}</span> can be used to optimize the
FSM.

<span class="k">\bigskip</span>
Finally the <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>map<span class="nb">}</span> command can be used to convert the (optimized) <span class="nb">{</span><span class="k">\tt</span>
<span class="k">\$</span>fsm<span class="nb">}</span> cell back to logic and registers.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=12cm,trim=-15cm 0cm 0cm -20cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/techmap<span class="nb">_</span>01.pdf<span class="nb">}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\vskip</span>-0.8cm
The <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> command replaces cells with implementations given as
verilog source. For example implementing a 32 bit adder using 16 bit adders:

<span class="k">\vbox</span> to 0cm<span class="nb">{</span>
<span class="k">\vskip</span>-0.3cm
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/techmap<span class="nb">_</span>01<span class="nb">_</span>map.v<span class="nb">}</span>
<span class="nb">}</span><span class="k">\vbox</span> to 0cm<span class="nb">{</span>
<span class="k">\vskip</span>-0.5cm
<span class="k">\lstinputlisting</span><span class="na">[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/techmap<span class="nb">_</span>01.v<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/techmap<span class="nb">_</span>01.ys<span class="nb">}</span>
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- stdcell mapping<span class="nb">}</span>
When <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> is used without a map file, it uses a built-in map file
to map all RTL cell types to a generic library of built-in logic gates and registers.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span>The built-in logic gate types are:<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOT<span class="k">\_</span> <span class="k">\$\_</span>AND<span class="k">\_</span> <span class="k">\$\_</span>OR<span class="k">\_</span> <span class="k">\$\_</span>XOR<span class="k">\_</span> <span class="k">\$\_</span>MUX<span class="k">\_</span><span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span>The register types are:<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SR<span class="k">\_</span>NN<span class="k">\_</span> <span class="k">\$\_</span>SR<span class="k">\_</span>NP<span class="k">\_</span> <span class="k">\$\_</span>SR<span class="k">\_</span>PN<span class="k">\_</span> <span class="k">\$\_</span>SR<span class="k">\_</span>PP<span class="k">\_</span> <span class="k">\\</span>
<span class="k">\$\_</span>DFF<span class="k">\_</span>N<span class="k">\_</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>P<span class="k">\_</span> <span class="k">\\</span>
<span class="k">\$\_</span>DFF<span class="k">\_</span>NN0<span class="k">\_</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NN1<span class="k">\_</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP0<span class="k">\_</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP1<span class="k">\_</span> <span class="k">\\</span>
<span class="k">\$\_</span>DFF<span class="k">\_</span>PN0<span class="k">\_</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PN1<span class="k">\_</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP0<span class="k">\_</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP1<span class="k">\_</span> <span class="k">\\</span>
<span class="k">\$\_</span>DFFSR<span class="k">\_</span>NNN<span class="k">\_</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>NNP<span class="k">\_</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>NPN<span class="k">\_</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>NPP<span class="k">\_</span> <span class="k">\\</span>
<span class="k">\$\_</span>DFFSR<span class="k">\_</span>PNN<span class="k">\_</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>PNP<span class="k">\_</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>PPN<span class="k">\_</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>PPP<span class="k">\_</span> <span class="k">\\</span>
<span class="k">\$\_</span>DLATCH<span class="k">\_</span>N<span class="k">\_</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>P<span class="k">\_</span><span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The <span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> command provides an interface to ABC<span class="k">\footnote</span><span class="na">[frame]</span><span class="nb">{</span><span class="k">\url</span><span class="nb">{</span>http://www.eecs.berkeley.edu/~alanmi/abc/<span class="nb">}}</span>,
an open source tool for low-level logic synthesis.

<span class="k">\medskip</span>
The <span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> command processes a netlist of internal gate types and can perform:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> logic minimization (optimization)
<span class="k">\item</span> mapping of logic to standard cell library (liberty format)
<span class="k">\item</span> mapping of logic to k-LUTs (for FPGA synthesis)
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\medskip</span>
Optionally <span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> can process registers from one clock domain and perform
sequential optimization (such as register balancing).

<span class="k">\medskip</span>
ABC is also controlled using scripts. An ABC script can be specified to use
more advanced ABC features. It is also possible to write the design with
<span class="nb">{</span><span class="k">\tt</span> write<span class="k">\_</span>blif<span class="nb">}</span> and load the output file into ABC outside of Yosys.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Example<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/abc<span class="nb">_</span>01.v<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/abc<span class="nb">_</span>01.ys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0 0cm 0 0cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExSyn/abc<span class="nb">_</span>01.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Other special-purpose mapping commands<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span><span class="k">\tt</span> dfflibmap<span class="nb">}</span>
This command maps the internal register cell types to the register types
described in a liberty file.
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span><span class="k">\tt</span> hilomap<span class="nb">}</span>
Some architectures require special driver cells for driving a constant hi or lo
value. This command replaces simple constants with instances of such driver cells.
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span><span class="k">\tt</span> iopadmap<span class="nb">}</span>
Top-level input/outputs must usually be implemented using special I/O-pad cells.
This command inserts this cells to the design.
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Example Synthesis Script<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>4cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>6pt<span class="nb">}{</span>7pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
# read and elaborate design
read<span class="nb">_</span>verilog cpu<span class="nb">_</span>top.v cpu<span class="nb">_</span>ctrl.v cpu<span class="nb">_</span>regs.v
read<span class="nb">_</span>verilog -D WITH<span class="nb">_</span>MULT cpu<span class="nb">_</span>alu.v
hierarchy -check -top cpu<span class="nb">_</span>top

# high-level synthesis
proc; opt; fsm;; memory -nomap; opt

# substitute block rams
techmap -map map<span class="nb">_</span>rams.v

# map remaining memories
memory<span class="nb">_</span>map

# low-level synthesis
techmap; opt; flatten;; abc -lut6
techmap -map map<span class="nb">_</span>xl<span class="nb">_</span>cells.v

# add clock buffers
select -set xl<span class="nb">_</span>clocks t:FDRE <span class="c">%x:+FDRE[C] t:FDRE %d</span>
iopadmap -inpad BUFGP O:I @xl<span class="nb">_</span>clocks

# add io buffers
select -set xl<span class="nb">_</span>nonclocks w:* t:BUFGP <span class="c">%x:+BUFGP[I] %d</span>
iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl<span class="nb">_</span>nonclocks

# write synthesis results
write<span class="nb">_</span>edif synth.edif
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>6cm<span class="nb">}</span>
<span class="k">\vskip</span>1cm
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span>Teaser / Outlook<span class="nb">}</span>
<span class="k">\small\parbox</span><span class="nb">{</span>6cm<span class="nb">}{</span>
The weird <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> expressions at the end of this script are discussed in
the next part (Section 3, ``Advanced Synthesis&#39;&#39;) of this presentation.<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Summary<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Yosys provides commands for each phase of the synthesis.
<span class="k">\item</span> Each command solves a (more or less) simple problem.
<span class="k">\item</span> Complex commands are often only front-ends to simple commands.
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> proc; opt; fsm; opt; memory; opt; techmap; opt; abc;;<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
Questions?
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>
</pre></div>
</code></pre></td></tr></table>
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