library ieee; use ieee.std_logic_1164.all; entity block02 is port (q : out std_logic; d : std_logic; clk : std_logic); end block02; architecture behav of block02 is begin b1 : block signal s : std_logic; begin process (clk) is begin if rising_edge (clk) then s <= d; end if; end process; q <= s; end block b1; end behav; rg/iCE40/yosys' title='iCE40/yosys Git repository'/>

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path: root/manual/PRESENTATION_ExAdv/mulshift_test.v

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module test (A, X, Y);
input [7:0] A;
output [7:0] X = A * 8'd 6;
output [7:0] Y = A * 8'd 8;
endmodule