module constpower(ys, yu); output [8*8*8-1:0] ys, yu; genvar i, j; generate for (i = 0; i < 8; i = i+1) for (j = 0; j < 8; j = j+1) begin:V assign ys[i*8 + j*64 + 7 : i*8 + j*64] = $signed(i-4) ** $signed(j-4); assign yu[i*8 + j*64 + 7 : i*8 + j*64] = $unsigned(i) ** $unsigned(j); end endgenerate endmodule cs-git' href='git://git.panaceas.org/iCE40/yosys' title='iCE40/yosys Git repository'/>
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module uut(in1, in2, in3, out1, out2);

input [8:0] in1, in2, in3;
output [8:0] out1, out2;

assign out1 = in1 + in2 + (in3 >> 4);

endmodule
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