<html><head><title>/tools/patch-image/</title></head>
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<h2>/tools/patch-image/</h2>
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<li><a href='/cgit.cgi/openwrt/upstream/plain/tools/?id=01fe21d1963ba7c904afb4e18a57e89cf9d50f0c'>../</a></li>
  <li><a href='/cgit.cgi/openwrt/upstream/plain/tools/patch-image/Makefile?id=01fe21d1963ba7c904afb4e18a57e89cf9d50f0c'>Makefile</a></li>
  <li><a href='/cgit.cgi/openwrt/upstream/plain/tools/patch-image/src/?id=01fe21d1963ba7c904afb4e18a57e89cf9d50f0c'>src</a></li>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>Optimizations<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:opt<span class="nb">}</span>

Yosys employs a number of optimizations to generate better and cleaner results.
This chapter outlines these optimizations.

<span class="k">\section</span><span class="nb">{</span>Simple Optimizations<span class="nb">}</span>

The Yosys pass <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> runs a number of simple optimizations. This includes removing unused
signals and cells and const folding. It is recommended to run this pass after each major step
in the synthesis script. At the time of this writing the <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> pass executes the following
passes that each perform a simple optimization:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Once at the beginning of <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span>:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>expr<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>merge -nomux<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Repeat until result is stable:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>muxtree<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>reduce<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>merge<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>rmdff<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>clean<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>expr<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The following section describes each of the <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_*</span><span class="nb">}</span> passes.

<span class="k">\subsection</span><span class="nb">{</span>The opt<span class="k">\_</span>expr pass<span class="nb">}</span>

This pass performs const folding on the internal combinational cell types
described in Chap.~<span class="k">\ref</span><span class="nb">{</span>chapter:celllib<span class="nb">}</span>. This means a cell with all constant
inputs is replaced with the constant value this cell drives. In some cases
this pass can also optimize cells with some constant inputs.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>
	<span class="k">\hfil</span>
	<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>cc|c<span class="nb">}</span>
		A-Input <span class="nb">&amp;</span> B-Input <span class="nb">&amp;</span> Replacement <span class="k">\\</span>
		<span class="k">\hline</span>
		any <span class="nb">&amp;</span>   0 <span class="nb">&amp;</span>   0 <span class="k">\\</span>
		  0 <span class="nb">&amp;</span> any <span class="nb">&amp;</span>   0 <span class="k">\\</span>
		  1 <span class="nb">&amp;</span>   1 <span class="nb">&amp;</span>   1 <span class="k">\\</span>
		<span class="k">\hline</span>
		X/Z <span class="nb">&amp;</span> X/Z <span class="nb">&amp;</span>   X <span class="k">\\</span>
		  1 <span class="nb">&amp;</span> X/Z <span class="nb">&amp;</span>   X <span class="k">\\</span>
		X/Z <span class="nb">&amp;</span>   1 <span class="nb">&amp;</span>   X <span class="k">\\</span>
		<span class="k">\hline</span>
		any <span class="nb">&amp;</span> X/Z <span class="nb">&amp;</span>   0 <span class="k">\\</span>
		X/Z <span class="nb">&amp;</span> any <span class="nb">&amp;</span>   0 <span class="k">\\</span>
		<span class="k">\hline</span>
		<span class="s">$</span><span class="nb">a</span><span class="s">$</span> <span class="nb">&amp;</span>   1 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">a</span><span class="s">$</span> <span class="k">\\</span>
		  1 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">b</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">b</span><span class="s">$</span> <span class="k">\\</span>
	<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Const folding rules for <span class="nb">{</span><span class="k">\tt\$\_</span>AND<span class="k">\_</span><span class="nb">}</span> cells as used in <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>expr<span class="nb">}</span>.<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>tab:opt<span class="nb">_</span>expr<span class="nb">_</span>and<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

Table~<span class="k">\ref</span><span class="nb">{</span>tab:opt<span class="nb">_</span>expr<span class="nb">_</span>and<span class="nb">}</span> shows the replacement rules used for optimizing
an <span class="nb">{</span><span class="k">\tt\$\_</span>AND<span class="k">\_</span><span class="nb">}</span> gate. The first three rules implement the obvious const folding
rules. Note that `any&#39; might include dynamic values calculated by other parts
of the circuit. The following three lines propagate undef (X) states.
These are the only three cases in which it is allowed to propagate an undef
according to Sec.~5.1.10 of IEEE Std. 1364-2005 <span class="k">\cite</span><span class="nb">{</span>Verilog2005<span class="nb">}</span>.

The next two lines assume the value 0 for undef states. These two rules are only
used if no other substitutions are possible in the current module. If other substitutions
are possible they are performed first, in the hope that the `any&#39; will change to
an undef value or a 1 and therefore the output can be set to undef.

The last two lines simply replace an <span class="nb">{</span><span class="k">\tt\$\_</span>AND<span class="k">\_</span><span class="nb">}</span> gate with one constant-1
input with a buffer.

Besides this basic const folding the <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>expr<span class="nb">}</span> pass can replace 1-bit wide
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eq<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ne<span class="nb">}</span> cells with buffers or not-gates if one input is constant.

The <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>expr<span class="nb">}</span> pass is very conservative regarding optimizing <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span> cells,
as these cells are often used to model decision-trees and breaking these trees can
interfere with other optimizations.

<span class="k">\subsection</span><span class="nb">{</span>The opt<span class="k">\_</span>muxtree pass<span class="nb">}</span>

This pass optimizes trees of multiplexer cells by analyzing the select inputs.
Consider the following simple example:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=Verilog]
module uut(a, y);
input a;
output [1:0] y = a ? (a ? 1 : 2) : 3;
endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

The output can never be 2, as this would require <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;a;
to be 1 for the outer multiplexer and 0 for the inner multiplexer. The <span class="nb">{</span><span class="k">\tt</span>
opt<span class="k">\_</span>muxtree<span class="nb">}</span> pass detects this contradiction and replaces the inner multiplexer
with a constant 1, yielding the logic for <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;y = a ? 1 : 3;.

<span class="k">\subsection</span><span class="nb">{</span>The opt<span class="k">\_</span>reduce pass<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>sloppypar<span class="nb">}</span>
This is a simple optimization pass that identifies and consolidates identical input
bits to <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>and<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> cells. It also sorts the input
bits to ease identification of shareable <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>and<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> cells
in other passes.
<span class="k">\end</span><span class="nb">{</span>sloppypar<span class="nb">}</span>

This pass also identifies and consolidates identical inputs to multiplexer cells. In this
case the new shared select bit is driven using a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> cell that combines
the original select bits.

Lastly this pass consolidates trees of <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>and<span class="nb">}</span> cells and trees of
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> cells to single large <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>and<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> cells.

These three simple optimizations are performed in a loop until a stable result is
produced.

<span class="k">\subsection</span><span class="nb">{</span>The opt<span class="k">\_</span>rmdff pass<span class="nb">}</span>

This pass identifies single-bit d-type flip-flops (<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_*</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span>
<span class="k">\$</span>adff<span class="nb">}</span> cells) with a constant data input and replaces them with a constant driver.

<span class="k">\subsection</span><span class="nb">{</span>The opt<span class="k">\_</span>clean pass<span class="nb">}</span>

This pass identifies unused signals and cells and removes them from the design. It also
creates an <span class="k">\B</span><span class="nb">{</span>unused<span class="k">\_</span>bits<span class="nb">}</span> attribute on wires with unused bits. This attribute can be
used for debugging or by other optimization passes.

<span class="k">\subsection</span><span class="nb">{</span>The opt<span class="k">\_</span>merge pass<span class="nb">}</span>

This pass performs trivial resource sharing. This means that this pass identifies cells
with identical inputs and replaces them with a single instance of the cell.

The option <span class="nb">{</span><span class="k">\tt</span> -nomux<span class="nb">}</span> can be used to disable resource sharing for multiplexer
cells (<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>pmux<span class="nb">}</span>. This can be useful as
it prevents multiplexer trees to be merged, which might prevent <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>muxtree<span class="nb">}</span>
to identify possible optimizations.

<span class="k">\section</span><span class="nb">{</span>FSM Extraction and Encoding<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="nb">}</span> pass performs finite-state-machine (FSM) extraction and recoding. The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="nb">}</span>
pass simply executes the following other passes:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Identify and extract FSMs:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>detect<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>extract<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\item</span> Basic optimizations:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>opt<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>clean<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>opt<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\item</span> Expanding to nearby gate-logic (if called with <span class="nb">{</span><span class="k">\tt</span> -expand<span class="nb">}</span>):
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>expand<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>clean<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>opt<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\item</span> Re-code FSM states (unless called with <span class="nb">{</span><span class="k">\tt</span> -norecode<span class="nb">}</span>):
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>recode<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\item</span> Print information about FSMs:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>info<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\item</span> Export FSMs in KISS2 file format (if called with <span class="nb">{</span><span class="k">\tt</span> -export<span class="nb">}</span>):
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>export<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\item</span> Map FSMs to RTL cells (unless called with <span class="nb">{</span><span class="k">\tt</span> -nomap<span class="nb">}</span>):
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>map<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>detect<span class="nb">}</span> pass identifies FSM state registers and marks them using the
<span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}{</span><span class="k">\tt</span> = &quot;auto&quot;<span class="nb">}</span> attribute. The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>extract<span class="nb">}</span> extracts all
FSMs marked using the <span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}</span> attribute (unless <span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}</span> is
set to <span class="nb">{</span><span class="k">\tt</span> &quot;none&quot;<span class="nb">}</span>) and replaces the corresponding RTL cells with a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span>
cell. All other <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_*</span><span class="nb">}</span> passes operate on these <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cells. The
<span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>map<span class="nb">}</span> call finally replaces the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cells with RTL cells.

Note that these optimizations operate on an RTL netlist. I.e.~the <span class="nb">{</span><span class="k">\tt</span> fsm<span class="nb">}</span> pass
should be executed after the <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> pass has transformed all
<span class="nb">{</span><span class="k">\tt</span> RTLIL::Process<span class="nb">}</span> objects to RTL cells.

The algorithms used for FSM detection and extraction are influenced by a more
general reported technique <span class="k">\cite</span><span class="nb">{</span>fsmextract<span class="nb">}</span>.

<span class="k">\subsection</span><span class="nb">{</span>FSM Detection<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>detect<span class="nb">}</span> pass identifies FSM state registers. It sets the
<span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}{</span><span class="k">\tt</span> = &quot;auto&quot;<span class="nb">}</span> attribute on any (multi-bit) wire that matches
the following description:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Does not already have the <span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}</span> attribute.
<span class="k">\item</span> Is not an output of the containing module.
<span class="k">\item</span> Is driven by single <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span> cell.
<span class="k">\item</span> The <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span>-Input of this <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span> cell is driven by a multiplexer
tree that only has constants or the old state value on its leaves.
<span class="k">\item</span> The state value is only used in the said multiplexer tree or by simple relational
cells that compare the state value to a constant (usually <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eq<span class="nb">}</span> cells).
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

This heuristic has proven to work very well. It is possible to overwrite it by setting
<span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}{</span><span class="k">\tt</span> = &quot;auto&quot;<span class="nb">}</span> on registers that should be considered FSM state registers
and setting <span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}{</span><span class="k">\tt</span> = &quot;none&quot;<span class="nb">}</span> on registers that match the above criteria
but should not be considered FSM state registers.

Note however that marking state registers with <span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}</span> that are not
suitable for FSM recoding can cause synthesis to fail or produce invalid
results.

<span class="k">\subsection</span><span class="nb">{</span>FSM Extraction<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>extract<span class="nb">}</span> pass operates on all state signals marked with the
<span class="k">\B</span><span class="nb">{</span>fsm<span class="k">\_</span>encoding<span class="nb">}</span> (<span class="nb">{</span><span class="k">\tt</span> != &quot;none&quot;<span class="nb">}</span>) attribute. For each state signal the following
information is determined:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The state registers
<span class="k">\item</span> The asynchronous reset state if the state registers use asynchronous reset
<span class="k">\item</span> All states and the control input signals used in the state transition functions
<span class="k">\item</span> The control output signals calculated from the state signals and control inputs
<span class="k">\item</span> A table of all state transitions and corresponding control inputs- and outputs
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The state registers (and asynchronous reset state, if applicable) is simply determined
by identifying the driver for the state signal.

From there the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span>-tree driving the state register inputs is
recursively traversed. All select inputs are control signals and the leaves of the
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span>-tree are the states. The algorithm fails if a non-constant leaf
that is not the state signal itself is found.

The list of control outputs is initialized with the bits from the state signal.
It is then extended by adding all values that are calculated by cells that
compare the state signal with a constant value.

In most cases this will cover all uses of the state register, thus rendering the
state encoding arbitrary. If however a design uses e.g.~a single bit of the state
value to drive a control output directly, this bit of the state signal will be
transformed to a control output of the same value.

Finally, a transition table for the FSM is generated. This is done by using the
<span class="nb">{</span><span class="k">\tt</span> ConstEval<span class="nb">}</span> C++ helper class (defined in <span class="nb">{</span><span class="k">\tt</span> kernel/consteval.h<span class="nb">}</span>) that can
be used to evaluate parts of the design. The <span class="nb">{</span><span class="k">\tt</span> ConstEval<span class="nb">}</span> class can be asked
to calculate a given set of result signals using a set of signal-value
assignments. It can also be passed a list of stop-signals that abort the <span class="nb">{</span><span class="k">\tt</span>
ConstEval<span class="nb">}</span> algorithm if the value of a stop-signal is needed in order to
calculate the result signals.

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>extract<span class="nb">}</span> pass uses the <span class="nb">{</span><span class="k">\tt</span> ConstEval<span class="nb">}</span> class in the following way
to create a transition table. For each state:

<span class="k">\begin</span><span class="nb">{</span>enumerate<span class="nb">}</span>
<span class="k">\item</span> Create a <span class="nb">{</span><span class="k">\tt</span> ConstEval<span class="nb">}</span> object for the module containing the FSM
<span class="k">\item</span> Add all control inputs to the list of stop signals
<span class="k">\item</span> Set the state signal to the current state
<span class="k">\item</span> Try to evaluate the next state and control output <span class="k">\label</span><span class="nb">{</span>enum:fsm<span class="nb">_</span>extract<span class="nb">_</span>cealg<span class="nb">_</span>try<span class="nb">}</span>
<span class="k">\item</span> If step~<span class="k">\ref</span><span class="nb">{</span>enum:fsm<span class="nb">_</span>extract<span class="nb">_</span>cealg<span class="nb">_</span>try<span class="nb">}</span> was not successful:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Recursively goto step~<span class="k">\ref</span><span class="nb">{</span>enum:fsm<span class="nb">_</span>extract<span class="nb">_</span>cealg<span class="nb">_</span>try<span class="nb">}</span> with the offending stop-signal set to 0.
<span class="k">\item</span> Recursively goto step~<span class="k">\ref</span><span class="nb">{</span>enum:fsm<span class="nb">_</span>extract<span class="nb">_</span>cealg<span class="nb">_</span>try<span class="nb">}</span> with the offending stop-signal set to 1.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> If step~<span class="k">\ref</span><span class="nb">{</span>enum:fsm<span class="nb">_</span>extract<span class="nb">_</span>cealg<span class="nb">_</span>try<span class="nb">}</span> was successful: Emit transition
<span class="k">\end</span><span class="nb">{</span>enumerate<span class="nb">}</span>

Finally a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cell is created with the generated transition table and added to the
module. This new cell is connected to the control signals and the old drivers for the
control outputs are disconnected.

<span class="k">\subsection</span><span class="nb">{</span>FSM Optimization<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>opt<span class="nb">}</span> pass performs basic optimizations on <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cells (not including state
recoding). The following optimizations are performed (in this order):

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Unused control outputs are removed from the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cell. The attribute <span class="k">\B</span><span class="nb">{</span>unused<span class="k">\_</span>bits<span class="nb">}</span>
(that is usually set by the <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>clean<span class="nb">}</span> pass) is used to determine which control
outputs are unused.
<span class="k">\item</span> Control inputs that are connected to the same driver are merged.
<span class="k">\item</span> When a control input is driven by a control output, the control input is removed and the transition
table altered to give the same performance without the external feedback path.
<span class="k">\item</span> Entries in the transition table that yield the same output and only
differ in the value of a single control input bit are merged and the different bit is removed
from the sensitivity list (turned into a don&#39;t-care bit).
<span class="k">\item</span> Constant inputs are removed and the transition table is altered to give an unchanged behaviour.
<span class="k">\item</span> Unused inputs are removed.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>FSM Recoding<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>recode<span class="nb">}</span> pass assigns new bit pattern to the states. Usually this
also implies a change in the width of the state signal. At the moment of this
writing only one-hot encoding with all-zero for the reset state is supported.

The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>recode<span class="nb">}</span> pass can also write a text file with the changes performed
by it that can be used when verifying designs synthesized by Yosys using Synopsys
Formality <span class="k">\citeweblink</span><span class="nb">{</span>Formality<span class="nb">}</span>.

<span class="k">\section</span><span class="nb">{</span>Logic Optimization<span class="nb">}</span>

Yosys can perform multi-level combinational logic optimization on gate-level netlists using the
external program ABC <span class="k">\citeweblink</span><span class="nb">{</span>ABC<span class="nb">}</span>. The <span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> pass extracts the combinational gate-level
parts of the design, passes it through ABC, and re-integrates the results. The <span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> pass
can also be used to perform other operations using ABC, such as technology mapping (see
Sec.~<span class="k">\ref</span><span class="nb">{</span>sec:techmap<span class="nb">_</span>extern<span class="nb">}</span> for details).
</pre></div>
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