example.v « APPNOTE_011_Design_Investigation « manual - iCE40/yosys - clone of https://github.com/YosysHQ/yosys

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module example(input clk, a, b, c,
               output reg [1:0] y);
    always @(posedge clk)
        if (c)
            y <= c ? a + b : 2'd0;
endmodule

"k">if (rst) count <= 0; else count <= count + 1; end assign ping = &count; endmodule module counter2(clk, rst, ping); input clk, rst; output ping; reg [31:0] count; integer i; reg carry; always @(posedge clk) begin carry = 1; for (i = 0; i < 32; i = i+1) begin count[i] <= !rst & (count[i] ^ carry); carry = count[i] & carry; end end assign ping = &count; endmodule