counter.v « cmos « examples - iCE40/yosys - clone of https://github.com/YosysHQ/yosys

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module counter (clk, rst, en, count);

   input clk, rst, en;
   output reg [2:0] count;

   always @(posedge clk)
      if (rst)
         count <= 3'd0;
      else if (en)
         count <= count + 3'd1;

endmodule

an> def __init__(self): self.has_errored = False def log(self, e): if e.level == "error": self.has_errored = True class DumpMaster(master.Master): def __init__( self, options: options.Options, server, with_termlog=True, with_dumper=True, ) -> None: master.Master.__init__(self, options, server) self.errorcheck = ErrorCheck() if with_termlog: self.addons.add(termlog.TermLog(), termstatus.TermStatus()) self.addons.add(*addons.default_addons()) if with_dumper: self.addons.add(dumper.Dumper()) self.addons.add( keepserving.KeepServing(), readfile.ReadFileStdin(), self.errorcheck )