# # Copyright (C) 2006-2015 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. # include $(TOPDIR)/rules.mk PKG_NAME:=automake PKG_CPE_ID:=cpe:/a:gnu:automake PKG_VERSION:=1.15.1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@GNU/automake PKG_HASH:=af6ba39142220687c500f79b4aa2f181d9b24e4f8d8ec497cea4ba26c64bedaf include $(INCLUDE_DIR)/host-build.mk HOST_CONFIGURE_ARGS += \ --datarootdir=$(STAGING_DIR_HOST)/share \ --disable-silent-rules HOST_CONFIGURE_VARS += \ PERL="/usr/bin/env perl" \ am_cv_prog_PERL_ithreads=no define Host/Configure (cd $(HOST_BUILD_DIR); $(AM_TOOL_PATHS) STAGING_DIR="" ./bootstrap) $(call Host/Configure/Default) endef define Host/Install # remove old automake resources to avoid version conflicts rm -rf $(STAGING_DIR_HOST)/share/aclocal-[0-9]* rm -rf $(STAGING_DIR_HOST)/share/automake-[0-9]* $(MAKE) -C $(HOST_BUILD_DIR) install mv $(STAGING_DIR_HOST)/bin/aclocal $(STAGING_DIR_HOST)/bin/aclocal.real $(INSTALL_BIN) ./files/aclocal $(STAGING_DIR_HOST)/bin ln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.9 ln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.10 ln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.11 ln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.11.6 ln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.15 endef define Host/Clean -$(MAKE) -C $(HOST_BUILD_DIR) uninstall $(call Host/Clean/Default) endef $(eval $(call HostBuild)) git/iCE40/yosys/tree/backends/verilog/verilog_backend.h?id=1af1cebb64b5d8d3f0a66d01d05762a15b3bc0db'>treecommitdiffstats
path: root/backends/verilog/verilog_backend.h
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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *  
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *  
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 *  ---
 *
 *  A simple and straightforward verilog backend.
 *
 *  Note that RTLIL processes can't always be mapped easily to a Verilog
 *  process. Therefore this frontend should only be used to export a
 *  Verilog netlist (i.e. after the "proc" pass has converted all processes
 *  to logic networks and registers).
 *
 */

#ifndef VERILOG_BACKEND_H
#define VERILOG_BACKEND_H

#include "kernel/rtlil.h"
#include <stdio.h>

namespace VERILOG_BACKEND {
	void verilog_backend(FILE *f, std::vector<std::string> args, RTLIL::Design *design);
}

#endif