module a; wire [5:0]x; wire [3:0]y; assign y = (4)55; endmodule /cgit.css'/>
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path: root/backends/verilog/Makefile.inc
blob: c2dffef7a45e0fc772fbc6639d12baab36676b13 (plain) 
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OBJS += backends/verilog/verilog_backend.o
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-19 23:21:10 +0000