read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 select -assert-count 6 t:LUT2 select -assert-count 2 t:LUT3 select -assert-count 8 t:inpad select -assert-count 10 t:outpad select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D tmproxy Git repository'/>
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