read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 select -assert-count 6 t:LUT2 select -assert-count 2 t:LUT3 select -assert-count 8 t:inpad select -assert-count 10 t:outpad select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D tmproxy Git repository'/>
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path: root/libmproxy/proxy/modes/transparent_proxy.py
blob: 3fdda65606d1304e4659aaded8ed0a03372fbe17 (plain)
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from __future__ import (absolute_import, print_function, division)

from ... import platform
from ...exceptions import ProtocolException
from ...protocol import Layer, ServerConnectionMixin


class TransparentProxy(Layer, ServerConnectionMixin):

    def __init__(self, ctx):
        super(TransparentProxy, self).__init__(ctx)
        self.resolver = platform.resolver()

    def __call__(self):
        try:
            self.server_conn.address = self.resolver.original_addr(self.client_conn.connection)
        except Exception as e:
            raise ProtocolException("Transparent mode failure: %s" % repr(e))

        layer = self.ctx.next_layer(self)
        try:
            layer()
        finally:
            if self.server_conn:
                self.disconnect()