| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 | |
| | * | | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 | |
| | * | | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 2 | -0/+31 | |
| | |\ \ | ||||||
| | | * \ | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 2 | -0/+31 | |
| | | |\ \ | ||||||
| | | | * | | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 2 | -0/+31 | |
| | * | | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 | |
| | |/ / / | ||||||
| | * | | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 2 | -12/+1 | |
| | * | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int... | Clifford Wolf | 2019-06-07 | 4 | -3/+42 | |
| | |\ \ \ | ||||||
| | | * | | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 4 | -3/+42 | |
| * | | | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux | Eddie Hung | 2019-06-06 | 2 | -0/+41 | |
| |\ \ \ \ \ | | |_|_|/ | |/| | | | ||||||
| | * | | | | Fix and test for balanced case | Eddie Hung | 2019-06-06 | 2 | -0/+41 | |
| * | | | | | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux | Eddie Hung | 2019-06-06 | 15 | -0/+512 | |
| |\| | | | | ||||||
| | * | | | | Fix warnings | Eddie Hung | 2019-06-06 | 2 | -3/+3 | |
| | * | | | | Support cascading $pmux.A with $mux.A and $mux.B | Eddie Hung | 2019-06-06 | 2 | -0/+40 | |
| | * | | | | Add non exclusive test | Eddie Hung | 2019-06-06 | 2 | -0/+56 | |
| | * | | | | One more and tidy up | Eddie Hung | 2019-06-06 | 2 | -6/+28 | |
| | * | | | | Add a few more special case tests | Eddie Hung | 2019-06-06 | 2 | -0/+51 | |
| | * | | | | Add tests, fix for != | Eddie Hung | 2019-06-06 | 2 | -0/+78 | |
| | |/ / / | ||||||
| | * | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ... | Maciej Kurc | 2019-06-04 | 4 | -0/+46 | |
| | * | | | Added tests for attributes | Maciej Kurc | 2019-06-03 | 9 | -0/+219 | |
| | |/ / | ||||||
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-03 | 1 | -0/+4 | |
| |\| | | ||||||
| | * | | Merge pull request #1049 from YosysHQ/clifford/fix1047 | Clifford Wolf | 2019-05-28 | 1 | -0/+4 | |
| | |\ \ | ||||||
| | | * | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 | Clifford Wolf | 2019-05-28 | 1 | -0/+4 | |
| * | | | | Rename to #23 | Eddie Hung | 2019-05-29 | 1 | -3/+3 | |
| * | | | | Add abc_test024 | Eddie Hung | 2019-05-29 | 1 | -6/+19 | |
| * | | | | Add abc9_test022 | Eddie Hung | 2019-05-28 | 1 | -0/+22 | |
| * | | | | From master | Eddie Hung | 2019-05-28 | 1 | -1/+1 | |
| * | | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-28 | 3 | -27/+84 | |
| |\| | | | ||||||
| | * | | | Add actual wandwor test that is part of "make test" | Clifford Wolf | 2019-05-28 | 2 | -33/+36 | |
| | * | | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 2 | -0/+76 | |
| | |\| | | ||||||
| | | * | | Fix init | Eddie Hung | 2019-05-24 | 1 | -27/+27 | |
| | | * | | Fix typos | Eddie Hung | 2019-05-24 | 1 | -6/+6 | |
| | | * | | Add more tests | Eddie Hung | 2019-05-24 | 2 | -20/+41 | |
| | | * | | Call proc | Eddie Hung | 2019-05-24 | 1 | -1/+1 | |
| | | * | | Fix duplicate driver | Eddie Hung | 2019-05-24 | 1 | -15/+15 | |
| | * | | | reformat wand/wor test | Stefan Biereigel | 2019-05-27 | 1 | -22/+21 | |
| | * | | | remove port direction workaround from test case | Stefan Biereigel | 2019-05-27 | 1 | -2/+1 | |
| | * | | | add simple test case for wand/wor | Stefan Biereigel | 2019-05-23 | 1 | -0/+35 | |
| * | | | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux | Eddie Hung | 2019-05-23 | 2 | -0/+55 | |
| |\ \ \ \ | | |/ / | |/| | | ||||||
| | * | | | Add opt_rmdff tests | Eddie Hung | 2019-05-23 | 2 | -0/+55 | |
| | |/ / | ||||||
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 10 | -5/+225 | |
| |\| | | ||||||
| | * | | Added tests for Verilog frontent for attributes on parameters and localparams | Maciej Kurc | 2019-05-16 | 2 | -0/+22 | |
| | * | | Add test case from #997 | Clifford Wolf | 2019-05-07 | 1 | -0/+12 | |
| | * | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -0/+86 | |
| | |\ \ | ||||||
| | | * | | Improve tests/various/specify.ys | Clifford Wolf | 2019-05-06 | 1 | -2/+32 | |
| | | * | | More testing | Eddie Hung | 2019-05-03 | 2 | -2/+5 | |
| | | * | | Fix spacing | Eddie Hung | 2019-05-03 | 1 | -6/+6 | |
| | | * | | Add quick-and-dirty specify tests | Eddie Hung | 2019-05-03 | 2 | -0/+53 | |
| | * | | | Merge pull request #975 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-05-06 | 1 | -0/+25 | |
| | |\ \ \ | ||||||
| | | * | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 | Clifford Wolf | 2019-05-06 | 6 | -5/+60 | |
| | | |\| | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |