iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	changed file() to open() in python scripts	Clifford Wolf	2015-05-11	4	-11/+11
*	Added "pmuxtree" command	Clifford Wolf	2015-04-07	1	-0/+51
*	fix for python 2.6.6	Clifford Wolf	2015-03-20	3	-165/+172
*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14	1	-2/+2
*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	2	-15/+13
*	Added $meminit test case	Clifford Wolf	2015-02-14	1	-0/+30
*	Some test related fixes	Clifford Wolf	2015-02-12	4	-151/+1
*	Bugfix in resource sharing test	Clifford Wolf	2015-01-27	1	-1/+1
*	Refactoring of memory_bram and xilinx brams	Clifford Wolf	2015-01-18	2	-2/+4
*	improvements in muxtree/select_leaves test	Clifford Wolf	2015-01-18	1	-2/+5
*	Improvements in opt_muxtree	Clifford Wolf	2015-01-18	1	-0/+8
*	Tiny fix in vcdcd.pl	Clifford Wolf	2015-01-13	1	-2/+2
*	Added memory_bram "shuffle_enable" feature	Clifford Wolf	2015-01-04	1	-0/+4
*	Added "memory -bram"	Clifford Wolf	2015-01-03	1	-1/+1
*	Added memory_bram 'or_next_if_better' feature	Clifford Wolf	2015-01-03	1	-3/+6
*	memory_bram transp support	Clifford Wolf	2015-01-03	1	-42/+66
*	Progress in memory_bram	Clifford Wolf	2015-01-03	3	-14/+17
*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02	1	-1/+1
*	Fixes and improvements in bram test	Clifford Wolf	2015-01-02	1	-20/+8
*	Progress in bram testbench	Clifford Wolf	2015-01-02	1	-11/+28
*	Progress in memory_bram	Clifford Wolf	2015-01-02	3	-13/+11
*	Progress in memory_bram	Clifford Wolf	2015-01-02	3	-22/+32
*	Progress in bram testbench	Clifford Wolf	2015-01-01	3	-42/+184
*	Bram testbench (incomplete)	Clifford Wolf	2015-01-01	2	-0/+120
*	Added "yosys -qq" to also quiet warning messages	Clifford Wolf	2014-11-09	1	-1/+1
*	Added support for task and function args in parentheses	Clifford Wolf	2014-10-27	1	-1/+35
*	Added "synth" command	Clifford Wolf	2014-09-14	1	-2/+2
*	Fixed autotest for non-basename arguments	Clifford Wolf	2014-09-06	1	-0/+3
*	Added tests/various/constmsk_test.ys	Clifford Wolf	2014-09-04	3	-0/+68
*	Added autotest -e (do not use -noexpr on write_verilog)	Clifford Wolf	2014-08-30	3	-4/+6
*	Cosmetic changes to FSM tests	Clifford Wolf	2014-08-21	1	-1/+1
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14	1	-1/+2
*	Added test_verific mode to tests/fsm/generate.py	Clifford Wolf	2014-08-12	1	-7/+17
*	Added multi-dim memory test (requires iverilog git head)	Clifford Wolf	2014-08-12	1	-0/+11
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10	1	-7/+22
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09	1	-1/+2
*	Improved FSM tests	Clifford Wolf	2014-08-08	3	-2/+4
*	Added FSM test bench	Clifford Wolf	2014-08-08	2	-0/+113
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	1	-0/+63
*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05	1	-0/+13
*	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03	3	-2/+3
*	Consolidated hana test benches into fewer files	Clifford Wolf	2014-08-01	175	-1332/+1622
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	1	-2/+5
*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30	6	-12/+29
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	1	-1/+1
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	1	-0/+57
*	Improvements in tests/vloghtb	Clifford Wolf	2014-07-28	2	-11/+17
*	Added techmap -extern	Clifford Wolf	2014-07-27	2	-1/+28
*	Added tests/various/.gitignore	Clifford Wolf	2014-07-26	1	-0/+1
*	Added tests/various/submod_extract.ys	Clifford Wolf	2014-07-26	2	-0/+27