| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+31 |
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| | * | Add multiple driver testcase | Eddie Hung | 2019-11-27 | 1 | -0/+31 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 2 | -0/+82 |
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| | * \ | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 1 | -0/+69 |
| | |\ \ | | | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder | ||||
| | | * | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| | | * | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 |
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| | | * | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 |
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| | * | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 1 | -0/+13 |
| | |\ \ \ | | | | | | | | | | | opt_share: Fix handling of fine cells. | ||||
| | | * | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+13 |
| | | |/ / | | | | | | | | | | | | | Fixes #1525. | ||||
| * | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -9/+0 |
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| | * | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 |
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| * | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -2/+23 |
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| | * | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -2/+5 |
| | | | | | | | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. | ||||
| | * | | Fix wire width | Eddie Hung | 2019-11-26 | 1 | -2/+2 |
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| | * | | Add testcase where \init is copied | Eddie Hung | 2019-11-25 | 1 | -0/+18 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 5 | -13/+24 |
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| | * | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -5/+16 |
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| | * | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 4 | -8/+8 |
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| * | | | Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff | Eddie Hung | 2019-11-23 | 3 | -11/+11 |
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| | * | | | Another sloppy mistake! | Eddie Hung | 2019-11-21 | 1 | -1/+1 |
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| | * | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff | Eddie Hung | 2019-11-21 | 3 | -4/+9 |
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| | * | | | | async2sync -> clk2fflogic | Eddie Hung | 2019-11-21 | 1 | -1/+1 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -3/+0 |
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| | * | | | | Remove redundant flatten | Eddie Hung | 2019-11-22 | 1 | -2/+0 |
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| | * | | | | Stray dump | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+28 |
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| | * | | | | Add another test with constant driver | Eddie Hung | 2019-11-22 | 1 | -0/+28 |
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| * | | | | | Add testcase for signal used as part input part output | Eddie Hung | 2019-11-22 | 1 | -0/+5 |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+25 |
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| | * | | | | Cleanup spacing | Eddie Hung | 2019-11-22 | 1 | -2/+1 |
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| | * | | | | Add testcase | Eddie Hung | 2019-11-22 | 1 | -0/+26 |
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| * | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -1/+63 |
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| | * | | | Merge pull request #1511 from YosysHQ/dave/always | Clifford Wolf | 2019-11-22 | 1 | -0/+63 |
| | |\ \ \ | | | | | | | | | | | sv: Error checking for always_comb, always_latch and always_ff | ||||
| | | * | | | sv: Add tests for SV always types | David Shah | 2019-11-21 | 1 | -0/+63 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | | gowin: Remove show command from tests. | Marcin Kościelnicki | 2019-11-22 | 1 | -1/+0 |
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| * | | | | Missing endmodule | Eddie Hung | 2019-11-22 | 1 | -0/+1 |
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| * | | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 3 | -3/+37 |
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| | * | | | Add a equiv test too | Eddie Hung | 2019-11-19 | 2 | -0/+23 |
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| | * | | | Add two tests | Eddie Hung | 2019-11-19 | 1 | -0/+12 |
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| * | / | Add test | Eddie Hung | 2019-11-21 | 1 | -1/+6 |
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| * | | Add multi clock test | Eddie Hung | 2019-11-20 | 1 | -0/+5 |
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| * | Merge pull request #1449 from pepijndevos/gowin | Clifford Wolf | 2019-11-19 | 12 | -0/+248 |
| |\ | | | | | Improvements for gowin support | ||||
| | * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-16 | 5 | -17/+34 |
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| | * | | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 1 | -0/+11 |
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| | * | | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -7/+10 |
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| | * | | don't cound exact luts in big muxes; futile and fragile | Pepijn de Vos | 2019-10-30 | 1 | -3/+0 |
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| | * | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 1 | -0/+13 |
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| | * | | do not use wide luts in testcase | Pepijn de Vos | 2019-10-28 | 1 | -3/+3 |
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| | * | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -2/+2 |
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| | * | | Add some tests | Pepijn de Vos | 2019-10-21 | 10 | -0/+224 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram | ||||
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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