| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 1 | -0/+13 | |
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| | | * | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+13 | |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -9/+0 | |
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| | * | | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 | |
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| * | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -2/+23 | |
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| | * | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -2/+5 | |
| | * | | | Fix wire width | Eddie Hung | 2019-11-26 | 1 | -2/+2 | |
| | * | | | Add testcase where \init is copied | Eddie Hung | 2019-11-25 | 1 | -0/+18 | |
| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 5 | -13/+24 | |
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| | * | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -5/+16 | |
| | * | | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 4 | -8/+8 | |
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| * | | | Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff | Eddie Hung | 2019-11-23 | 3 | -11/+11 | |
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| | * | | | Another sloppy mistake! | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
| | * | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff | Eddie Hung | 2019-11-21 | 3 | -4/+9 | |
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| | * | | | | async2sync -> clk2fflogic | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -3/+0 | |
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| | * | | | | Remove redundant flatten | Eddie Hung | 2019-11-22 | 1 | -2/+0 | |
| | * | | | | Stray dump | Eddie Hung | 2019-11-22 | 1 | -1/+0 | |
| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+28 | |
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| | * | | | | Add another test with constant driver | Eddie Hung | 2019-11-22 | 1 | -0/+28 | |
| * | | | | | Add testcase for signal used as part input part output | Eddie Hung | 2019-11-22 | 1 | -0/+5 | |
| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+25 | |
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| | * | | | | Cleanup spacing | Eddie Hung | 2019-11-22 | 1 | -2/+1 | |
| | * | | | | Add testcase | Eddie Hung | 2019-11-22 | 1 | -0/+26 | |
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| * | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -1/+63 | |
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| | * | | | Merge pull request #1511 from YosysHQ/dave/always | Clifford Wolf | 2019-11-22 | 1 | -0/+63 | |
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| | | * | | | sv: Add tests for SV always types | David Shah | 2019-11-21 | 1 | -0/+63 | |
| | * | | | | gowin: Remove show command from tests. | Marcin Kościelnicki | 2019-11-22 | 1 | -1/+0 | |
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| * | | | | Missing endmodule | Eddie Hung | 2019-11-22 | 1 | -0/+1 | |
| * | | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 3 | -3/+37 | |
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| | * | | | Add a equiv test too | Eddie Hung | 2019-11-19 | 2 | -0/+23 | |
| | * | | | Add two tests | Eddie Hung | 2019-11-19 | 1 | -0/+12 | |
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| * | / | Add test | Eddie Hung | 2019-11-21 | 1 | -1/+6 | |
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| * | | Add multi clock test | Eddie Hung | 2019-11-20 | 1 | -0/+5 | |
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| * | Merge pull request #1449 from pepijndevos/gowin | Clifford Wolf | 2019-11-19 | 12 | -0/+248 | |
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| | * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-16 | 5 | -17/+34 | |
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| | * | | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 1 | -0/+11 | |
| | * | | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -7/+10 | |
| | * | | don't cound exact luts in big muxes; futile and fragile | Pepijn de Vos | 2019-10-30 | 1 | -3/+0 | |
| | * | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 1 | -0/+13 | |
| | * | | do not use wide luts in testcase | Pepijn de Vos | 2019-10-28 | 1 | -3/+3 | |
| | * | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -2/+2 | |
| | * | | Add some tests | Pepijn de Vos | 2019-10-21 | 10 | -0/+224 | |
| * | | | Fix #1462, #1480. | Marcin Kościelnicki | 2019-11-19 | 2 | -0/+29 | |
| * | | | Fix #1496. | Marcin Kościelnicki | 2019-11-18 | 1 | -0/+13 | |
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| * | | Fixed tests | Miodrag Milanovic | 2019-11-11 | 5 | -17/+34 | |
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| * | fixed error | Miodrag Milanovic | 2019-10-18 | 1 | -1/+1 | |
| * | Unify verilog style | Miodrag Milanovic | 2019-10-18 | 11 | -191/+157 | |
| * | Common memory test now shared | Miodrag Milanovic | 2019-10-18 | 10 | -89/+5 | |
| * | Remove not needed tests | Miodrag Milanovic | 2019-10-18 | 4 | -52/+0 | |
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index : iCE40/yosys | |
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