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* ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
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* ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
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* ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-5/+305
| | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+6
| | | | LSE/Synplify use case insensitive matching.
* ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-20/+179
| | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* ice40: remove impossible test.whitequark2020-02-061-15/+0
| | | | | | iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM, essentially a duplicate of the "dpram.ys" test.
* shiftx2mux: fix select out of boundsEddie Hung2020-02-052-1/+12
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* Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-051-0/+49
|\ | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-2874-149/+1770
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| * | Add testcaseEddie Hung2019-12-131-0/+49
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* | | Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-053-5/+115
|\ \ \ | | | | | | | | techmap LSB-first for compatible $shift/$shiftx cells
| * \ \ Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0517-30/+474
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| * | | | Update tests with reduced areaEddie Hung2020-01-212-6/+6
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| * | | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-211-4/+4
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| * | | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-211-0/+110
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* | | | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+21
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* | | | Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-051-0/+66
|\ \ \ \ | | | | | | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
| * | | | More rigorous testEddie Hung2020-01-161-7/+34
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| * | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-151-0/+39
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* | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-034-4/+84
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* | | | | sv: More tests for wildcard port connectionsDavid Shah2020-02-021-0/+57
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-0/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | sv: Add tests for wildcard port connectionsDavid Shah2020-02-021-0/+56
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1647 from YosysHQ/dave/sprintfDavid Shah2020-02-021-0/+12
|\ \ \ \ \ | | | | | | | | | | | | ast: Add support for $sformatf system function
| * | | | | ast: Add support for $sformatf system functionDavid Shah2020-01-191-0/+12
| | |/ / / | |/| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1559 from YosysHQ/efinix_test_fixMiodrag Milanović2020-01-291-1/+1
|\ \ \ \ \ | | | | | | | | | | | | Fix for non-deterministic test
| * | | | | Updated test to use assert-maxMiodrag Milanovic2020-01-281-1/+1
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| * | | | | Fix for non-deterministic testMiodrag Milanovic2019-12-071-1/+1
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* | | | | | Add "help -all" and "help -celltypes" sanity testEddie Hung2020-01-281-0/+2
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* | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-282-0/+102
|\ \ \ \ \ | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| * | | | | Import tests from #1628Eddie Hung2020-01-272-0/+102
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* | | | | | Merge pull request #1567 from YosysHQ/eddie/sat_init_warningClaire Wolf2020-01-281-0/+11
|\ \ \ \ \ \ | | | | | | | | | | | | | | sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
| * | | | | | Even more obvious testcaseEddie Hung2019-12-111-6/+5
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| * | | | | | Make testcase clearer with \o having its own initEddie Hung2019-12-111-0/+2
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| * | | | | | Add test: 'Warning: ignoring initial value on non-register: \o'Eddie Hung2019-12-111-0/+10
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* | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+5
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | synth_xilinx: error out if tristate without '-iopad'
| * | | | | Add testEddie Hung2019-12-121-0/+5
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* | | | | Merge pull request #1619 from YosysHQ/eddie/abc9_refactorEddie Hung2020-01-273-0/+60
|\ \ \ \ \ | | | | | | | | | | | | Refactor `abc9` pass
| * | | | | simple_abc9 tests to discard whitebox before write for simEddie Hung2020-01-232-2/+3
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| * | | | | Test for (* keep *)-ed abc9_box_idEddie Hung2020-01-231-0/+16
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| * | | | | abc_box_id -> abc9_box_id in testEddie Hung2020-01-231-1/+1
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| * | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-215-0/+24
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| * | | | | write_xaiger: fix for (* keep *) on flop outputEddie Hung2020-01-211-0/+15
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| * | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-0/+13
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-146-9/+29
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| * | | | | | abc9: respect (* keep *) on cellsEddie Hung2020-01-131-0/+15
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| * | | | | | write_xaiger: add support and test for (* keep *) on wiresEddie Hung2020-01-131-0/+13
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* | | | | | | Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warningsEddie Hung2020-01-271-23/+4
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
| * | | | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-241-23/+4
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* | | | | | | simple_abc9 tests to discard whitebox before write for simEddie Hung2020-01-232-2/+3
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