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* Remove split_shiftx testsEddie Hung2019-04-262-139/+0
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* Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7muxEddie Hung2019-04-252-0/+139
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| * Add testEddie Hung2019-04-252-0/+139
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* | Remove topo sort no-loop assertion, with testEddie Hung2019-04-243-1/+76
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* | Fix abc9 with (* keep *) wiresEddie Hung2019-04-231-0/+38
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-224-0/+110
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| * Updaye pmux2shiftx testClifford Wolf2019-04-221-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #909 from zachjs/masterClifford Wolf2019-04-222-0/+48
| |\ | | | | | | support repeat loops with constant repeat counts outside of constant functions
| | * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-092-0/+48
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| * | Merge pull request #944 from YosysHQ/clifford/pmux2shiftxClifford Wolf2019-04-222-0/+62
| |\ \ | | | | | | | | Add pmux2shiftx command
| | * | Improve "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improvements in "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improvements in pmux2shiftxClifford Wolf2019-04-202-20/+30
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add test for pmux2shiftxClifford Wolf2019-04-202-0/+52
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge remote-tracking branch 'origin/clifford/libwb' into xaigEddie Hung2019-04-212-2/+3
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| * | | Fix testsClifford Wolf2019-04-212-2/+3
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-202-0/+8
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| * | Add tests/aiger/.gitignoreClifford Wolf2019-04-191-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add retime testEddie Hung2019-04-051-0/+6
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* | Select to find union of both sets on stackEddie Hung2019-04-191-1/+1
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* | Re-enable partsel.v testEddie Hung2019-04-161-1/+0
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-151-3/+2
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| * | Revert "Recognise default entry in case even if all cases covered (fix for ↵Eddie Hung2019-04-151-3/+2
| | | | | | | | | | | | #931)"
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-121-2/+3
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| * | Add default entry to testcaseEddie Hung2019-04-111-2/+3
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* | Merge branch 'master' into xaigEddie Hung2019-04-0814-5/+737
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| * Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
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| * Liberty file parser now accepts superfluous ;Niels Moseley2019-03-273-2/+97
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| * Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-0/+22
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Updated the liberty parser to accept [A:B] ranges (AST has not been ↵Niels Moseley2019-03-246-0/+541
| | | | | | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
| * Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-1911-31/+175
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| | * fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
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| | * Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
| | | | | | | | | | | | Mark dff_init.v as expected to fail since it uses "initial value".
| | * Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add "write_verilog -siminit"Clifford Wolf2019-02-281-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-253-3/+1
| | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
| * | One more merge conflictEddie Hung2019-02-171-6/+1
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| * | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-175-8/+97
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* | \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-265-1/+94
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| * | | Merge pull request #812 from ucb-bar/arrayhierarchyfixesClifford Wolf2019-02-242-1/+68
| |\ \ \ | | | | | | | | | | Define basic_cell_type() function and use it to derive the cell type …
| | * | | Address requested changes - don't require non-$ name.Jim Lawson2019-02-222-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types.
| | * | | Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-192-1/+65
| | | | | | | | | | | | | | | | | | | | Add simple test.
| * | | | Merge pull request #824 from litghost/fix_reduce_on_ffClifford Wolf2019-02-242-0/+24
| |\ \ \ \ | | | | | | | | | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter.
| | * | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter.Keith Rothman2019-02-222-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | | | | Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
| |/ / / / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Uncomment out more testsEddie Hung2019-02-261-25/+39
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* | | | | Enable two inout testsEddie Hung2019-02-261-16/+14
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* | | | | Add broken testcasesEddie Hung2019-02-251-0/+46
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* | | | | Revert "tests/simple to also do LUT synth"Eddie Hung2019-02-211-1/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit 5994382a20a0b7e890d22d032eecb39b61e0b3ce.