iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	verilog: use derived module info to elaborate cell connections	Zachary Snow	2021-10-25	1	-0/+6
	- Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change