| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | genrtlil: fix mux2rtlil generated wire signedness | Zachary Snow | 2020-12-22 | 1 | -4/+9 |
| * | Sign extend port connections where necessary | Zachary Snow | 2020-12-18 | 1 | -0/+76 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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