| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added $div and $mod technology mapping | Clifford Wolf | 2013-08-09 | 1 | -3/+3 |
| * | Major redesign of expr width/sign detecion (verilog/ast frontend) | Clifford Wolf | 2013-07-09 | 1 | -2/+2 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+164 |
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index : iCE40/yosys | |
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