iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
*	Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵	Udi Finkelstein	2018-10-25	13	-0/+64
	parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.