iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	tests/bram: Do not generate write address collisions.	Marcelina Kościelnicka	2021-03-08	1	-5/+23
*	Added support for (single-clock) transparent memories to bram tests	Clifford Wolf	2016-11-01	2	-10/+23
*	Fixed "make test" for git head of iverilog	Clifford Wolf	2016-10-11	1	-1/+1
*	Add optional SEED=n command line option to Makefile, and -S n command line op...	Eric Smith	2016-09-22	2	-4/+32
*	Switched to Python 3	Clifford Wolf	2015-08-22	2	-5/+2
*	changed file() to open() in python scripts	Clifford Wolf	2015-05-11	1	-4/+4
*	Refactoring of memory_bram and xilinx brams	Clifford Wolf	2015-01-18	1	-2/+2
*	Added memory_bram "shuffle_enable" feature	Clifford Wolf	2015-01-04	1	-0/+4
*	Added "memory -bram"	Clifford Wolf	2015-01-03	1	-1/+1
*	Added memory_bram 'or_next_if_better' feature	Clifford Wolf	2015-01-03	1	-3/+6
*	memory_bram transp support	Clifford Wolf	2015-01-03	1	-42/+66
*	Progress in memory_bram	Clifford Wolf	2015-01-03	3	-14/+17
*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02	1	-1/+1
*	Fixes and improvements in bram test	Clifford Wolf	2015-01-02	1	-20/+8
*	Progress in bram testbench	Clifford Wolf	2015-01-02	1	-11/+28
*	Progress in memory_bram	Clifford Wolf	2015-01-02	3	-13/+11
*	Progress in memory_bram	Clifford Wolf	2015-01-02	3	-22/+32
*	Progress in bram testbench	Clifford Wolf	2015-01-01	3	-42/+184
*	Bram testbench (incomplete)	Clifford Wolf	2015-01-01	2	-0/+120