iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	1	-8/+8
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	intel_alm: Add IO buffer insertion	gatecat	2021-05-15	1	-6/+6
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	techmap/shift_shiftx: Remove the "shiftx2mux" special path.	Marcelina Kościelnicka	2020-08-20	1	-2/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
*	intel_alm: increase abc9 -W	Dan Ravensloft	2020-07-26	1	-6/+6
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*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	1	-6/+4
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*	intel_alm: add Cyclone 10 GX tests	Dan Ravensloft	2020-07-05	1	-1/+45
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-0/+45
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).