| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | memory_bram: Reuse extract_rdff helper for make_outreg. | Marcelina Kościelnicka | 2021-05-25 | 1 | -6/+4 |
| | | | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later. | ||||
| * | intel_alm: Add global buffer insertion | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | intel_alm: Add IO buffer insertion | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | intel_alm: add Cyclone 10 GX tests | Dan Ravensloft | 2020-07-05 | 1 | -1/+22 |
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| * | intel_alm: direct LUTRAM cell instantiation | Dan Ravensloft | 2020-05-07 | 1 | -0/+20 |
| By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus. | |||||
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index : iCE40/yosys | |
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