| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel_alm: Add global buffer insertion | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | intel_alm: Add IO buffer insertion | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Replace opt_rmdff with opt_dff. | Marcelina Kościelnicka | 2020-08-07 | 1 | -5/+7 |
| | | |||||
| * | intel_alm: add Cyclone 10 GX tests | Dan Ravensloft | 2020-07-05 | 1 | -0/+22 |
| | | |||||
| * | synth_intel_alm: Use dfflegalize. | Marcelina Kościelnicka | 2020-07-04 | 1 | -1/+1 |
| | | |||||
| * | Improve MISTRAL_FF specify rules | Dan Ravensloft | 2020-07-04 | 1 | -1/+2 |
| | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com> | ||||
| * | tests: update fsm.ys resource count | Eddie Hung | 2020-07-04 | 1 | -4/+4 |
| | | | | | | Suspect it is to do with map/set ordering in techmap; should be fixed by #1862? | ||||
| * | intel_alm: fix DFFE matching | Dan Ravensloft | 2020-06-11 | 1 | -2/+3 |
| | | |||||
| * | synth_intel_alm: alternative synthesis for Intel FPGAs | Dan Ravensloft | 2020-04-15 | 1 | -0/+18 |
| By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6). | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |