| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 1 | -42/+0 |
| | | |||||
| * | hierarchy - proc reorder | Miodrag Milanovic | 2019-10-18 | 1 | -4/+4 |
| | | |||||
| * | check muxes per type | Miodrag Milanovic | 2019-10-04 | 1 | -7/+37 |
| | | |||||
| * | Add new tests for Anlogic architecture | SergeyDegtyar | 2019-09-23 | 1 | -0/+12 |
| Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |