| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 1 | -33/+0 |
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| * | hierarchy - proc reorder | Miodrag Milanovic | 2019-10-18 | 1 | -3/+3 |
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| * | split latches into separate checks | Miodrag Milanovic | 2019-10-04 | 1 | -7/+24 |
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| * | Add new tests for Anlogic architecture | SergeyDegtyar | 2019-09-23 | 1 | -0/+16 |
| Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. | |||||
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index : iCE40/yosys | |
| [no description] |
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