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| * | | | | | | | | | | | | | | | | generated by cgit v1.2.3 (git 2.25.1) at 2025-10-24 23:55:16 +0000 6e2b772b05'>Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
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| * | | | | | | | | | | | | | | | | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
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| * | | | | | | | | | | | | | | | | Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
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| * | | | | | | | | | | | | | | | | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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| * | | | | | | | | | | | | | | | | Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
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* | | | | | | | | | | | | | | | | Add unconditional match blocks for force RAMEddie Hung2019-12-161-4/+36
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* | | | | | | | | | | | | | | | | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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* | | | | | | | | | | | | | | | | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-4/+4
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* | | | | | | | | | | | | | | | | Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-18/+12
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* | | | | | | | | | | | | | | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+19
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* | | | | | | | | | | | | | | | | Merge pull request #1533 from dh73/bram_xilinxEddie Hung2019-12-131-6/+9
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
| * | | | | | | | | | | | | | | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-5/+5
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| * | | | | | | | | | | | | | | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-121-2/+2
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| * | | | | | | | | | | | | | | | Merge https://github.com/YosysHQ/yosys into bram_xilinxDiego H2019-12-1220-775/+1170
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| * | | | | | | | | | | | | | | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
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* | | | | | | | | | | | | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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* | | | | | | | | | | | | | | Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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* | | | | | | | | | | | | | | Merge pull request #1564 from ZirconiumX/intel_housekeepingDavid Shah2019-12-118-6/+6
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| * | | | | | | | | | | | | | | synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
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| * | | | | | | | | | | | | | | synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
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* | | | | | | | | | | | | | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-094-20/+22
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / |/| | | | | | | | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| * | | | | | | | | | | | | | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
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| * | | | | | | | | | | | | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-1/+1
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| * | | | | | | | | | | | | | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-092-19/+1
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| * | | | | | | | | | | | | | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
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| * | | | | | | | | | | | | | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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* | | | | | | | | | | | | | | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1225.
* | | | | | | | | | | | | | | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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* | | | | | | | | | | | | | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-032-112/+270
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gowin: add and test DFF init values
| * | | | | | | | | | | | | | Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
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| * | | | | | | | | | | | | | attempt to fix formattingPepijn de Vos2019-11-251-154/+154
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| * | | | | | | | | | | | | | gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
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* | | | | | | | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
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* | | | | | | | | | | | | | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
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* | | | | | | | | | | | | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
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* | | | | | | | | | | | | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-251-2/+6
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* | | | | | | | | | | / coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
| |_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at>
* | | | | | | | | | | gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
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* | | | | | | | | | Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-198-43/+547
|\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | Improvements for gowin support
| * | | | | | | | | | Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware does not actually support it. In reality it is always initialised to its reset value.
| * | | | | | | | | | add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
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| * | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-164-15/+439
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| * | | | | | | | | | | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
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| * | | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1122-22988/+30572
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| * | | | | | | | | | | | fix wide lutsPepijn de Vos2019-11-061-12/+12
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| * | | | | | | | | | | | add IOBUFPepijn de Vos2019-10-282-1/+10
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| * | | | | | | | | | | | add tristate buffer and testPepijn de Vos2019-10-282-2/+8
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generated by cgit v1.2.3 (git 2.25.1) at 2025-10-24 23:55:16 +0000