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authorEddie Hung <eddie@fpgeh.com>2019-12-13 08:54:19 -0800
committerEddie Hung <eddie@fpgeh.com>2019-12-13 08:54:19 -0800
commitd6514fc2e13976b15be396f413b046deb6f0c9fa (patch)
treed13e5ff67e37c8fed027f9612aea213c90f9a2e1 /techlibs
parentd0ee4cd88f1f966c194fdc60e47ef67944882afb (diff)
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RAM64M8 to also have [5:0] for address
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/xilinx/cells_sim.v16
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 56eb782c6..f9ce496ff 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -1230,14 +1230,14 @@ module RAM64M8 (
output DOF,
output DOG,
output DOH,
- input [4:0] ADDRA,
- input [4:0] ADDRB,
- input [4:0] ADDRC,
- input [4:0] ADDRD,
- input [4:0] ADDRE,
- input [4:0] ADDRF,
- input [4:0] ADDRG,
- input [4:0] ADDRH,
+ input [5:0] ADDRA,
+ input [5:0] ADDRB,
+ input [5:0] ADDRC,
+ input [5:0] ADDRD,
+ input [5:0] ADDRE,
+ input [5:0] ADDRF,
+ input [5:0] ADDRG,
+ input [5:0] ADDRH,
input DIA,
input DIB,
input DIC,