Commit message (Expand) | Author | Age | Files | Lines | |
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* | Add RAM32X6SDP and RAM64X3SDP modes | Eddie Hung | 2019-12-12 | 2 | -8/+120 |
* | Fix RAM64M model to have 6 bit address bus | Eddie Hung | 2019-12-12 | 1 | -4/+4 |
* | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 2 | -0/+168 |
* | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 |
* | Fix bitwidth mismatch; suppresses iverilog warning | Eddie Hung | 2019-12-11 | 1 | -4/+4 |
* | Merge pull request #1564 from ZirconiumX/intel_housekeeping | David Shah | 2019-12-11 | 8 | -6/+6 |
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| * | synth_intel: a10gx -> arria10gx | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 |
| * | synth_intel: cyclone10 -> cyclone10lp | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 |
* | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 4 | -20/+22 |
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| * | ice40_opt to restore attributes/name when unwrapping | Eddie Hung | 2019-12-09 | 1 | -0/+15 |
| * | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 1 | -1/+1 |
| * | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 2 | -19/+1 |
| * | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve | Eddie Hung | 2019-12-03 | 1 | -1/+1 |
| * | ice40_opt to ignore (* keep *) -ed cells | Eddie Hung | 2019-12-03 | 1 | -0/+5 |
* | | -22988/+30572 | ||||
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| * | | | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -12/+12 |
| * | | | add IOBUF | Pepijn de Vos | 2019-10-28 | 2 | -1/+10 |
| * | | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 2 | -2/+8 |
| * | | | More formatting | Pepijn de Vos | 2019-10-28 | 1 | -55/+49 |
| * | | | really really fix formatting maybe | Pepijn de Vos | 2019-10-28 | 1 | -41/+41 |
| * | | | undo formatting fuckup | Pepijn de Vos | 2019-10-28 | 1 | -25/+25 |
| * | | | add wide luts | Pepijn de Vos | 2019-10-28 | 3 | -36/+119 |
| * | | | add 32-bit BRAM and byte-enables | Pepijn de Vos | 2019-10-28 | 2 | -4/+25 |
| * | | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -11/+11 |
| * | | | add a few more missing dff | Pepijn de Vos | 2019-10-21 | 1 | -7/+16 |
| * | | | add negedge DFF | Pepijn de Vos | 2019-10-21 | 2 | -15/+139 |
| * | | | use ADDSUB ALU mode to remove inverters | Pepijn de Vos | 2019-10-21 | 2 | -7/+77 |
| * | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-10-21 | 58 | -1315/+24105 |
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| * | | | | remove duplicate DFFR | Pepijn de Vos | 2019-10-16 | 1 | -10/+0 |
| * | | | | Revert "add MUX support" | Pepijn de Vos | 2019-09-06 | 3 | -17/+0 |
| * | | | | fix BRAM width and init | Pepijn de Vos | 2019-09-06 | 2 | -12/+28 |
| * | | | | add more DFF to sim lib | Pepijn de Vos | 2019-09-06 | 2 | -6/+111 |
| * | | | | WIP aditional DFF primitives | Pepijn de Vos | 2019-09-05 | 2 | -1/+48 |