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* Merge pull request #941 from Wren6991/sim_lib_io_clkeClifford Wolf2019-04-221-10/+19
|\ | | | | ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
| * ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵Luke Wren2019-04-211-10/+19
| | | | | | | | experiments
* | Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-masterClifford Wolf2019-04-2210-10/+458
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| * | GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flowDiego2019-04-1210-11/+459
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* | Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #916 from YosysHQ/map_cells_before_map_lutsClifford Wolf2019-04-221-10/+10
|\ \ | | | | | | synth_xilinx to map_cells before map_luts
| * \ Merge branch 'master' into map_cells_before_map_lutsEddie Hung2019-04-216-59/+85
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| * | | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
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| * | | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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* | | | Merge pull request #911 from mmicko/gowin-nobramClifford Wolf2019-04-221-1/+1
|\ \ \ \ | |_|/ / |/| | | Make nobram false by default for gowin
| * | | Make nobram false by default for gowinMiodrag Milanovic2019-04-021-1/+1
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* | | Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-1811-15/+15
| | | | | | | | | | | | This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.
* | | Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-184-44/+69
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| * | Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
| |\ \ | | | | | | | | Add additional cells sim models for core 7-series primitives.
| | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * | Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | |/ | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * / Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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* | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-1011-15/+15
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* | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
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* | RetryEddie Hung2019-04-051-1/+1
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* | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-052-7/+9
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* | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
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* xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
|\ | | | | iCE40 BRAM primitives init from file
| * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Add link to SF2 / igloo2 macro library guideClifford Wolf2019-03-071-21/+24
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improvements in sf2 cells_sim.vClifford Wolf2019-03-062-30/+251
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add sf2 techmap rules for more FF typesClifford Wolf2019-03-061-25/+39
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Refactor SF2 iobuf insertion, Add clkint insertionClifford Wolf2019-03-063-83/+152
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improvements in SF2 flow and demoClifford Wolf2019-03-052-8/+23
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
|\ \ | | | | | | Changes required for VPR place and route in synth_xilinx
| * | Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #850 from daveshah1/ecp5_warn_conflictClifford Wolf2019-03-051-2/+7
|\ \ \ | | | | | | | | ecp5: Demote conflicting FF init values to a warning
| * | | ecp5: Demote conflicting FF init values to a warningDavid Shah2019-03-041-2/+7
| |/ / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / / Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
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* | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
|\ \ | | | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
| * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| |/ | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net>
* | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-286-19/+19
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* | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
|\ \ | |/ |/| ECP5 Improvements
| * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
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