| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | | | | | | | | Special abc9_clock wire to contain only clock signal | Eddie Hung | 2019-11-25 | 1 | -12/+10 | |
| | * | | | | | | | | | | | | For abc9, run clkpart before ff_map and after abc9 | Eddie Hung | 2019-11-23 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+2 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 1 | -12/+16 | |
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| | | * | | | | | | | | | | | | | Do not drop async control signals in abc_map.v | Eddie Hung | 2019-11-19 | 1 | -12/+16 | |
| | * | | | | | | | | | | | | | | Add blackbox model for $__ABC9_FF_ so that clock partitioning works | Eddie Hung | 2019-11-20 | 1 | -0/+3 | |
| | * | | | | | | | | | | | | | | Fix INIT values | Eddie Hung | 2019-11-20 | 1 | -4/+4 | |
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 41 | -23094/+31993 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-08 | 1 | -5/+9 | |
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| | * | | | | | | | | | | | | | | | Cleanup | Eddie Hung | 2019-10-07 | 1 | -7/+2 | |
| | * | | | | | | | | | | | | | | | Rename $currQ to $abc9_currQ | Eddie Hung | 2019-10-07 | 1 | -46/+46 | |
| | * | | | | | | | | | | | | | | | Update comments in abc9_map.v | Eddie Hung | 2019-10-07 | 1 | -131/+57 | |
| | * | | | | | | | | | | | | | | | Remove -D_ABC9 | Eddie Hung | 2019-10-07 | 1 | -2/+0 | |
| | * | | | | | | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 4 | -230/+200 | |
| | * | | | | | | | | | | | | | | | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 | |
| | * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 4 | -181/+9 | |
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| | * | | | | | | | | | | | | | | | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 | |
| | * | | | | | | | | | | | | | | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -9/+10 | |
| | * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 31 | -278/+294 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 6 | -2/+184 | |
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| | * | | | | | | | | | | | | | | | | | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 | |
| | * | | | | | | | | | | | | | | | | | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 | |
| | * | | | | | | | | | | | | | | | | | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 | |
| | * | | | | | | | | | | | | | | | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 2 | -111/+118 | |
| | * | | | | | | | | | | | | | | | | | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 | |
| | * | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 8 | -124/+122 | |
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| | * | | | | | | | | | | | | | | | | | | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 | |
| | * | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 19 | -31/+3401 | |
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| | * | | | | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 6 | -295/+314 | |
| | * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 57 | -1594/+22196 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 6 | -17/+359 | |
| * | | | | | | | | | | | | | | | | | | | | | | | Fix DSP48E1 sim | Eddie Hung | 2020-01-06 | 1 | -3/+3 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-06 | 5 | -1653/+507 | |
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| | * | | | | | | | | | | | | | | | | | | | | | Wrap arrival functions inside `YOSYS too | Eddie Hung | 2020-01-06 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | Fix return value of arrival time functions, fix word | Eddie Hung | 2020-01-06 | 1 | -18/+14 | |
| | * | | | | | | | | | | | | | | | | | | | | | Drive $[ABCD] explicitly | Eddie Hung | 2020-01-02 | 1 | -15/+21 | |
| | * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-02 | 13 | -43/+43 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | ifndef __ICARUS__ -> ifdef YOSYS | Eddie Hung | 2020-01-01 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | | Rework abc9's DSP48E1 model | Eddie Hung | 2020-01-01 | 5 | -1656/+506 | |
| * | | | | | | | | | | | | | | | | | | | | | | Valid to have attribute starting with SB_CARRY. | Miodrag Milanovic | 2020-01-04 | 1 | -0/+2 | |
| * | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1604 from whitequark/unify-ram-naming | whitequark | 2020-01-02 | 18 | -40/+67 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|/ / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys. | whitequark | 2020-01-01 | 18 | -40/+67 | |
| * | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1601 from YosysHQ/eddie/synth_retime | Eddie Hung | 2020-01-02 | 12 | -37/+37 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 11 | -12/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Disable synth_gowin -abc9 as it offers no advantages yet | Eddie Hung | 2019-12-30 | 1 | -12/+12 | |
| | * | | | | | | | | | | | | | | | | | | | | | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 11 | -13/+13 | |
| * | | | | | | | | | | | | | | | | | | | | | | | ifdef __ICARUS__ -> ifndef YOSYS | Eddie Hung | 2020-01-01 | 1 | -6/+6 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Fix anlogic async flop mapping | Eddie Hung | 2020-01-01 | 1 | -8/+8 | |
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index : iCE40/yosys | |
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