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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:45:29 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 16:45:29 -0800 |
commit | 01866a79093092bc2f8a8b20376f6cb552f76f00 (patch) | |
tree | acbeaee73a4a27ffaee8ee82cbb36f2ced22e30a /techlibs | |
parent | 66698cb6fd0e33a27197b7412e094dc77363b5e5 (diff) | |
download | yosys-01866a79093092bc2f8a8b20376f6cb552f76f00.tar.gz yosys-01866a79093092bc2f8a8b20376f6cb552f76f00.tar.bz2 yosys-01866a79093092bc2f8a8b20376f6cb552f76f00.zip |
Fix DSP48E1 sim
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 1cd4d2f30..70ab1f293 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2388,8 +2388,8 @@ module DSP48E1 ( if (CEB2) Br2 <= Br1; end end else if (BREG == 1) begin - //initial Br1 = 25'b0; - initial Br2 = 25'b0; + //initial Br1 = 18'b0; + initial Br2 = 18'b0; always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; @@ -2436,7 +2436,7 @@ module DSP48E1 ( endgenerate // A/D input selection and pre-adder - wire signed [29:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; + wire signed [24:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); |