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* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-061-0/+10
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* Added WORDS parameter to $meminitClifford Wolf2015-07-311-1/+2
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* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-271-1/+0
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* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-201-20/+43
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* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-181-0/+2
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* Improved liberty file test caseClifford Wolf2015-07-061-1/+2
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* Added "synth -nofsm"Clifford Wolf2015-07-021-1/+10
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* Fixed trailing whitespacesClifford Wolf2015-07-0213-30/+30
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* iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-201-2/+2
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* Added "synth -nordff -noalumacc"Clifford Wolf2015-06-151-3/+20
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* synth_ice40 now flattens by defaultClifford Wolf2015-06-091-4/+8
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* Added iCE40 PLL cellsClifford Wolf2015-05-311-0/+168
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* Added output args to synth_ice40Clifford Wolf2015-05-262-2/+37
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* improved ice40 SB_IO sim modelClifford Wolf2015-05-231-16/+9
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* Added ice40 SB_IO sim modelClifford Wolf2015-05-231-1/+46
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* Verific build fixesClifford Wolf2015-05-172-4/+4
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* ice40_opt bugfixClifford Wolf2015-04-272-6/+4
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* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-271-3/+44
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* Added simplemap $lut supportClifford Wolf2015-04-271-8/+2
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* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-273-2/+134
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* Initialization support for all iCE40 bram modesClifford Wolf2015-04-268-28/+65
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* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-255-54/+261
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* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-251-59/+83
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* More iCE40 bram improvementsClifford Wolf2015-04-254-51/+69
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* iCE40 bram progressClifford Wolf2015-04-242-16/+35
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* iCE40 bram tests and fixesClifford Wolf2015-04-246-16/+181
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* Added ice40 bram supportClifford Wolf2015-04-244-1/+192
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* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-191-13/+289
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* added sync reset to ice40 test_ffs.shClifford Wolf2015-04-183-6/+20
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* Added ice40 test_arithClifford Wolf2015-04-182-0/+13
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* Added ice40 SB_CARRY supportClifford Wolf2015-04-183-2/+81
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* Added mapping of synchronous set/reset to iCE40 flowClifford Wolf2015-04-173-4/+130
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* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-161-2/+2
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* Fixed "dff2dffe -direct-match"Clifford Wolf2015-04-161-0/+2
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* Added simple ice40 dff testsClifford Wolf2015-04-163-0/+49
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* improved ice40 dff cell mappingClifford Wolf2015-04-163-7/+46
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* use "hierarchy -auto-top" in synth_ice40Clifford Wolf2015-04-141-3/+3
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* more cells in ice40 cell libraryClifford Wolf2015-04-141-8/+289
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* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
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* Added memory_bram "make_outreg" featureClifford Wolf2015-04-091-0/+2
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* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-093-13/+67
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* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
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* Added support for initialized xilinx bramsClifford Wolf2015-04-0610-91/+314
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* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
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* Added Xilinx bram black-box modulesClifford Wolf2015-04-063-0/+322
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* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-051-6/+6
| | | | | | this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-051-0/+29
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* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-5/+6
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* Fixes in cmos_cells.vClifford Wolf2015-03-251-3/+12
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* Added very first version of "synth_ice40"Clifford Wolf2015-03-054-0/+211
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