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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-27 22:44:01 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-27 22:44:01 +0200 |
| commit | 516e8828f2e1175b449e45879d19d20e080e2398 (patch) | |
| tree | b55387494d6945ab65288e3beafe42a891fa5736 /techlibs | |
| parent | 4d0ba9b3b27d507ba032bdc1a4bcbf63e2581336 (diff) | |
| download | yosys-516e8828f2e1175b449e45879d19d20e080e2398.tar.gz yosys-516e8828f2e1175b449e45879d19d20e080e2398.tar.bz2 yosys-516e8828f2e1175b449e45879d19d20e080e2398.zip | |
Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index b7a196602..d7e1f9afa 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -460,7 +460,6 @@ module SB_RAM40_4K ( if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13]; if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14]; if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15]; - if (!WMASK_I[16]) memory[WADDR[7:0]][16] <= WDATA_I[16]; end end |