| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor | Eddie Hung | 2020-01-02 | 12 | -756/+722 |
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| | * | synth_xilinx -dff to work with abc too | Eddie Hung | 2020-01-02 | 1 | -6/+14 |
| | * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 14 | -66/+86 |
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| | * | | Update comments | Eddie Hung | 2020-01-02 | 1 | -11/+6 |
| | * | | abc9 -keepff -> -dff; refactor dff operations | Eddie Hung | 2020-01-02 | 2 | -58/+58 |
| | * | | Clamp -46ps for FDPE* too | Eddie Hung | 2020-01-01 | 1 | -2/+2 |
| | * | | Restore abc9 -keepff | Eddie Hung | 2020-01-01 | 2 | -86/+6 |
| | * | | Re-arrange FD order | Eddie Hung | 2019-12-31 | 3 | -182/+182 |
| | * | | Missing character | Eddie Hung | 2019-12-31 | 1 | -1/+1 |
| | * | | Cleanup xilinx boxes | Eddie Hung | 2019-12-31 | 2 | -391/+425 |
| | * | | Cleanup ice40 boxes | Eddie Hung | 2019-12-31 | 3 | -30/+43 |
| | * | | Cleanup ecp5 boxes | Eddie Hung | 2019-12-31 | 4 | -35/+31 |
| | * | | Update abc9_xc7.box comments | Eddie Hung | 2019-12-31 | 1 | -18/+18 |
| | * | | FDCE ports to be alphabetical | Eddie Hung | 2019-12-31 | 1 | -3/+3 |
| | * | | Fix attributes on $__ABC9_ASYNC[01] whitebox | Eddie Hung | 2019-12-31 | 1 | -2/+2 |
| | * | | Fix incorrect $__ABC9_ASYNC[01] box | Eddie Hung | 2019-12-31 | 1 | -2/+2 |
| * | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2020-01-02 | 27 | -91/+118 |
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| | * \ \ | Merge pull request #1604 from whitequark/unify-ram-naming | whitequark | 2020-01-02 | 18 | -40/+67 |
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| | | * | | Harmonize BRAM/LUTRAM descriptions across all of Yosys. | whitequark | 2020-01-01 | 18 | -40/+67 |
| | * | | | Merge pull request #1601 from YosysHQ/eddie/synth_retime | Eddie Hung | 2020-01-02 | 12 | -37/+37 |
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| | | * | | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 11 | -12/+12 |
| | | * | | | Disable synth_gowin -abc9 as it offers no advantages yet | Eddie Hung | 2019-12-30 | 1 | -12/+12 |
| | | * | | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 11 | -13/+13 |
| | * | | | | ifdef __ICARUS__ -> ifndef YOSYS | Eddie Hung | 2020-01-01 | 1 | -6/+6 |
| | * | | | | Fix anlogic async flop mapping | Eddie Hung | 2020-01-01 | 1 | -8/+8 |
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| * | | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor | Eddie Hung | 2019-12-30 | 6 | -121/+673 |
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| | * | | Do not offset FD* box timings due to -46ps Tsu | Eddie Hung | 2019-12-30 | 1 | -12/+21 |
| | * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 10 | -32/+377 |
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| | * | | | Tidy up abc9_map.v | Eddie Hung | 2019-12-30 | 1 | -103/+103 |
| | * | | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 2 | -2/+98 |
| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
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| | * \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 4 | -172/+240 |
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| | * | | | | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-19 | 1 | -0/+78 |
| | * | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 5 | -36/+55 |
| | * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 14 | -81/+995 |
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| | * \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 13 | -30/+32 |
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| | * | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 |
| | * | | | | | | | Fix comment | Eddie Hung | 2019-12-09 | 1 | -1/+1 |
| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 7 | -745/+1138 |
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| | * | | | | | | | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 |
| | * | | | | | | | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 |
| | * | | | | | | | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 |
| | * | | | | | | | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 |
| | * | | | | | | | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 |
| | * | | | | | | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 1 | -118/+201 |
| | * | | | | | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 |
| | * | | | | | | | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 |
| | * | | | | | | | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 |
| | * | | | | | | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 |
| | * | | | | | | | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 |
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index : iCE40/yosys | |
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